From nobody Fri Dec 19 19:07:33 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E94881A4340; Sun, 24 Mar 2024 22:43:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711320201; cv=none; b=s6QhVihyO1a2kIhMT0bsBqrRoXxMuJ/If+ME06e82g7bDBInPVPLQyDcVyGq8l9V4YHTt7g3zzvvytobnzRRuqkRKz54z36/Jt1cmwkn6FY3zhxqxXMJi6zdkTFXN+k7BbaCp3SW1rayb3wNoNmenANB89YqpolUM5nPfF9XtQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711320201; c=relaxed/simple; bh=+SChueW4aiGDhNe28gOu9r+rnNWL+FfG6Vdr3Jg0dsE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OfXNhIIpKQi6riaHZQ5/tXyxvg+M/M31pgMpgAt8OXUgRLxFh1Ha9Wy/nHgusCcJtDAINzlPK4qp6POdU2IjzkEEm3mtTdhsHOvyWg1YxTek6JcCNDj6e0iVrSzi1+CYx2yK/5dGSCyS1J/EyVNNjeL9gXMWrh9NAu1EMdeMXfY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AW4f14tJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AW4f14tJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3608EC43390; Sun, 24 Mar 2024 22:43:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711320200; bh=+SChueW4aiGDhNe28gOu9r+rnNWL+FfG6Vdr3Jg0dsE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AW4f14tJvdd6lIU/jBMVXkZvIMQd3qWNF8YbSdtMhkbA0YXjgVYKy6ShkOLQe1nFH +8ad4uk2tl2lXydSjms5lQegtAJNpDEoHIGdDqKiN3t2Vot2eOL6Rf/5e9xGFeHOa/ dtGvdxCe3xokUh2Yz6ePQu0Mg3N4JzUp34nvGOpp183GOsu8eqVnoS/QKlJ/8K4N8u zWRq4Q7fdYU6SydG7CVw8xhXXLu+bFsJq7rRt2VpIdhXR54MtGgGbPMllOpPFBvfKs E0KZLgTU+jIX4SyWzevZTTCdMNIaVGy2P0vyaVaRhQfdBXpzc/QI2bkhFhEJ8nv235 +8v4+tfNPNv6Q== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Paloma Arellano , Dmitry Baryshkov , Sasha Levin Subject: [PATCH 6.8 508/715] drm/msm/dpu: add division of drm_display_mode's hskew parameter Date: Sun, 24 Mar 2024 18:31:27 -0400 Message-ID: <20240324223455.1342824-509-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324223455.1342824-1-sashal@kernel.org> References: <20240324223455.1342824-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paloma Arellano [ Upstream commit 551ee0f210991d25f336bc27262353bfe99d3eed ] Setting up the timing engine when the physical encoder has a split role neglects dividing the drm_display_mode's hskew parameter. Let's fix this since this must also be done in preparation for implementing YUV420 over DP. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579605/ Link: https://lore.kernel.org/r/20240222194025.25329-3-quic_parellan@quicin= c.com Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index f562beb6f7971..f02411b062c4c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -260,12 +260,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine( mode.htotal >>=3D 1; mode.hsync_start >>=3D 1; mode.hsync_end >>=3D 1; + mode.hskew >>=3D 1; =20 DPU_DEBUG_VIDENC(phys_enc, - "split_role %d, halve horizontal %d %d %d %d\n", + "split_role %d, halve horizontal %d %d %d %d %d\n", phys_enc->split_role, mode.hdisplay, mode.htotal, - mode.hsync_start, mode.hsync_end); + mode.hsync_start, mode.hsync_end, + mode.hskew); } =20 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); --=20 2.43.0