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[2a01:c22:6fc3:1a00::e63]) by smtp.googlemail.com with ESMTPSA id h10-20020a170906590a00b00a46196a7faesm1375116ejq.57.2024.03.23.16.13.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Mar 2024 16:13:21 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, gnstark@salutedevices.com, neil.armstrong@linaro.org, lars@metafoo.de, jic23@kernel.org, Martin Blumenstingl Subject: [PATCH v1 3/3] iio: adc: meson: simplify MESON_SAR_ADC_REG11 register access Date: Sun, 24 Mar 2024 00:13:09 +0100 Message-ID: <20240323231309.415425-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240323231309.415425-1-martin.blumenstingl@googlemail.com> References: <20240323231309.415425-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simply check the max_register value to decide whether MESON_SAR_ADC_REG11 is present on the current IP revision. This allows dropping two additional bool fields from struct meson_sar_adc_param which previously had to be manually kept in sync. No functional changes intended. Signed-off-by: Martin Blumenstingl --- drivers/iio/adc/meson_saradc.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 6b2af0c2bbc7..8c1e542c0ab7 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -320,14 +320,12 @@ static const struct iio_chan_spec meson_sar_adc_and_t= emp_iio_channels[] =3D { struct meson_sar_adc_param { bool has_bl30_integration; unsigned long clock_rate; - u32 bandgap_reg; unsigned int resolution; const struct regmap_config *regmap_config; u8 temperature_trimming_bits; unsigned int temperature_multiplier; unsigned int temperature_divider; bool disable_ring_counter; - bool has_reg11; bool has_vref_select; bool cmv_select; bool adc_eoc; @@ -995,7 +993,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN, regval); =20 - if (priv->param->has_reg11) { + if (priv->param->regmap_config->max_register >=3D MESON_SAR_ADC_REG11) { regval =3D priv->param->adc_eoc ? MESON_SAR_ADC_REG11_EOC : 0; regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, MESON_SAR_ADC_REG11_EOC, regval); @@ -1031,16 +1029,15 @@ static int meson_sar_adc_init(struct iio_dev *indio= _dev) static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_o= ff) { struct meson_sar_adc_priv *priv =3D iio_priv(indio_dev); - const struct meson_sar_adc_param *param =3D priv->param; - u32 enable_mask; =20 - if (param->bandgap_reg =3D=3D MESON_SAR_ADC_REG11) - enable_mask =3D MESON_SAR_ADC_REG11_BANDGAP_EN; + if (priv->param->regmap_config->max_register >=3D MESON_SAR_ADC_REG11) + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, + MESON_SAR_ADC_REG11_BANDGAP_EN, + on_off ? MESON_SAR_ADC_REG11_BANDGAP_EN : 0); else - enable_mask =3D MESON_SAR_ADC_DELTA_10_TS_VBG_EN; - - regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask, - on_off ? enable_mask : 0); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TS_VBG_EN, + on_off ? MESON_SAR_ADC_DELTA_10_TS_VBG_EN : 0); } =20 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) @@ -1205,7 +1202,6 @@ static const struct iio_info meson_sar_adc_iio_info = =3D { static const struct meson_sar_adc_param meson_sar_adc_meson8_param =3D { .has_bl30_integration =3D false, .clock_rate =3D 1150000, - .bandgap_reg =3D MESON_SAR_ADC_DELTA_10, .regmap_config =3D &meson_sar_adc_regmap_config_meson8, .resolution =3D 10, .temperature_trimming_bits =3D 4, @@ -1216,7 +1212,6 @@ static const struct meson_sar_adc_param meson_sar_adc= _meson8_param =3D { static const struct meson_sar_adc_param meson_sar_adc_meson8b_param =3D { .has_bl30_integration =3D false, .clock_rate =3D 1150000, - .bandgap_reg =3D MESON_SAR_ADC_DELTA_10, .regmap_config =3D &meson_sar_adc_regmap_config_meson8, .resolution =3D 10, .temperature_trimming_bits =3D 5, @@ -1227,10 +1222,8 @@ static const struct meson_sar_adc_param meson_sar_ad= c_meson8b_param =3D { static const struct meson_sar_adc_param meson_sar_adc_gxbb_param =3D { .has_bl30_integration =3D true, .clock_rate =3D 1200000, - .bandgap_reg =3D MESON_SAR_ADC_REG11, .regmap_config =3D &meson_sar_adc_regmap_config_gxbb, .resolution =3D 10, - .has_reg11 =3D true, .vref_voltage =3D VREF_VOLTAGE_1V8, .cmv_select =3D true, }; @@ -1238,11 +1231,9 @@ static const struct meson_sar_adc_param meson_sar_ad= c_gxbb_param =3D { static const struct meson_sar_adc_param meson_sar_adc_gxl_param =3D { .has_bl30_integration =3D true, .clock_rate =3D 1200000, - .bandgap_reg =3D MESON_SAR_ADC_REG11, .regmap_config =3D &meson_sar_adc_regmap_config_gxbb, .resolution =3D 12, .disable_ring_counter =3D 1, - .has_reg11 =3D true, .vref_voltage =3D VREF_VOLTAGE_1V8, .cmv_select =3D true, }; @@ -1250,11 +1241,9 @@ static const struct meson_sar_adc_param meson_sar_ad= c_gxl_param =3D { static const struct meson_sar_adc_param meson_sar_adc_axg_param =3D { .has_bl30_integration =3D true, .clock_rate =3D 1200000, - .bandgap_reg =3D MESON_SAR_ADC_REG11, .regmap_config =3D &meson_sar_adc_regmap_config_gxbb, .resolution =3D 12, .disable_ring_counter =3D 1, - .has_reg11 =3D true, .vref_voltage =3D VREF_VOLTAGE_1V8, .has_vref_select =3D true, .vref_select =3D VREF_VDDA, @@ -1264,11 +1253,9 @@ static const struct meson_sar_adc_param meson_sar_ad= c_axg_param =3D { static const struct meson_sar_adc_param meson_sar_adc_g12a_param =3D { .has_bl30_integration =3D false, .clock_rate =3D 1200000, - .bandgap_reg =3D MESON_SAR_ADC_REG11, .regmap_config =3D &meson_sar_adc_regmap_config_gxbb, .resolution =3D 12, .disable_ring_counter =3D 1, - .has_reg11 =3D true, .vref_voltage =3D VREF_VOLTAGE_0V9, .adc_eoc =3D true, .has_vref_select =3D true, --=20 2.44.0