From nobody Sun Feb 8 07:14:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19FC260894 for ; Fri, 22 Mar 2024 17:56:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711130194; cv=none; b=PJmtF2Ql9UKI+KY4kK36KqaazVsmhBSJdbsb1cML7adBNTGn5BBFRsm0rKMKecUauiFyf1KbtySzB1wafTusksSzdmHP13CsNEmySTwMrUmH2JxyU5Tr/ux2v22rhzhEXFkoYQlNOY1q2nFQxYtnMVv7apS6MfLr+1bHhNuNMbg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711130194; c=relaxed/simple; bh=zpniM12Plr/IbgqsKzUJwGxiwaeLzWobVxGgT3mo4kk=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=btbH+a3N+BVVwrx1pWTF96BRK/7VRSuZups3un3ABepzKqbefDoIRzf4rrdWT4Z0wt/FI/maoyaJJzd2LZ+MbdefYhAmbG1rmkKnNrWS3DCqxKxfBo16d5m2mKCS56euY/uI07ytIKfHyVg13iOnfJylddynHLFwFqhmsE+UUbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Hg0oIPa3; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Hg0oIPa3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711130193; x=1742666193; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=zpniM12Plr/IbgqsKzUJwGxiwaeLzWobVxGgT3mo4kk=; b=Hg0oIPa3kT9l1QWxL61BZfhiYwiC+RdYu5X3zuYZjcBUkFpDnvUI3+C/ HeU8tNzYDwRG7UI5m8qXBSZsbbcQDL3U29zwttp26Fu75p0TN5tB5xMs+ pB2jWKSGoGuwhKpseTUp+Bn7tMyZM+YIfRv3DAHyBgZTe2XNoyiOny1Ud FtHYN2i3Kc2rnrsr0iex8n0SRxXuoo4sImmf7++N/zcqgJlezp5si/wDG QS0n4xkMUHI+9l7rdXCYgDyB7OhtammThgCtQwEujYtNMg0j8cqC0Yibs XpyI0Gjlv7J95HQFYNMLhzT8hrwE7mV+/lquhke+6iXFHmfqFwsJK0ABd Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="28669679" X-IronPort-AV: E=Sophos;i="6.07,146,1708416000"; d="scan'208";a="28669679" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 10:56:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,146,1708416000"; d="scan'208";a="15425569" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa006.jf.intel.com with ESMTP; 22 Mar 2024 10:56:31 -0700 Subject: [PATCH 1/4] x86/cpu: Add and use new CPUID region helper To: linux-kernel@vger.kernel.org Cc: jgross@suse.com,tglx@linutronix.de,x86@kernel.org,bp@alien8.de,Dave Hansen From: Dave Hansen Date: Fri, 22 Mar 2024 10:56:30 -0700 References: <20240322175629.01E8B39D@davehans-spike.ostc.intel.com> In-Reply-To: <20240322175629.01E8B39D@davehans-spike.ostc.intel.com> Message-Id: <20240322175630.72CE974F@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen There are some (before now) unwritten rules about CPUID "regions". Basically, there is a 32-bit address space of CPUID leaves. The top 16 bits address a "region" and the first leaf in a region is special. The kernel only has a few spots that care about this, but it's rather hard to make sense of the code as is. Add a helper that explains regions. Use it where applicable. Signed-off-by: Dave Hansen Cc: Juergen Gross Reviewed-by: Kai Huang --- b/arch/x86/include/asm/cpuid.h | 59 +++++++++++++++++++++++++++++++++= +++++ b/arch/x86/kernel/cpu/common.c | 13 +++----- b/arch/x86/kernel/cpu/transmeta.c | 9 +---- b/arch/x86/xen/enlighten_pv.c | 9 +---- 4 files changed, 69 insertions(+), 21 deletions(-) diff -puN arch/x86/include/asm/cpuid.h~cpuid-regions arch/x86/include/asm/c= puid.h --- a/arch/x86/include/asm/cpuid.h~cpuid-regions 2024-03-18 15:12:20.676308= 753 -0700 +++ b/arch/x86/include/asm/cpuid.h 2024-03-22 09:17:13.296507986 -0700 @@ -168,4 +168,63 @@ static inline uint32_t hypervisor_cpuid_ return 0; } =20 +/* + * By convention, CPUID is broken up into regions which each + * have 2^16 leaves. EAX in the first leaf of each valid + * region returns the maximum valid leaf in that region. + * + * The regions can be thought of as being vendor-specific + * areas of CPUID, but that's imprecise because everybody + * implements the "Intel" region and Intel implements the + * AMD region. There are a few well-known regions: + * - Intel (0x0000) + * - AMD (0x8000) + * - Transmeta (0x8086) + * - Centaur (0xC000) + * + * Consider a CPU that where the maximum leaf in the Transmeta + * region is 2. On such a CPU, leaf 0x80860000 would contain: + * EAX=3D=3D0x80860002. + * region-^^^^ + * max leaf-^^^^ + */ +static inline u32 cpuid_region_max_leaf(u16 region) +{ + u32 eax =3D cpuid_eax(region << 16); + + /* + * An unsupported region may return data from the last + * "basic" leaf, which is essentially garbage. Avoid + * mistaking basic leaf data for region data. + * + * Note: this is not perfect. It is theoretically + * possible for the last basic leaf to _resemble_ a + * valid first leaf from a region that doesn't exist. + * But Intel at least seems to pad out the basic region + * with 0's, possibly to avoid this. + */ + if ((eax >> 16) !=3D region) + return 0; + + return eax; +} + +/* Returns true if the leaf exists and @value was populated */ +static inline bool get_cpuid_region_leaf(u32 leaf, enum cpuid_regs_idx reg, + u32 *value) +{ + u16 region =3D leaf >> 16; + u32 regs[4]; + + if (cpuid_region_max_leaf(region) < leaf) + return false; + + cpuid(leaf, ®s[CPUID_EAX], ®s[CPUID_EBX], + ®s[CPUID_ECX], ®s[CPUID_EDX]); + + *value =3D regs[reg]; + + return true; +} + #endif /* _ASM_X86_CPUID_H */ diff -puN arch/x86/kernel/cpu/common.c~cpuid-regions arch/x86/kernel/cpu/co= mmon.c --- a/arch/x86/kernel/cpu/common.c~cpuid-regions 2024-03-18 15:12:20.676308= 753 -0700 +++ b/arch/x86/kernel/cpu/common.c 2024-03-18 15:12:20.684309023 -0700 @@ -1049,16 +1049,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c) } =20 /* AMD-defined flags: level 0x80000001 */ - eax =3D cpuid_eax(0x80000000); - c->extended_cpuid_level =3D eax; + c->extended_cpuid_level =3D cpuid_region_max_leaf(0x8000); =20 - if ((eax & 0xffff0000) =3D=3D 0x80000000) { - if (eax >=3D 0x80000001) { - cpuid(0x80000001, &eax, &ebx, &ecx, &edx); + if (c->extended_cpuid_level >=3D 0x80000001) { + cpuid(0x80000001, &eax, &ebx, &ecx, &edx); =20 - c->x86_capability[CPUID_8000_0001_ECX] =3D ecx; - c->x86_capability[CPUID_8000_0001_EDX] =3D edx; - } + c->x86_capability[CPUID_8000_0001_ECX] =3D ecx; + c->x86_capability[CPUID_8000_0001_EDX] =3D edx; } =20 if (c->extended_cpuid_level >=3D 0x80000007) { diff -puN arch/x86/kernel/cpu/transmeta.c~cpuid-regions arch/x86/kernel/cpu= /transmeta.c --- a/arch/x86/kernel/cpu/transmeta.c~cpuid-regions 2024-03-18 15:12:20.680= 308889 -0700 +++ b/arch/x86/kernel/cpu/transmeta.c 2024-03-18 15:12:20.684309023 -0700 @@ -9,14 +9,9 @@ =20 static void early_init_transmeta(struct cpuinfo_x86 *c) { - u32 xlvl; - /* Transmeta-defined flags: level 0x80860001 */ - xlvl =3D cpuid_eax(0x80860000); - if ((xlvl & 0xffff0000) =3D=3D 0x80860000) { - if (xlvl >=3D 0x80860001) - c->x86_capability[CPUID_8086_0001_EDX] =3D cpuid_edx(0x80860001); - } + get_cpuid_region_leaf(0x80860001, CPUID_EDX, + &c->x86_capability[CPUID_8086_0001_EDX]); } =20 static void init_transmeta(struct cpuinfo_x86 *c) diff -puN arch/x86/xen/enlighten_pv.c~cpuid-regions arch/x86/xen/enlighten_= pv.c --- a/arch/x86/xen/enlighten_pv.c~cpuid-regions 2024-03-18 15:12:20.6803088= 89 -0700 +++ b/arch/x86/xen/enlighten_pv.c 2024-03-22 09:15:33.280428290 -0700 @@ -141,16 +141,13 @@ static void __init xen_set_mtrr_data(voi }; unsigned int reg; unsigned long mask; - uint32_t eax, width; + uint32_t width; static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; =20 /* Get physical address width (only 64-bit cpus supported). */ width =3D 36; - eax =3D cpuid_eax(0x80000000); - if ((eax >> 16) =3D=3D 0x8000 && eax >=3D 0x80000008) { - eax =3D cpuid_eax(0x80000008); - width =3D eax & 0xff; - } + /* Will overwrite 'width' if available in CPUID: */ + get_cpuid_region_leaf(0x80000008, CPUID_EAX, &width); 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charset="utf-8" From: Dave Hansen IBS details are enumerated in an extended CPUID leaf. But the support has an open-coded CPUID region check. Use the new helper to trim down the code. Signed-off-by: Dave Hansen -- Note: this cleanup could take another form: if (boot_cpu_data->extended_cpuid_level >=3D IBS_CPUID_FEATURES) caps =3D cpuid_eax(IBS_CPUID_FEATURES); that would be one fewer CPUID invocations, but one more line of code. --- b/arch/x86/events/amd/ibs.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff -puN arch/x86/events/amd/ibs.c~ibs-region-helpers arch/x86/events/amd/= ibs.c --- a/arch/x86/events/amd/ibs.c~ibs-region-helpers 2024-03-18 15:12:21.2283= 27350 -0700 +++ b/arch/x86/events/amd/ibs.c 2024-03-18 15:12:21.228327350 -0700 @@ -1278,18 +1278,13 @@ static __init int perf_event_ibs_init(vo =20 static __init u32 __get_ibs_caps(void) { - u32 caps; - unsigned int max_level; + u32 caps =3D 0; =20 if (!boot_cpu_has(X86_FEATURE_IBS)) return 0; =20 - /* check IBS cpuid feature flags */ - max_level =3D cpuid_eax(0x80000000); - if (max_level < IBS_CPUID_FEATURES) - return IBS_CAPS_DEFAULT; + get_cpuid_region_leaf(IBS_CPUID_FEATURES, CPUID_EAX, &caps); =20 - caps =3D cpuid_eax(IBS_CPUID_FEATURES); if (!(caps & IBS_CAPS_AVAIL)) /* cpuid flags not valid */ return IBS_CAPS_DEFAULT; _ From nobody Sun Feb 8 07:14:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A8E360BA7 for ; Fri, 22 Mar 2024 17:56:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711130196; cv=none; b=sP4xDPqg7XYUB3kUYro4PHIKs0MZSFvWXDz4OcJTfxYO8nn97jg7uT82dIp2n6DLbya0rBlfIJuFdF2XZTZBP3eNkOh32bEPgJ/L+a5Cf+EACEvhP8qkH0gnnE+VdOWkaw/wHJN0S2NJLWC/TXj7V6VuPYvM9PIDS+WCqC9AqR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711130196; c=relaxed/simple; bh=R39FNwAEvPrsTrN8h1zduBan957TEM8t3B4Ef3RYhjk=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=S/wjkz4j8iQ5E7Cq2dBEfdArmN7gmzKSs1+mkYFmu0xlLZB6+7cXg/VTbKDUuEMdm0vdMu9wINcdmibyD2P8jTLw4IgGdL5NjXL4BLQLE6KnZ+PpMkOfLM+G0t1BIO/mF3Lgdxhu8SfI32ERizmJD+WvRPHNGP9ay4nh0S/U8zs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RCpArUNq; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RCpArUNq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711130195; x=1742666195; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=R39FNwAEvPrsTrN8h1zduBan957TEM8t3B4Ef3RYhjk=; b=RCpArUNqIHcpJusg6vT1mP/0XSho8C7dxfE4OZ7k2OkeFOD/3feCiDJX qWEmNllSwbh0TEr9Ci3/CprAp2zGyEQsoPnVrXJb6uhKtSTLjAgYcjw2j zPp8sQN4K4H9/wVgNpn3o3p83vvWNZoGShvNaBuip3Qqh/phfvzPErrJg T9EJpBcC5soMyFRh44Dcyl1HhoFLjd7QrSsaZ40bpN4+52YrWhWrzzdlm cx1jIAo8FzAMuBJtjQFl4eSCPmPShdNDCeH+GdgBR1LgkNnpjsQr0gJql 9YA4Z5uAM4aHpe0BUoRgsoFX/egaZGALONCMPwGBG6I6ty+oGVX3m1phb Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="28669703" X-IronPort-AV: E=Sophos;i="6.07,146,1708416000"; d="scan'208";a="28669703" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 10:56:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,146,1708416000"; d="scan'208";a="15425575" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa006.jf.intel.com with ESMTP; 22 Mar 2024 10:56:34 -0700 Subject: [PATCH 3/4] x86/boot: Explicitly pass NX enabling status To: linux-kernel@vger.kernel.org Cc: jgross@suse.com,tglx@linutronix.de,x86@kernel.org,bp@alien8.de,Dave Hansen From: Dave Hansen Date: Fri, 22 Mar 2024 10:56:33 -0700 References: <20240322175629.01E8B39D@davehans-spike.ostc.intel.com> In-Reply-To: <20240322175629.01E8B39D@davehans-spike.ostc.intel.com> Message-Id: <20240322175633.1CF5EB0E@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The kernel sometimes needs to mask unsupported bits out of page table entries. It does that with a mask: '__supported_pte_mask'. That mask can obviously only contain the No-eXecute bit ( _PAGE_NX) on hardware where NX is supported. x86_configure_nx() checks the boot CPU's NX support and adjusts the mask appropriately. But it doesn't check support directly. It uses the venerable 'boot_cpu_data' which is a software approximation of the actual CPU support. Unfortunately, Xen wants to set up '__supported_pte_mask' before 'boot_cpu_data' has been initialized. It hacks around this problem by repeating some of the 'boot_cpu_data' setup *just* for NX. Have x86_configure_nx() stop consulting 'boot_cpu_data' and move the NX detection to the caller. No functional change. That will come later. Signed-off-by: Dave Hansen Reviewed-by: Kai Huang --- b/arch/x86/include/asm/proto.h | 2 +- b/arch/x86/kernel/setup.c | 6 +++--- b/arch/x86/xen/enlighten_pv.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff -puN arch/x86/include/asm/proto.h~x86_configure_nx-arg arch/x86/includ= e/asm/proto.h --- a/arch/x86/include/asm/proto.h~x86_configure_nx-arg 2024-03-18 15:12:21= .704343388 -0700 +++ b/arch/x86/include/asm/proto.h 2024-03-18 15:12:21.708343524 -0700 @@ -37,7 +37,7 @@ void entry_SYSRETL_compat_end(void); #define entry_SYSENTER_compat NULL #endif =20 -void x86_configure_nx(void); +void x86_configure_nx(bool nx_supported); =20 extern int reboot_force; =20 diff -puN arch/x86/kernel/setup.c~x86_configure_nx-arg arch/x86/kernel/setu= p.c --- a/arch/x86/kernel/setup.c~x86_configure_nx-arg 2024-03-18 15:12:21.7043= 43388 -0700 +++ b/arch/x86/kernel/setup.c 2024-03-18 15:12:21.708343524 -0700 @@ -687,9 +687,9 @@ dump_kernel_offset(struct notifier_block return 0; } =20 -void x86_configure_nx(void) +void x86_configure_nx(bool nx_supported) { - if (boot_cpu_has(X86_FEATURE_NX)) + if (nx_supported) __supported_pte_mask |=3D _PAGE_NX; else __supported_pte_mask &=3D ~_PAGE_NX; @@ -853,7 +853,7 @@ void __init setup_arch(char **cmdline_p) * whether hardware doesn't support NX (so that the early EHCI debug * console setup can safely call set_fixmap()). */ - x86_configure_nx(); + x86_configure_nx(boot_cpu_has(X86_FEATURE_NX)); =20 parse_early_param(); =20 diff -puN arch/x86/xen/enlighten_pv.c~x86_configure_nx-arg arch/x86/xen/enl= ighten_pv.c --- a/arch/x86/xen/enlighten_pv.c~x86_configure_nx-arg 2024-03-18 15:12:21.= 704343388 -0700 +++ b/arch/x86/xen/enlighten_pv.c 2024-03-18 15:12:21.708343524 -0700 @@ -1371,7 +1371,7 @@ asmlinkage __visible void __init xen_sta =20 /* Work out if we support NX */ get_cpu_cap(&boot_cpu_data); - x86_configure_nx(); + x86_configure_nx(boot_cpu_has(X86_FEATURE_NX)); =20 /* * Set up kernel GDT and segment registers, mainly so that _ From nobody Sun Feb 8 07:14:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72D3F60DC4 for ; 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a="28669710" X-IronPort-AV: E=Sophos;i="6.07,146,1708416000"; d="scan'208";a="28669710" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 10:56:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,146,1708416000"; d="scan'208";a="15425579" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by orviesa006.jf.intel.com with ESMTP; 22 Mar 2024 10:56:35 -0700 Subject: [PATCH 4/4] x86/xen: Enumerate NX from CPUID directly To: linux-kernel@vger.kernel.org Cc: jgross@suse.com,tglx@linutronix.de,x86@kernel.org,bp@alien8.de,Dave Hansen From: Dave Hansen Date: Fri, 22 Mar 2024 10:56:34 -0700 References: <20240322175629.01E8B39D@davehans-spike.ostc.intel.com> In-Reply-To: <20240322175629.01E8B39D@davehans-spike.ostc.intel.com> Message-Id: <20240322175634.80024377@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen xen_start_kernel() is some of the first C code run "Xen PV" systems. It precedes things like setup_arch() or processor initialization code that would be thought of as "very early". That means that 'boot_cpu_data' is garbage. It has not even established the utter basics like if the CPU supports the CPUID instruction. Unfortunately get_cpu_cap() requires this exact information. Nevertheless, xen_start_kernel() calls get_cpu_cap(). But it works out in practice because it's looking for the NX bit which comes from an extended CPUID leaf that doesn't depend on c->cpuid_level being set. Stop calling get_cpu_cap(). Use CPUID directly. Add a little helper to avoid cluttering up the xen_start_kernel() flow. This removes the risky, barely-working call to get_cpu_cap(). Note: The '& 31' strips the "capability" word off of an X86_FEATURE_* value. It's a magic number, but there are a few of them sparsely scattered around and it's way shorter than any helper. Signed-off-by: Dave Hansen Cc: Juergen Gross --- b/arch/x86/xen/enlighten_pv.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff -puN arch/x86/xen/enlighten_pv.c~xen-explain1 arch/x86/xen/enlighten_p= v.c --- a/arch/x86/xen/enlighten_pv.c~xen-explain1 2024-03-22 09:30:25.49989261= 4 -0700 +++ b/arch/x86/xen/enlighten_pv.c 2024-03-22 09:30:25.503892742 -0700 @@ -1306,6 +1306,21 @@ static void __init xen_domu_set_legacy_f =20 extern void early_xen_iret_patch(void); =20 +/* + * It is too early for boot_cpu_has() and friends to work. + * Use CPUID to directly enumerate NX support. + */ +static inline void xen_configure_nx(void) +{ + bool nx_supported; + u32 eax =3D 0; + + get_cpuid_region_leaf(0x80000001, CPUID_EDX, &eax); + + nx_supported =3D eax & (X86_FEATURE_NX & 31); + x86_configure_nx(nx_supported); +} + /* First C function to be called on Xen boot */ asmlinkage __visible void __init xen_start_kernel(struct start_info *si) { @@ -1369,9 +1384,7 @@ asmlinkage __visible void __init xen_sta /* Get mfn list */ xen_build_dynamic_phys_to_machine(); =20 - /* Work out if we support NX */ - get_cpu_cap(&boot_cpu_data); - x86_configure_nx(boot_cpu_has(X86_FEATURE_NX)); + xen_configure_nx(); =20 /* * Set up kernel GDT and segment registers, mainly so that _