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Lin" , Fei Shao , Sean Paul , Jason Chen , , , , , "Hsiao Chien Sung" Subject: [PATCH v6 09/14] drm/mediatek: Support "Pre-multiplied" alpha blending in Mixer Date: Fri, 22 Mar 2024 13:28:24 +0800 Message-ID: <20240322052829.9893-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240322052829.9893-1-shawn.sung@mediatek.com> References: <20240322052829.9893-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.610000-8.000000 X-TMASE-MatchedRID: zNyJSLgyXoKp2D+ysBQGebxygpRxo4693KXiaLjnK32vloAnGr4qhglh 29MaPxbmZKE0ERpSKdRmWak1/EAxtADNPxu11HXjhK8o4aoss8rTDXgcUlCNow2Y8xyy93kWQkz RZrI7fzZdrC9Pth1iYg2D76bNs2ltQF24kZp9Ww91e7Xbb6Im2greImldQ5BD8cWgFw6wp7MsX2 NvG8rX7UT88A7P9JJ2gAYZl0IbohgfE8yM4pjsDwtuKBGekqUpI/NGWt0UYPCB43xWfKawlupLM z1pj71LYuxt2qKukyukpj240SI5SaZKBMoCxDE+ X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.610000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 41C2D9E0853424E91D6A6ACE9E27EECBE7CB8B01094EFCBABF26693BDF33E8C62000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hsiao Chien Sung Support "Pre-multiplied" blend mode on MediaTek's chips. Before this patch, only the "Coverage" mode is supported. Please refer to the description of the commit "drm/mediatek: Support alpha blending in display driver" for more information. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 6bf398850e85f..4b12ca285e84b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -35,6 +36,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -153,7 +155,8 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, struct mtk_plane_pending_state *pending =3D &state->pending; unsigned int offset =3D (pending->x & 1) << 31 | pending->y << 16 | pendi= ng->x; unsigned int align_width =3D ALIGN_DOWN(pending->width, 2); - unsigned int alpha_con =3D 0; + unsigned int mix_con =3D NON_PREMULTI_SOURCE; + bool replace_src_a =3D false; =20 dev_dbg(dev, "%s+ idx:%d", __func__, idx); =20 @@ -170,19 +173,27 @@ void mtk_ethdr_layer_config(struct device *dev, unsig= ned int idx, return; } =20 - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con =3D MIXER_ALPHA_AEN | MIXER_ALPHA; + mix_con |=3D MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA); =20 - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : t= rue, - DEFAULT_9BIT_ALPHA, + if (state->base.pixel_blend_mode !=3D DRM_MODE_BLEND_COVERAGE) + mix_con |=3D PREMULTI_SOURCE; + + if (state->base.fb && !state->base.fb->format->has_alpha) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a =3D true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_= ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); =20 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq= _base, mixer->regs, MIX_L_SRC_SIZE(idx)); mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC= _OFFSET(idx)); - mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, M= IX_L_SRC_CON(idx), - 0x1ff); + mtk_ddp_write(cmdq_pkt, mix_con, &mixer->cmdq_base, mixer->regs, MIX_L_SR= C_CON(idx)); mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MI= X_SRC_CON, BIT(idx)); } --=20 2.18.0