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Document the behavior as of the current draft of the specification, which is version 0.8.4. Signed-off-by: Samuel Holland --- .../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..bb7d5d84f31f 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,18 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. =20 + - const: smmpm + description: | + The standard Smmpm extension for M-mode pointer masking as def= ined + at commit a1e68469c60 ("Minor correction to pointer masking sp= ec.") + of riscv-j-extension. + + - const: smnpm + description: | + The standard Smnpm extension for next-mode pointer masking as = defined + at commit a1e68469c60 ("Minor correction to pointer masking sp= ec.") + of riscv-j-extension. + - const: smstateen description: | The standard Smstateen extension for controlling access to CSRs @@ -147,6 +159,12 @@ properties: and mode-based filtering as ratified at commit 01d1df0 ("Add a= bility to manually trigger workflow. (#2)") of riscv-count-overflow. =20 + - const: ssnpm + description: | + The standard Ssnpm extension for next-mode pointer masking as = defined + at commit a1e68469c60 ("Minor correction to pointer masking sp= ec.") + of riscv-j-extension. + - const: sstc description: | The standard Sstc supervisor-level extension for time compare = as --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 206524F206 for ; Tue, 19 Mar 2024 21:59:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710885561; cv=none; b=dN1eDNI230mjwM0M40KDQaCWNoDDn0EXo7/CKCZhmmWptlTT/BnnYfCMYZeYSQv/1Skid/sBXlWEbyEnKR9ws2oSGBoEdkWui9NVlxHzaDaPjN2nka/MTgqy3ehWi/QSg3gYcwYm4WRKU5fovGZdyio5NV2QCoSXA+7/l+Sz09I= ARC-Message-Signature: i=1; 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Tue, 19 Mar 2024 14:59:19 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, Conor Dooley , kasan-dev@googlegroups.com, Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , Samuel Holland , Albert Ou , Andrew Jones Subject: [RFC PATCH 2/9] riscv: Add ISA extension parsing for pointer masking Date: Tue, 19 Mar 2024 14:58:28 -0700 Message-ID: <20240319215915.832127-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.1 In-Reply-To: <20240319215915.832127-1-samuel.holland@sifive.com> References: <20240319215915.832127-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RISC-V Pointer Masking specification defines three extensions: Smmpm, Smnpm, and Ssnpm. Add support for parsing each of them. Smmpm implies the existence of the mseccfg CSR. As it is the only user of this CSR so far, there is no need for an Xlinuxmseccfg extension. Signed-off-by: Samuel Holland --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 1f2d2599c655..1a21dfc47f08 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,9 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_SMMPM 74 +#define RISCV_ISA_EXT_SMNPM 75 +#define RISCV_ISA_EXT_SSNPM 76 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 @@ -88,8 +91,10 @@ =20 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA +#define RISCV_ISA_EXT_SxNPM RISCV_ISA_EXT_SMNPM #else #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA +#define RISCV_ISA_EXT_SxNPM RISCV_ISA_EXT_SSNPM #endif =20 #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 79a5a35fab96..d1846aab1f78 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -311,9 +311,12 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), + __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A41E4F889 for ; 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charset="utf-8" Pointer masking is controlled via a two-bit PMM field, which appears in various CSRs depending on which extensions are implemented. Smmpm defines the field in mseccfg; Smnpm defines the field in menvcfg; Ssnpm defines the field in senvcfg and (if present) henvcfg and hstatus. Signed-off-by: Samuel Holland --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..1d5a6d73482c 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -119,6 +119,10 @@ =20 /* HSTATUS flags */ #ifdef CONFIG_64BIT +#define HSTATUS_PMM _AC(0x3000000000000, UL) +#define HSTATUS_PMM_PMLEN_0 _AC(0x0000000000000, UL) +#define HSTATUS_PMM_PMLEN_7 _AC(0x2000000000000, UL) +#define HSTATUS_PMM_PMLEN_16 _AC(0x3000000000000, UL) #define HSTATUS_VSXL _AC(0x300000000, UL) #define HSTATUS_VSXL_SHIFT 32 #endif @@ -194,6 +198,10 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_PMM _AC(0x300000000, ULL) +#define ENVCFG_PMM_PMLEN_0 _AC(0x000000000, ULL) +#define ENVCFG_PMM_PMLEN_7 _AC(0x200000000, ULL) +#define ENVCFG_PMM_PMLEN_16 _AC(0x300000000, ULL) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 @@ -215,6 +223,12 @@ #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) =20 +/* mseccfg bits */ +#define MSECCFG_PMM ENVCFG_PMM +#define MSECCFG_PMM_PMLEN_0 ENVCFG_PMM_PMLEN_0 +#define MSECCFG_PMM_PMLEN_7 ENVCFG_PMM_PMLEN_7 +#define MSECCFG_PMM_PMLEN_16 ENVCFG_PMM_PMLEN_16 + /* symbolic CSR names: */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -381,6 +395,8 @@ #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPADDR0 0x3b0 +#define CSR_MSECCFG 0x747 +#define CSR_MSECCFGH 0x757 #define CSR_MVENDORID 0xf11 #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9A5F5FB89 for ; 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charset="utf-8" This allows checking if some thread other than current is 32-bit. Signed-off-by: Samuel Holland --- arch/riscv/include/asm/compat.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/compat.h b/arch/riscv/include/asm/compa= t.h index 2ac955b51148..233c439c12d7 100644 --- a/arch/riscv/include/asm/compat.h +++ b/arch/riscv/include/asm/compat.h @@ -12,11 +12,18 @@ #include #include =20 +#ifdef CONFIG_COMPAT + static inline int is_compat_task(void) { return test_thread_flag(TIF_32BIT); } =20 +static inline int is_compat_thread(struct thread_info *thread) +{ + return test_ti_thread_flag(thread, TIF_32BIT); +} + struct compat_user_regs_struct { compat_ulong_t pc; compat_ulong_t ra; @@ -126,4 +133,13 @@ static inline void cregs_to_regs(struct compat_user_re= gs_struct *cregs, regs->t6 =3D (unsigned long) cregs->t6; }; =20 +#else + +static inline int is_compat_thread(struct thread_info *thread) +{ + return 0; +} + +#endif + #endif /* __ASM_COMPAT_H */ --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C39665FBA9 for ; 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Tue, 19 Mar 2024 14:59:23 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id z25-20020aa785d9000000b006e6c61b264bsm10273892pfn.32.2024.03.19.14.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 14:59:22 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, Conor Dooley , kasan-dev@googlegroups.com, Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , Samuel Holland , Andrew Jones , Guo Ren , Heiko Stuebner , Paul Walmsley Subject: [RFC PATCH 5/9] riscv: Split per-CPU and per-thread envcfg bits Date: Tue, 19 Mar 2024 14:58:31 -0700 Message-ID: <20240319215915.832127-6-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.1 In-Reply-To: <20240319215915.832127-1-samuel.holland@sifive.com> References: <20240319215915.832127-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some envcfg bits need to be controlled on a per-thread basis, such as the pointer masking mode. However, the envcfg CSR value cannot simply be stored in struct thread_struct, because some hardware may implement a different subset of envcfg CSR bits is across CPUs. As a result, we need to combine the per-CPU and per-thread bits whenever we switch threads. Signed-off-by: Samuel Holland --- arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/switch_to.h | 12 ++++++++++++ arch/riscv/kernel/cpufeature.c | 4 +++- 4 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 0bd11862b760..b1ad8d0b4599 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -33,6 +33,8 @@ DECLARE_PER_CPU(long, misaligned_access_speed); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 +DECLARE_PER_CPU(unsigned long, riscv_cpu_envcfg); + void riscv_user_isa_enable(void); =20 #ifdef CONFIG_RISCV_MISALIGNED diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index a8509cc31ab2..06b87402a4d8 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -118,6 +118,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + unsigned long envcfg; u32 riscv_v_flags; u32 vstate_ctrl; struct __riscv_v_ext_state vstate; diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7efdb0584d47..256a354a5c4a 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -69,6 +69,17 @@ static __always_inline bool has_fpu(void) { return false= ; } #define __switch_to_fpu(__prev, __next) do { } while (0) #endif =20 +static inline void sync_envcfg(struct task_struct *task) +{ + csr_write(CSR_ENVCFG, this_cpu_read(riscv_cpu_envcfg) | task->thread.envc= fg); +} + +static inline void __switch_to_envcfg(struct task_struct *next) +{ + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XL= INUXENVCFG)) + sync_envcfg(next); +} + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); =20 @@ -80,6 +91,7 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector()) \ __switch_to_vector(__prev, __next); \ + __switch_to_envcfg(__next); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d1846aab1f78..32aaaf41f8a8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -44,6 +44,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __rea= d_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 +DEFINE_PER_CPU(unsigned long, riscv_cpu_envcfg); + /* Performance information */ DEFINE_PER_CPU(long, misaligned_access_speed); =20 @@ -978,7 +980,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZI= CBOZ)) - csr_set(CSR_ENVCFG, ENVCFG_CBZE); + this_cpu_or(riscv_cpu_envcfg, ENVCFG_CBZE); } =20 #ifdef CONFIG_RISCV_ALTERNATIVE --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF685FDB2 for ; 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charset="utf-8" RISC-V supports pointer masking with a variable number of tag bits ("PMLEN") and which is configured at the next higher privilege level. Wire up the PR_SET_TAGGED_ADDR_CTRL and PR_GET_TAGGED_ADDR_CTRL prctls so userspace can request a minimum number of tag bits and determine the actual number of tag bits. As with PR_TAGGED_ADDR_ENABLE, the pointer masking configuration is thread-scoped, inherited on clone() and fork() and cleared on exec(). Signed-off-by: Samuel Holland --- arch/riscv/Kconfig | 8 +++ arch/riscv/include/asm/processor.h | 8 +++ arch/riscv/kernel/process.c | 107 +++++++++++++++++++++++++++++ include/uapi/linux/prctl.h | 3 + 4 files changed, 126 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e3142ce531a0..a1a1585120f0 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -479,6 +479,14 @@ config RISCV_ISA_C =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_POINTER_MASKING + bool "Smmpm, Smnpm, and Ssnpm extensions for pointer masking" + depends on 64BIT + default y + help + Add support to dynamically detect the presence of the Smmpm, Smnpm, + and Ssnpm extensions (pointer masking) and enable their usage. + config RISCV_ISA_SVNAPOT bool "Svnapot extension support for supervisor mode NAPOT pages" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 06b87402a4d8..64b34e839802 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -185,6 +185,14 @@ extern int set_unalign_ctl(struct task_struct *tsk, un= signed int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) =20 +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */ +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg); +long get_tagged_addr_ctrl(struct task_struct *task); +#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg) +#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current) +#endif + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 92922dbd5b5c..3578e75f4aa4 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -7,6 +7,7 @@ * Copyright (C) 2017 SiFive */ =20 +#include #include #include #include @@ -154,6 +155,18 @@ void start_thread(struct pt_regs *regs, unsigned long = pc, #endif } =20 +static void flush_tagged_addr_state(void) +{ +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SxNPM)) + return; + + current->thread.envcfg &=3D ~ENVCFG_PMM; + + sync_envcfg(current); +#endif +} + void flush_thread(void) { #ifdef CONFIG_FPU @@ -173,6 +186,7 @@ void flush_thread(void) memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); clear_tsk_thread_flag(current, TIF_RISCV_V_DEFER_RESTORE); #endif + flush_tagged_addr_state(); } =20 void arch_release_task_struct(struct task_struct *tsk) @@ -236,3 +250,96 @@ void __init arch_task_cache_init(void) { riscv_v_setup_ctx_cache(); } + +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +static bool have_user_pmlen_7; +static bool have_user_pmlen_16; + +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg) +{ + unsigned long valid_mask =3D PR_PMLEN_MASK; + struct thread_info *ti =3D task_thread_info(task); + u8 pmlen; + + if (is_compat_thread(ti)) + return -EINVAL; + + if (arg & ~valid_mask) + return -EINVAL; + + pmlen =3D FIELD_GET(PR_PMLEN_MASK, arg); + if (pmlen > 16) { + return -EINVAL; + } else if (pmlen > 7) { + if (have_user_pmlen_16) + pmlen =3D 16; + else + return -EINVAL; + } else if (pmlen > 0) { + /* + * Prefer the smallest PMLEN that satisfies the user's request, + * in case choosing a larger PMLEN has a performance impact. + */ + if (have_user_pmlen_7) + pmlen =3D 7; + else if (have_user_pmlen_16) + pmlen =3D 16; + else + return -EINVAL; + } + + task->thread.envcfg &=3D ~ENVCFG_PMM; + if (pmlen =3D=3D 7) + task->thread.envcfg |=3D ENVCFG_PMM_PMLEN_7; + else if (pmlen =3D=3D 16) + task->thread.envcfg |=3D ENVCFG_PMM_PMLEN_16; + + if (task =3D=3D current) + sync_envcfg(current); + + return 0; +} + +long get_tagged_addr_ctrl(struct task_struct *task) +{ + struct thread_info *ti =3D task_thread_info(task); + long ret =3D 0; + + if (is_compat_thread(ti)) + return -EINVAL; + + switch (task->thread.envcfg & ENVCFG_PMM) { + case ENVCFG_PMM_PMLEN_7: + ret |=3D FIELD_PREP(PR_PMLEN_MASK, 7); + break; + case ENVCFG_PMM_PMLEN_16: + ret |=3D FIELD_PREP(PR_PMLEN_MASK, 16); + break; + } + + return ret; +} + +static bool try_to_set_pmm(unsigned long value) +{ + csr_set(CSR_ENVCFG, value); + return (csr_read_clear(CSR_ENVCFG, ENVCFG_PMM) & ENVCFG_PMM) =3D=3D value; +} + +static int __init tagged_addr_init(void) +{ + if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SxNPM)) + return 0; + + /* + * envcfg.PMM is a WARL field. Detect which values are supported. + * Assume the supported PMLEN values are the same on all harts. + */ + csr_clear(CSR_ENVCFG, ENVCFG_PMM); + have_user_pmlen_7 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_7); + have_user_pmlen_16 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_16); + + return 0; +} +core_initcall(tagged_addr_init); +#endif /* CONFIG_RISCV_ISA_POINTER_MASKING */ diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..488b0d8e8495 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -244,6 +244,9 @@ struct prctl_mm_map { # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) /* Unused; kept only for source compatibility */ # define PR_MTE_TCF_SHIFT 1 +/* RISC-V pointer masking tag length */ +# define PR_PMLEN_SHIFT 24 +# define PR_PMLEN_MASK (0x7fUL << PR_PMLEN_SHIFT) =20 /* Control reclaim behavior when allocating memory */ #define PR_SET_IO_FLUSHER 57 --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E6126026E for ; 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Tue, 19 Mar 2024 14:59:25 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id z25-20020aa785d9000000b006e6c61b264bsm10273892pfn.32.2024.03.19.14.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 14:59:25 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, tech-j-ext@lists.risc-v.org, Conor Dooley , kasan-dev@googlegroups.com, Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , Samuel Holland , Albert Ou , Greentime Hu Subject: [RFC PATCH 7/9] riscv: Add support for the tagged address ABI Date: Tue, 19 Mar 2024 14:58:33 -0700 Message-ID: <20240319215915.832127-8-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.1 In-Reply-To: <20240319215915.832127-1-samuel.holland@sifive.com> References: <20240319215915.832127-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When pointer masking is enabled for userspace, the kernel can accept tagged pointers as arguments to some system calls. Allow this by untagging the pointers in access_ok() and the uaccess routines. The software untagging in the uaccess routines is required because U-mode and S-mode have entirely separate pointer masking configurations. Signed-off-by: Samuel Holland --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/uaccess.h | 40 +++++++++++++++++++++--- arch/riscv/kernel/process.c | 49 +++++++++++++++++++++++++++++- 3 files changed, 84 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 64b34e839802..cdc8569b2118 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -124,6 +124,7 @@ struct thread_struct { struct __riscv_v_ext_state vstate; unsigned long align_ctl; struct __riscv_v_ext_state kernel_vstate; + u8 pmlen; }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uacc= ess.h index ec0cab9fbddd..ed282dcf9a6d 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -9,8 +9,38 @@ #define _ASM_RISCV_UACCESS_H =20 #include +#include #include /* for TASK_SIZE */ =20 +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +static inline unsigned long __untagged_addr(unsigned long addr) +{ + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SxNPM)) { + u8 shift =3D current->thread.pmlen; + + /* + * Virtual addresses are sign-extended, while + * physical addresses are zero-extended. + */ + if (IS_ENABLED(CONFIG_MMU)) + return (long)(addr << shift) >> shift; + else + return (addr << shift) >> shift; + } + + return addr; +} + +#define untagged_addr(addr) ({ \ + unsigned long __addr =3D (__force unsigned long)(addr); \ + (__force __typeof__(addr))__untagged_addr(__addr); \ +}) + +#define access_ok(addr, size) likely(__access_ok(untagged_addr(addr), size= )) +#else +#define untagged_addr(addr) addr +#endif + /* * User space memory access functions */ @@ -130,7 +160,7 @@ do { \ */ #define __get_user(x, ptr) \ ({ \ - const __typeof__(*(ptr)) __user *__gu_ptr =3D (ptr); \ + const __typeof__(*(ptr)) __user *__gu_ptr =3D untagged_addr(ptr); \ long __gu_err =3D 0; \ \ __chk_user_ptr(__gu_ptr); \ @@ -246,7 +276,7 @@ do { \ */ #define __put_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__gu_ptr =3D (ptr); \ + __typeof__(*(ptr)) __user *__gu_ptr =3D untagged_addr(ptr); \ __typeof__(*__gu_ptr) __val =3D (x); \ long __pu_err =3D 0; \ \ @@ -293,13 +323,13 @@ unsigned long __must_check __asm_copy_from_user(void = *to, static inline unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n) { - return __asm_copy_from_user(to, from, n); + return __asm_copy_from_user(to, untagged_addr(from), n); } =20 static inline unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n) { - return __asm_copy_to_user(to, from, n); + return __asm_copy_to_user(untagged_addr(to), from, n); } =20 extern long strncpy_from_user(char *dest, const char __user *src, long cou= nt); @@ -314,7 +344,7 @@ unsigned long __must_check clear_user(void __user *to, = unsigned long n) { might_fault(); return access_ok(to, n) ? - __clear_user(to, n) : n; + __clear_user(untagged_addr(to), n) : n; } =20 #define __get_kernel_nofault(dst, src, type, err_label) \ diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 3578e75f4aa4..36129040b7bd 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -162,6 +162,7 @@ static void flush_tagged_addr_state(void) return; =20 current->thread.envcfg &=3D ~ENVCFG_PMM; + current->thread.pmlen =3D 0; =20 sync_envcfg(current); #endif @@ -255,9 +256,14 @@ void __init arch_task_cache_init(void) static bool have_user_pmlen_7; static bool have_user_pmlen_16; =20 +/* + * Control the relaxed ABI allowing tagged user addresses into the kernel. + */ +static unsigned int tagged_addr_disabled; + long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg) { - unsigned long valid_mask =3D PR_PMLEN_MASK; + unsigned long valid_mask =3D PR_PMLEN_MASK | PR_TAGGED_ADDR_ENABLE; struct thread_info *ti =3D task_thread_info(task); u8 pmlen; =20 @@ -288,12 +294,25 @@ long set_tagged_addr_ctrl(struct task_struct *task, u= nsigned long arg) return -EINVAL; } =20 + /* + * Do not allow the enabling of the tagged address ABI if globally + * disabled via sysctl abi.tagged_addr_disabled, if pointer masking + * is disabled for userspace. + */ + if (arg & PR_TAGGED_ADDR_ENABLE && (tagged_addr_disabled || !pmlen)) + return -EINVAL; + task->thread.envcfg &=3D ~ENVCFG_PMM; if (pmlen =3D=3D 7) task->thread.envcfg |=3D ENVCFG_PMM_PMLEN_7; else if (pmlen =3D=3D 16) task->thread.envcfg |=3D ENVCFG_PMM_PMLEN_16; =20 + if (arg & PR_TAGGED_ADDR_ENABLE) + task->thread.pmlen =3D pmlen; + else + task->thread.pmlen =3D 0; + if (task =3D=3D current) sync_envcfg(current); =20 @@ -308,6 +327,13 @@ long get_tagged_addr_ctrl(struct task_struct *task) if (is_compat_thread(ti)) return -EINVAL; =20 + if (task->thread.pmlen) + ret =3D PR_TAGGED_ADDR_ENABLE; + + /* + * The task's pmlen is only set if the tagged address ABI is enabled, + * so the effective PMLEN must be extracted from envcfg.PMM. + */ switch (task->thread.envcfg & ENVCFG_PMM) { case ENVCFG_PMM_PMLEN_7: ret |=3D FIELD_PREP(PR_PMLEN_MASK, 7); @@ -326,6 +352,24 @@ static bool try_to_set_pmm(unsigned long value) return (csr_read_clear(CSR_ENVCFG, ENVCFG_PMM) & ENVCFG_PMM) =3D=3D value; } =20 +/* + * Global sysctl to disable the tagged user addresses support. This control + * only prevents the tagged address ABI enabling via prctl() and does not + * disable it for tasks that already opted in to the relaxed ABI. + */ + +static struct ctl_table tagged_addr_sysctl_table[] =3D { + { + .procname =3D "tagged_addr_disabled", + .mode =3D 0644, + .data =3D &tagged_addr_disabled, + .maxlen =3D sizeof(int), + .proc_handler =3D proc_dointvec_minmax, + .extra1 =3D SYSCTL_ZERO, + .extra2 =3D SYSCTL_ONE, + }, +}; + static int __init tagged_addr_init(void) { if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SxNPM)) @@ -339,6 +383,9 @@ static int __init tagged_addr_init(void) have_user_pmlen_7 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_7); have_user_pmlen_16 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_16); =20 + if (!register_sysctl("abi", tagged_addr_sysctl_table)) + return -EINVAL; + return 0; } core_initcall(tagged_addr_init); --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B9386026C for ; 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charset="utf-8" This allows a tracer to control the ABI of the tracee, as on arm64. Signed-off-by: Samuel Holland --- arch/riscv/kernel/ptrace.c | 42 ++++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 43 insertions(+) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index e8515aa9d80b..3d414db2118b 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -28,6 +28,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_V REGSET_V, #endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + REGSET_TAGGED_ADDR_CTRL, +#endif }; =20 static int riscv_gpr_get(struct task_struct *target, @@ -152,6 +155,35 @@ static int riscv_vr_set(struct task_struct *target, } #endif =20 +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +static int tagged_addr_ctrl_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + long ctrl =3D get_tagged_addr_ctrl(target); + + if (IS_ERR_VALUE(ctrl)) + return ctrl; + + return membuf_write(&to, &ctrl, sizeof(ctrl)); +} + +static int tagged_addr_ctrl_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + long ctrl; + + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); + if (ret) + return ret; + + return set_tagged_addr_ctrl(target, ctrl); +} +#endif + static const struct user_regset riscv_user_regset[] =3D { [REGSET_X] =3D { .core_note_type =3D NT_PRSTATUS, @@ -182,6 +214,16 @@ static const struct user_regset riscv_user_regset[] = =3D { .set =3D riscv_vr_set, }, #endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + [REGSET_TAGGED_ADDR_CTRL] =3D { + .core_note_type =3D NT_RISCV_TAGGED_ADDR_CTRL, + .n =3D 1, + .size =3D sizeof(long), + .align =3D sizeof(long), + .regset_get =3D tagged_addr_ctrl_get, + .set =3D tagged_addr_ctrl_set, + }, +#endif }; =20 static const struct user_regset_view riscv_user_native_view =3D { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 9417309b7230..90806024fed6 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -447,6 +447,7 @@ typedef struct elf64_shdr { #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ +#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (= prctl()) */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension regist= ers */ --=20 2.43.1 From nobody Mon Feb 9 00:26:19 2026 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00BA7604A4 for ; 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charset="utf-8" This test covers the behavior of the PR_SET_TAGGED_ADDR_CTRL and PR_GET_TAGGED_ADDR_CTRL prctl() operations, their effects on the userspace ABI, and their effects on the system call ABI. Signed-off-by: Samuel Holland --- tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/tags/Makefile | 10 + .../selftests/riscv/tags/pointer_masking.c | 307 ++++++++++++++++++ 3 files changed, 318 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/riscv/tags/Makefile create mode 100644 tools/testing/selftests/riscv/tags/pointer_masking.c diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftes= ts/riscv/Makefile index 4a9ff515a3a0..6e7e6621a71a 100644 --- a/tools/testing/selftests/riscv/Makefile +++ b/tools/testing/selftests/riscv/Makefile @@ -5,7 +5,7 @@ ARCH ?=3D $(shell uname -m 2>/dev/null || echo not) =20 ifneq (,$(filter $(ARCH),riscv)) -RISCV_SUBTARGETS ?=3D hwprobe vector mm +RISCV_SUBTARGETS ?=3D hwprobe mm tags vector else RISCV_SUBTARGETS :=3D endif diff --git a/tools/testing/selftests/riscv/tags/Makefile b/tools/testing/se= lftests/riscv/tags/Makefile new file mode 100644 index 000000000000..ed82ff9c664e --- /dev/null +++ b/tools/testing/selftests/riscv/tags/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +CFLAGS +=3D -I$(top_srcdir)/tools/include + +TEST_GEN_PROGS :=3D pointer_masking + +include ../../lib.mk + +$(OUTPUT)/pointer_masking: pointer_masking.c + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/tags/pointer_masking.c b/tools/t= esting/selftests/riscv/tags/pointer_masking.c new file mode 100644 index 000000000000..c9f66e8436ab --- /dev/null +++ b/tools/testing/selftests/riscv/tags/pointer_masking.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../kselftest.h" + +#ifndef PR_PMLEN_SHIFT +#define PR_PMLEN_SHIFT 24 +#endif +#ifndef PR_PMLEN_MASK +#define PR_PMLEN_MASK (0x7fUL << PR_PMLEN_SHIFT) +#endif + +static int dev_zero; + +static sigjmp_buf jmpbuf; + +static void sigsegv_handler(int sig) +{ + siglongjmp(jmpbuf, 1); +} + +static int min_pmlen; +static int max_pmlen; + +static inline bool valid_pmlen(int pmlen) +{ + return pmlen =3D=3D 0 || pmlen =3D=3D 7 || pmlen =3D=3D 16; +} + +static void test_pmlen(void) +{ + ksft_print_msg("Testing available PMLEN values\n"); + + for (int request =3D 0; request <=3D 16; request++) { + int pmlen, ret; + + ret =3D prctl(PR_SET_TAGGED_ADDR_CTRL, request << PR_PMLEN_SHIFT, 0, 0, = 0); + if (ret) { + ksft_test_result_skip("PMLEN=3D%d PR_GET_TAGGED_ADDR_CTRL\n", request); + ksft_test_result_skip("PMLEN=3D%d constraint\n", request); + ksft_test_result_skip("PMLEN=3D%d validity\n", request); + continue; + } + + ret =3D prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0); + ksft_test_result(ret >=3D 0, "PMLEN=3D%d PR_GET_TAGGED_ADDR_CTRL\n", req= uest); + if (ret < 0) { + ksft_test_result_skip("PMLEN=3D%d constraint\n", request); + ksft_test_result_skip("PMLEN=3D%d validity\n", request); + continue; + } + + pmlen =3D (ret & PR_PMLEN_MASK) >> PR_PMLEN_SHIFT; + ksft_test_result(pmlen >=3D request, "PMLEN=3D%d constraint\n", request); + ksft_test_result(valid_pmlen(pmlen), "PMLEN=3D%d validity\n", request); + + if (min_pmlen =3D=3D 0) + min_pmlen =3D pmlen; + if (max_pmlen < pmlen) + max_pmlen =3D pmlen; + } + + if (max_pmlen =3D=3D 0) + ksft_exit_fail_msg("Failed to enable pointer masking\n"); +} + +static int set_tagged_addr_ctrl(int pmlen, bool tagged_addr_abi) +{ + int arg, ret; + + arg =3D pmlen << PR_PMLEN_SHIFT | tagged_addr_abi; + ret =3D prctl(PR_SET_TAGGED_ADDR_CTRL, arg, 0, 0, 0); + if (!ret) { + ret =3D prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0); + if (ret =3D=3D arg) + return 0; + } + + return ret < 0 ? -errno : -ENODATA; +} + +static void test_dereference_pmlen(int pmlen) +{ + static volatile int i; + volatile int *p; + int ret; + + ret =3D set_tagged_addr_ctrl(pmlen, false); + if (ret) + return ksft_test_result_error("PMLEN=3D%d setup (%d)\n", pmlen, ret); + + i =3D pmlen; + + if (pmlen) { + p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen); + + /* These dereferences should succeed. */ + if (sigsetjmp(jmpbuf, 1)) + return ksft_test_result_fail("PMLEN=3D%d valid tag\n", pmlen); + if (*p !=3D pmlen) + return ksft_test_result_fail("PMLEN=3D%d bad value\n", pmlen); + *p++; + } + + p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen - 1); + + /* These dereferences should raise SIGSEGV. */ + if (sigsetjmp(jmpbuf, 1)) + return ksft_test_result_pass("PMLEN=3D%d dereference\n", pmlen); + *p++; + ksft_test_result_fail("PMLEN=3D%d invalid tag\n", pmlen); +} + +static void test_dereference(void) +{ + ksft_print_msg("Testing userspace pointer dereference\n"); + + signal(SIGSEGV, sigsegv_handler); + + test_dereference_pmlen(0); + test_dereference_pmlen(min_pmlen); + test_dereference_pmlen(max_pmlen); + + signal(SIGSEGV, SIG_DFL); +} + +static void test_fork_exec(void) +{ + int ret, status; + + ksft_print_msg("Testing fork/exec behavior\n"); + + ret =3D set_tagged_addr_ctrl(min_pmlen, false); + if (ret) + return ksft_test_result_error("setup (%d)\n", ret); + + if (fork()) { + wait(&status); + ksft_test_result(WIFEXITED(status) && WEXITSTATUS(status) =3D=3D 0, + "dereference after fork\n"); + } else { + static volatile int i; + volatile int *p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen= - min_pmlen); + + exit(*p); + } + + if (fork()) { + wait(&status); + ksft_test_result(WIFSIGNALED(status) && WTERMSIG(status) =3D=3D SIGSEGV, + "dereference after fork+exec\n"); + } else { + execl("/proc/self/exe", "", NULL); + } +} + +static void test_tagged_addr_abi_sysctl(void) +{ + char value; + int fd; + + ksft_print_msg("Testing tagged address ABI sysctl\n"); + + fd =3D open("/proc/sys/abi/tagged_addr_disabled", O_WRONLY); + if (fd < 0) { + ksft_test_result_skip("failed to open sysctl file\n"); + ksft_test_result_skip("failed to open sysctl file\n"); + return; + } + + value =3D '1'; + pwrite(fd, &value, 1, 0); + ksft_test_result(set_tagged_addr_ctrl(min_pmlen, true) =3D=3D -EINVAL, + "sysctl disabled\n"); + + value =3D '0'; + pwrite(fd, &value, 1, 0); + ksft_test_result(set_tagged_addr_ctrl(min_pmlen, true) =3D=3D 0, + "sysctl enabled\n"); + + set_tagged_addr_ctrl(0, false); + + close(fd); +} + +static void test_tagged_addr_abi_pmlen(int pmlen) +{ + int i, *p, ret; + + i =3D ~pmlen; + + if (pmlen) { + p =3D (int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen); + + ret =3D set_tagged_addr_ctrl(pmlen, false); + if (ret) + return ksft_test_result_error("PMLEN=3D%d ABI disabled setup (%d)\n", + pmlen, ret); + + ret =3D write(dev_zero, p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d ABI disabled write\n", pmlen); + + ret =3D read(dev_zero, p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d ABI disabled read\n", pmlen); + + if (i !=3D ~pmlen) + return ksft_test_result_fail("PMLEN=3D%d ABI disabled value\n", pmlen); + + ret =3D set_tagged_addr_ctrl(pmlen, true); + if (ret) + return ksft_test_result_error("PMLEN=3D%d ABI enabled setup (%d)\n", + pmlen, ret); + + ret =3D write(dev_zero, p, sizeof(*p)); + if (ret !=3D sizeof(*p)) + return ksft_test_result_fail("PMLEN=3D%d ABI enabled write\n", pmlen); + + ret =3D read(dev_zero, p, sizeof(*p)); + if (ret !=3D sizeof(*p)) + return ksft_test_result_fail("PMLEN=3D%d ABI enabled read\n", pmlen); + + if (i) + return ksft_test_result_fail("PMLEN=3D%d ABI enabled value\n", pmlen); + + i =3D ~pmlen; + } else { + /* The tagged address ABI cannot be enabled when PMLEN =3D=3D 0. */ + ret =3D set_tagged_addr_ctrl(pmlen, true); + if (ret !=3D -EINVAL) + return ksft_test_result_error("PMLEN=3D%d ABI setup (%d)\n", + pmlen, ret); + } + + p =3D (int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen - 1); + + ret =3D write(dev_zero, p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d invalid tag write (%d)\n", pmle= n, errno); + + ret =3D read(dev_zero, p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d invalid tag read\n", pmlen); + + if (i !=3D ~pmlen) + return ksft_test_result_fail("PMLEN=3D%d invalid tag value\n", pmlen); + + ksft_test_result_pass("PMLEN=3D%d tagged address ABI\n", pmlen); +} + +static void test_tagged_addr_abi(void) +{ + ksft_print_msg("Testing tagged address ABI\n"); + + test_tagged_addr_abi_pmlen(0); + test_tagged_addr_abi_pmlen(min_pmlen); + test_tagged_addr_abi_pmlen(max_pmlen); +} + +static struct test_info { + unsigned int nr_tests; + void (*test_fn)(void); +} tests[] =3D { + { .nr_tests =3D 17 * 3, test_pmlen }, + { .nr_tests =3D 3, test_dereference }, + { .nr_tests =3D 2, test_fork_exec }, + { .nr_tests =3D 2, test_tagged_addr_abi_sysctl }, + { .nr_tests =3D 3, test_tagged_addr_abi }, +}; + +int main(int argc, char **argv) +{ + unsigned int plan =3D 0; + + /* Check if this is the child process after execl(). */ + if (!argv[0][0]) { + static volatile int i; + volatile int *p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen= - 7); + + return *p; + } + + dev_zero =3D open("/dev/zero", O_RDWR); + if (dev_zero < 0) + return 1; + + ksft_print_header(); + + for (int i =3D 0; i < ARRAY_SIZE(tests); ++i) + plan +=3D tests[i].nr_tests; + + ksft_set_plan(plan); + + for (int i =3D 0; i < ARRAY_SIZE(tests); ++i) + tests[i].test_fn(); + + ksft_finished(); +} --=20 2.43.1