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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-3-926d7a4ccd80@linaro.org> References: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> In-Reply-To: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3998; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=WsGgAE39xLO1WpNxrXfF0aN/WkAyS4SNo1d7Voxy384=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBl+WyVxmma2DSKw3/90m56VEW2t4wrDj06AsVmW6xr jurjn3aJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZflslQAKCRB33NvayMhJ0eJ7EA Ci49/QyBonFj6tTlibAF/GecKy1f4werx+qj80VTNMHp4lnZqaFjmcd5Mf36y+mo8ejHbBNVJk448Q TXtX8ILRoQzCPl4EhvAJIKLQdqoS9jynPhkVnN/BfMvt4Z3KGwIQGjNCcBjJZJdo2LVBs6qlWGsivm Lwru5OgO1kRvo0JYWs9INIqH2Pkua4sen+yy4repsxhxS1+pnY3Cbt+ijHz7Meq/BmJKjQ51iPoR1o uoB0Mk9xEPgAHTZZKA214XRQL2UsvUsf3V//3wuHX5Qu5GrEZ2XVNxwDw3hD1gyYFXNNac12iGWVYu Xi5pT5vu0HkqR9bGSepW2fKD+rAvqUpWqRJ2MDzSjrtX2i0K/7mQP79ZtZiJ1UQhraZyJkiWmwH44m 8TAaLzuQhsPoAQtcfCmYnkXI4uU+INxioz23jM1kFZ2tsqevV5Top4womKXrL0xt0FfSDFnerrGWNr eqUD1iQ7PYDRYg0qh7O6WpkJHEEOiioIFSmTMBPgAF8/N475ppBZJ8n3HZcTiAOpUdtmFeC9WxHJli v1lo+blY9rjF7fmF3Bdf3VOLa7kZ6/esa1aZNHKOlls8R38Bdv6m2Xhr87ZvQZ6tbLSeJTmLkNLMid x8sC12HuRi8gFf9hB8eUEj6p813xjDgMr0BoYTnxpBxOP8CvB+bGmMtvTM4A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, add the code to register it for PHYs configs that sets a aux_clock_rate. In order to get the right clock, add qmp_pcie_clk_hw_get() which uses the newly introduced QMP_PCIE_PIPE_CLK & QMP_PCIE_PHY_AUX_CLK clock IDs and also supports the legacy bindings by returning the PIPE clock. Signed-off-by: Neil Armstrong --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 70 ++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 079b3e306489..2d05226ae200 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -22,6 +22,8 @@ #include #include =20 +#include + #include "phy-qcom-qmp-common.h" =20 #include "phy-qcom-qmp.h" @@ -2389,6 +2391,9 @@ struct qmp_phy_cfg { =20 /* QMP PHY pipe clock interface rate */ unsigned long pipe_clock_rate; + + /* QMP PHY AUX clock interface rate */ + unsigned long aux_clock_rate; }; =20 struct qmp_pcie { @@ -2420,6 +2425,7 @@ struct qmp_pcie { int mode; =20 struct clk_fixed_rate pipe_clk_fixed; + struct clk_fixed_rate aux_clk_fixed; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -3681,6 +3687,62 @@ static int phy_pipe_clk_register(struct qmp_pcie *qm= p, struct device_node *np) return devm_clk_hw_register(qmp->dev, &fixed->hw); } =20 +/* + * Register a fixed rate PHY aux clock. + * + * The _phy_aux_clksrc generated by PHY goes to the GCC that gate + * controls it. The _phy_aux_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _phy_aux_clksrc here. The gcc driver takes care + * of assigning this _phy_aux_clksrc as parent to _phy_aux_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<--------------------------------------------= -+ + * | | = | + * | +-------+ | +-----+ = | + * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk--= -+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *= np) +{ + struct clk_fixed_rate *fixed =3D &qmp->aux_clk_fixed; + struct clk_init_data init =3D { }; + int ret; + + ret =3D of_property_read_string_index(np, "clock-output-names", 1, &init.= name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np); + return ret; + } + + init.ops =3D &clk_fixed_rate_ops; + + fixed->fixed_rate =3D qmp->cfg->aux_clock_rate; + fixed->hw.init =3D &init; + + return devm_clk_hw_register(qmp->dev, &fixed->hw); +} + +static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec,= void *data) +{ + struct qmp_pcie *qmp =3D data; + + /* Support legacy bindings */ + if (!clkspec->args_count) + return &qmp->pipe_clk_fixed.hw; + + switch (clkspec->args[0]) { + case QMP_PCIE_PIPE_CLK: + return &qmp->pipe_clk_fixed.hw; + case QMP_PCIE_PHY_AUX_CLK: + return &qmp->aux_clk_fixed.hw; + } + + return ERR_PTR(-EINVAL); +} + static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_no= de *np) { int ret; @@ -3689,6 +3751,14 @@ static int qmp_pcie_register_clocks(struct qmp_pcie = *qmp, struct device_node *np if (ret) return ret; =20 + if (qmp->cfg->aux_clock_rate) { + ret =3D phy_aux_clk_register(qmp, np); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(qmp->dev, qmp_pcie_clk_hw_get, qmp); + } + return devm_of_clk_add_hw_provider(qmp->dev, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); } --=20 2.34.1