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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-5-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan X-Mailer: b4 0.13.0 The current driver supports only parts with 2 channels. In order to prepare the support of new compatible ADCs with more channels, this commit: - defines MAX_NUM_CHANNEL to specify the maximum number of channels currently supported by the driver - adds available_scan_mask member in ad7380_chip_info structure - fixes spi xfer struct len depending on number of channels - fixes scan_data.raw buffer size to handle more channels - adds a timing specifications structure in ad7380_chip_info structure Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 996ca83feaed..3aca41ce9a14 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -29,6 +29,7 @@ #include #include =20 +#define MAX_NUM_CHANNELS 2 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 =20 @@ -65,12 +66,19 @@ #define AD7380_ALERT_LOW_TH GENMASK(11, 0) #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) =20 +#define T_CONVERT_NS 190 /* conversion time */ +struct ad7380_timing_specs { + const unsigned int t_csh_ns; /* CS minimum high time */ +}; + struct ad7380_chip_info { const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; const char * const *vcm_supplies; unsigned int num_vcm_supplies; + const unsigned long *available_scan_masks; + const struct ad7380_timing_specs *timing_specs; }; =20 #define AD7380_CHANNEL(index, bits, diff) { \ @@ -115,16 +123,24 @@ static const unsigned long ad7380_2_channel_scan_mask= s[] =3D { 0 }; =20 +static const struct ad7380_timing_specs ad7380_timing =3D { + .t_csh_ns =3D 10, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, .num_channels =3D ARRAY_SIZE(ad7380_channels), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7381_chip_info =3D { .name =3D "ad7381", .channels =3D ad7381_channels, .num_channels =3D ARRAY_SIZE(ad7381_channels), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7383_chip_info =3D { @@ -133,6 +149,8 @@ static const struct ad7380_chip_info ad7383_chip_info = =3D { .num_channels =3D ARRAY_SIZE(ad7383_channels), .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7384_chip_info =3D { @@ -141,6 +159,8 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .num_channels =3D ARRAY_SIZE(ad7384_channels), .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 struct ad7380_state { @@ -148,15 +168,15 @@ struct ad7380_state { struct spi_device *spi; struct regmap *regmap; unsigned int vref_mv; - unsigned int vcm_mv[2]; + unsigned int vcm_mv[MAX_NUM_CHANNELS]; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. - * Make the buffer large enough for 2 16-bit samples and one 64-bit + * Make the buffer large enough for MAX_NUM_CHANNELS 16-bit samples and o= ne 64-bit * aligned 64 bit timestamp. */ struct { - u16 raw[2]; + u16 raw[MAX_NUM_CHANNELS]; =20 s64 ts __aligned(8); } scan_data __aligned(IIO_DMA_MINALIGN); @@ -194,7 +214,7 @@ static int ad7380_regmap_reg_read(void *context, unsign= ed int reg, .tx_buf =3D &st->tx, .cs_change =3D 1, .cs_change_delay =3D { - .value =3D 10, /* t[CSH] */ + .value =3D st->chip_info->timing_specs->t_csh_ns, .unit =3D SPI_DELAY_UNIT_NSECS, }, }, { @@ -255,7 +275,8 @@ static irqreturn_t ad7380_trigger_handler(int irq, void= *p) struct ad7380_state *st =3D iio_priv(indio_dev); struct spi_transfer xfer =3D { .bits_per_word =3D st->chip_info->channels[0].scan_type.realbits, - .len =3D 4, + .len =3D (st->chip_info->num_channels - 1) * + ((st->chip_info->channels->scan_type.storagebits > 16) ? 4 : 2), .rx_buf =3D st->scan_data.raw, }; int ret; @@ -282,21 +303,22 @@ static int ad7380_read_direct(struct ad7380_state *st, .speed_hz =3D AD7380_REG_WR_SPEED_HZ, .bits_per_word =3D chan->scan_type.realbits, .delay =3D { - .value =3D 190, /* t[CONVERT] */ + .value =3D T_CONVERT_NS, .unit =3D SPI_DELAY_UNIT_NSECS, }, .cs_change =3D 1, .cs_change_delay =3D { - .value =3D 10, /* t[CSH] */ + .value =3D st->chip_info->timing_specs->t_csh_ns, .unit =3D SPI_DELAY_UNIT_NSECS, }, }, - /* then read both channels */ + /* then read all channels */ { .speed_hz =3D AD7380_REG_WR_SPEED_HZ, .bits_per_word =3D chan->scan_type.realbits, .rx_buf =3D st->scan_data.raw, - .len =3D 4, + .len =3D (st->chip_info->num_channels - 1) * + ((chan->scan_type.storagebits > 16) ? 4 : 2), }, }; int ret; @@ -472,7 +494,7 @@ static int ad7380_probe(struct spi_device *spi) indio_dev->name =3D st->chip_info->name; indio_dev->info =3D &ad7380_info; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->available_scan_masks =3D ad7380_2_channel_scan_masks; + indio_dev->available_scan_masks =3D st->chip_info->available_scan_masks; =20 ret =3D devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, iio_pollfunc_store_time, --=20 2.44.0