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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-1-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan , Conor Dooley X-Mailer: b4 0.13.0 From: David Lechner This adds a binding specification for the Analog Devices Inc. AD7380 family of ADCs. Signed-off-by: David Lechner Reviewed-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 82 ++++++++++++++++++= ++++ MAINTAINERS | 9 +++ 2 files changed, 91 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml new file mode 100644 index 000000000000..5e1ee0ebe0a2 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7380.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices Simultaneous Sampling Analog to Digital Converters + +maintainers: + - Michael Hennerich + - Nuno S=C3=A1 + +description: | + * https://www.analog.com/en/products/ad7380.html + * https://www.analog.com/en/products/ad7381.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad7380 + - adi,ad7381 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 80000000 + spi-cpol: true + spi-cpha: true + + vcc-supply: + description: A 3V to 3.6V supply that powers the chip. + + vlogic-supply: + description: + A 1.65V to 3.6V supply for the logic pins. + + refio-supply: + description: + A 2.5V to 3.3V supply for the external reference voltage. When omitt= ed, + the internal 2.5V reference is used. + + interrupts: + description: + When the device is using 1-wire mode, this property is used to optio= nally + specify the ALERT interrupt. + maxItems: 1 + +required: + - compatible + - reg + - vcc-supply + - vlogic-supply + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad7380"; + reg =3D <0>; + + spi-cpol; + spi-cpha; + spi-max-frequency =3D <80000000>; + + interrupts =3D <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent =3D <&gpio0>; + + vcc-supply =3D <&supply_3_3V>; + vlogic-supply =3D <&supply_3_3V>; + refio-supply =3D <&supply_2_5V>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 7b1a6f2d0c9c..f7c512f3bbda 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -427,6 +427,15 @@ W: http://wiki.analog.com/AD7142 W: https://ez.analog.com/linux-software-drivers F: drivers/input/misc/ad714x.c =20 +AD738X ADC DRIVER (AD7380/1/2/4) +M: Michael Hennerich +M: Nuno S=C3=A1 +R: David Lechner +S: Supported +W: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/= ad738x +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml + AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich S: Supported --=20 2.44.0 From nobody Fri Dec 19 17:43:31 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C54227D410 for ; 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Tue, 19 Mar 2024 03:11:32 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id je2-20020a05600c1f8200b004133072017csm21096384wmb.42.2024.03.19.03.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:11:31 -0700 (PDT) From: Julien Stephan Date: Tue, 19 Mar 2024 11:11:23 +0100 Subject: [PATCH v5 2/7] iio: adc: ad7380: new driver for AD7380 ADCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-2-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan , Stefan Popa X-Mailer: b4 0.13.0 From: David Lechner This adds a new driver for the AD7380 family ADCs. The driver currently implements basic support for the AD7380, AD7381, 2-channel differential ADCs. Support for additional single-ended, pseudo-differential and 4-channel chips that use the same register map as well as additional features of the chip will be added in future patches. Co-developed-by: Stefan Popa Signed-off-by: Stefan Popa Reviewed-by: Nuno Sa Signed-off-by: David Lechner [Julien Stephan: add datasheet links of supported parts] [Julien Stephan: fix rx/tx buffer for regmap access] Signed-off-by: Julien Stephan --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 16 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7380.c | 447 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 465 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f7c512f3bbda..2277870853c7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -435,6 +435,7 @@ S: Supported W: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/= ad738x W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +F: drivers/iio/adc/ad7380.c =20 AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 8db68b80b391..631386b037ae 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -155,6 +155,22 @@ config AD7298 To compile this driver as a module, choose M here: the module will be called ad7298. =20 +config AD7380 + tristate "Analog Devices AD7380 ADC driver" + depends on SPI_MASTER + select IIO_BUFFER + select IIO_TRIGGER + select IIO_TRIGGERED_BUFFER + help + AD7380 is a family of simultaneous sampling ADCs that share the same + SPI register map and have similar pinouts. + + Say yes here to build support for Analog Devices AD7380 ADC and + similar chips. + + To compile this driver as a module, choose M here: the module will be + called ad7380. + config AD7476 tristate "Analog Devices AD7476 1-channel ADCs driver and other similar d= evices from AD and TI" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index edb32ce2af02..bd3cbbb178fa 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_AD7291) +=3D ad7291.o obj-$(CONFIG_AD7292) +=3D ad7292.o obj-$(CONFIG_AD7298) +=3D ad7298.o obj-$(CONFIG_AD7923) +=3D ad7923.o +obj-$(CONFIG_AD7380) +=3D ad7380.o obj-$(CONFIG_AD7476) +=3D ad7476.o obj-$(CONFIG_AD7606_IFACE_PARALLEL) +=3D ad7606_par.o obj-$(CONFIG_AD7606_IFACE_SPI) +=3D ad7606_spi.o diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c new file mode 100644 index 000000000000..caf6deb3a8b1 --- /dev/null +++ b/drivers/iio/adc/ad7380.c @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD738x Simultaneous Sampling SAR ADCs + * + * Copyright 2017 Analog Devices Inc. + * Copyright 2024 BayLibre, SAS + * + * Datasheets of supported parts: + * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* 2.5V internal reference voltage */ +#define AD7380_INTERNAL_REF_MV 2500 + +/* reading and writing registers is more reliable at lower than max speed = */ +#define AD7380_REG_WR_SPEED_HZ 10000000 + +#define AD7380_REG_WR BIT(15) +#define AD7380_REG_REGADDR GENMASK(14, 12) +#define AD7380_REG_DATA GENMASK(11, 0) + +#define AD7380_REG_ADDR_NOP 0x0 +#define AD7380_REG_ADDR_CONFIG1 0x1 +#define AD7380_REG_ADDR_CONFIG2 0x2 +#define AD7380_REG_ADDR_ALERT 0x3 +#define AD7380_REG_ADDR_ALERT_LOW_TH 0x4 +#define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5 + +#define AD7380_CONFIG1_OS_MODE BIT(9) +#define AD7380_CONFIG1_OSR GENMASK(8, 6) +#define AD7380_CONFIG1_CRC_W BIT(5) +#define AD7380_CONFIG1_CRC_R BIT(4) +#define AD7380_CONFIG1_ALERTEN BIT(3) +#define AD7380_CONFIG1_RES BIT(2) +#define AD7380_CONFIG1_REFSEL BIT(1) +#define AD7380_CONFIG1_PMODE BIT(0) + +#define AD7380_CONFIG2_SDO2 GENMASK(9, 8) +#define AD7380_CONFIG2_SDO BIT(8) +#define AD7380_CONFIG2_RESET GENMASK(7, 0) + +#define AD7380_CONFIG2_RESET_SOFT 0x3C +#define AD7380_CONFIG2_RESET_HARD 0xFF + +#define AD7380_ALERT_LOW_TH GENMASK(11, 0) +#define AD7380_ALERT_HIGH_TH GENMASK(11, 0) + +struct ad7380_chip_info { + const char *name; + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +#define AD7380_CHANNEL(index, bits) { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .indexed =3D 1, \ + .differential =3D 1, \ + .channel =3D 2 * (index), \ + .channel2 =3D 2 * (index) + 1, \ + .scan_index =3D (index), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D (bits), \ + .storagebits =3D 16, \ + .endianness =3D IIO_CPU, \ + }, \ +} + +#define DEFINE_AD7380_2_CHANNEL(name, bits) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits), \ + AD7380_CHANNEL(1, bits), \ + IIO_CHAN_SOFT_TIMESTAMP(2), \ +} + +DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16); +DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14); + +/* Since this is simultaneous sampling, we don't allow individual channels= . */ +static const unsigned long ad7380_2_channel_scan_masks[] =3D { + GENMASK(1, 0), + 0 +}; + +static const struct ad7380_chip_info ad7380_chip_info =3D { + .name =3D "ad7380", + .channels =3D ad7380_channels, + .num_channels =3D ARRAY_SIZE(ad7380_channels), +}; + +static const struct ad7380_chip_info ad7381_chip_info =3D { + .name =3D "ad7381", + .channels =3D ad7381_channels, + .num_channels =3D ARRAY_SIZE(ad7381_channels), +}; + +struct ad7380_state { + const struct ad7380_chip_info *chip_info; + struct spi_device *spi; + struct regmap *regmap; + unsigned int vref_mv; + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + * Make the buffer large enough for 2 16-bit samples and one 64-bit + * aligned 64 bit timestamp. + */ + struct { + u16 raw[2]; + + s64 ts __aligned(8); + } scan_data __aligned(IIO_DMA_MINALIGN); + u16 tx; + u16 rx; +}; + +static int ad7380_regmap_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct ad7380_state *st =3D context; + struct spi_transfer xfer =3D { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .tx_buf =3D &st->tx, + }; + + st->tx =3D FIELD_PREP(AD7380_REG_WR, 1) | + FIELD_PREP(AD7380_REG_REGADDR, reg) | + FIELD_PREP(AD7380_REG_DATA, val); + + return spi_sync_transfer(st->spi, &xfer, 1); +} + +static int ad7380_regmap_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct ad7380_state *st =3D context; + struct spi_transfer xfers[] =3D { + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .tx_buf =3D &st->tx, + .cs_change =3D 1, + .cs_change_delay =3D { + .value =3D 10, /* t[CSH] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + }, { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D 16, + .len =3D 2, + .rx_buf =3D &st->rx, + }, + }; + int ret; + + st->tx =3D FIELD_PREP(AD7380_REG_WR, 0) | + FIELD_PREP(AD7380_REG_REGADDR, reg) | + FIELD_PREP(AD7380_REG_DATA, 0); + + ret =3D spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret < 0) + return ret; + + *val =3D FIELD_GET(AD7380_REG_DATA, st->rx); + + return 0; +} + +static const struct regmap_config ad7380_regmap_config =3D { + .reg_bits =3D 3, + .val_bits =3D 12, + .reg_read =3D ad7380_regmap_reg_read, + .reg_write =3D ad7380_regmap_reg_write, + .max_register =3D AD7380_REG_ADDR_ALERT_HIGH_TH, + .can_sleep =3D true, +}; + +static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg, + u32 writeval, u32 *readval) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + if (readval) + ret =3D regmap_read(st->regmap, reg, readval); + else + ret =3D regmap_write(st->regmap, reg, writeval); + + iio_device_release_direct_mode(indio_dev); + + return ret; +} + +static irqreturn_t ad7380_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad7380_state *st =3D iio_priv(indio_dev); + struct spi_transfer xfer =3D { + .bits_per_word =3D st->chip_info->channels[0].scan_type.realbits, + .len =3D 4, + .rx_buf =3D st->scan_data.raw, + }; + int ret; + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret) + goto out; + + iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data, + pf->timestamp); + +out: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int ad7380_read_direct(struct ad7380_state *st, + struct iio_chan_spec const *chan, int *val) +{ + struct spi_transfer xfers[] =3D { + /* toggle CS (no data xfer) to trigger a conversion */ + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D chan->scan_type.realbits, + .delay =3D { + .value =3D 190, /* t[CONVERT] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + .cs_change =3D 1, + .cs_change_delay =3D { + .value =3D 10, /* t[CSH] */ + .unit =3D SPI_DELAY_UNIT_NSECS, + }, + }, + /* then read both channels */ + { + .speed_hz =3D AD7380_REG_WR_SPEED_HZ, + .bits_per_word =3D chan->scan_type.realbits, + .rx_buf =3D st->scan_data.raw, + .len =3D 4, + }, + }; + int ret; + + ret =3D spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret < 0) + return ret; + + *val =3D sign_extend32(st->scan_data.raw[chan->scan_index], + chan->scan_type.realbits - 1); + + return IIO_VAL_INT; +} + +static int ad7380_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct ad7380_state *st =3D iio_priv(indio_dev); + int ret; + + switch (info) { + case IIO_CHAN_INFO_RAW: + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D ad7380_read_direct(st, chan, val); + iio_device_release_direct_mode(indio_dev); + + return ret; + case IIO_CHAN_INFO_SCALE: + *val =3D st->vref_mv; + *val2 =3D chan->scan_type.realbits; + + return IIO_VAL_FRACTIONAL_LOG2; + } + + return -EINVAL; +} + +static const struct iio_info ad7380_info =3D { + .read_raw =3D &ad7380_read_raw, + .debugfs_reg_access =3D &ad7380_debugfs_reg_access, +}; + +static int ad7380_init(struct ad7380_state *st, struct regulator *vref) +{ + int ret; + + /* perform hard reset */ + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, + AD7380_CONFIG2_RESET, + FIELD_PREP(AD7380_CONFIG2_RESET, + AD7380_CONFIG2_RESET_HARD)); + if (ret < 0) + return ret; + + /* select internal or external reference voltage */ + ret =3D regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, + AD7380_CONFIG1_REFSEL, + FIELD_PREP(AD7380_CONFIG1_REFSEL, + vref ? 1 : 0)); + if (ret < 0) + return ret; + + /* SPI 1-wire mode */ + return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, + AD7380_CONFIG2_SDO, + FIELD_PREP(AD7380_CONFIG2_SDO, 1)); +} + +static void ad7380_regulator_disable(void *p) +{ + regulator_disable(p); +} + +static int ad7380_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct ad7380_state *st; + struct regulator *vref; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return dev_err_probe(&spi->dev, -EINVAL, "missing match data\n"); + + vref =3D devm_regulator_get_optional(&spi->dev, "refio"); + if (IS_ERR(vref)) { + if (PTR_ERR(vref) !=3D -ENODEV) + return dev_err_probe(&spi->dev, PTR_ERR(vref), + "Failed to get refio regulator\n"); + + vref =3D NULL; + } + + /* + * If there is no REFIO supply, then it means that we are using + * the internal 2.5V reference, otherwise REFIO is reference voltage. + */ + if (vref) { + ret =3D regulator_enable(vref); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&spi->dev, + ad7380_regulator_disable, vref); + if (ret) + return ret; + + ret =3D regulator_get_voltage(vref); + if (ret < 0) + return ret; + + st->vref_mv =3D ret / 1000; + } else { + st->vref_mv =3D AD7380_INTERNAL_REF_MV; + } + + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); + if (IS_ERR(st->regmap)) + return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), + "failed to allocate register map\n"); + + indio_dev->channels =3D st->chip_info->channels; + indio_dev->num_channels =3D st->chip_info->num_channels; + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &ad7380_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->available_scan_masks =3D ad7380_2_channel_scan_masks; + + ret =3D devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, + iio_pollfunc_store_time, + ad7380_trigger_handler, NULL); + if (ret) + return ret; + + ret =3D ad7380_init(st, vref); + if (ret) + return ret; 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Tue, 19 Mar 2024 03:11:33 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id je2-20020a05600c1f8200b004133072017csm21096384wmb.42.2024.03.19.03.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:11:32 -0700 (PDT) From: Julien Stephan Date: Tue, 19 Mar 2024 11:11:24 +0100 Subject: [PATCH v5 3/7] dt-bindings: iio: adc: ad7380: add pseudo-differential parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-3-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan X-Mailer: b4 0.13.0 From: David Lechner Adding AD7383 and AD7384 compatible parts that are pseudo-differential. Pseudo-differential require common mode voltage supplies, so add them conditionally Signed-off-by: David Lechner Signed-off-by: Julien Stephan Acked-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 32 ++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index 5e1ee0ebe0a2..de3d28a021ae 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -13,6 +13,8 @@ maintainers: description: | * https://www.analog.com/en/products/ad7380.html * https://www.analog.com/en/products/ad7381.html + * https://www.analog.com/en/products/ad7383.html + * https://www.analog.com/en/products/ad7384.html =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -21,6 +23,8 @@ properties: enum: - adi,ad7380 - adi,ad7381 + - adi,ad7383 + - adi,ad7384 =20 reg: maxItems: 1 @@ -42,6 +46,16 @@ properties: A 2.5V to 3.3V supply for the external reference voltage. When omitt= ed, the internal 2.5V reference is used. =20 + aina-supply: + description: + The common mode voltage supply for the AINA- pin on pseudo-different= ial + chips. + + ainb-supply: + description: + The common mode voltage supply for the AINB- pin on pseudo-different= ial + chips. + interrupts: description: When the device is using 1-wire mode, this property is used to optio= nally @@ -56,6 +70,24 @@ required: =20 unevaluatedProperties: false =20 +allOf: + # pseudo-differential chips require common mode voltage supplies, + # true differential chips don't use them + - if: + properties: + compatible: + enum: + - adi,ad7383 + - adi,ad7384 + then: + required: + - aina-supply + - ainb-supply + else: + properties: + aina-supply: false + ainb-supply: false + examples: - | #include --=20 2.44.0 From nobody Fri Dec 19 17:43:31 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CDE07E116 for ; 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Tue, 19 Mar 2024 03:11:34 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id je2-20020a05600c1f8200b004133072017csm21096384wmb.42.2024.03.19.03.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:11:33 -0700 (PDT) From: Julien Stephan Date: Tue, 19 Mar 2024 11:11:25 +0100 Subject: [PATCH v5 4/7] iio: adc: ad7380: add support for pseudo-differential parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-4-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan X-Mailer: b4 0.13.0 From: David Lechner Add support for AD7383, AD7384 pseudo-differential compatible parts. Pseudo differential parts require common mode voltage supplies so add the support for them and add the support of IIO_CHAN_INFO_OFFSET to retrieve the offset Signed-off-by: David Lechner Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 98 +++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 85 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index caf6deb3a8b1..996ca83feaed 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -7,6 +7,7 @@ * * Datasheets of supported parts: * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf + * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7383-7384.pdf */ =20 #include @@ -68,16 +69,19 @@ struct ad7380_chip_info { const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; + const char * const *vcm_supplies; + unsigned int num_vcm_supplies; }; =20 -#define AD7380_CHANNEL(index, bits) { \ +#define AD7380_CHANNEL(index, bits, diff) { \ .type =3D IIO_VOLTAGE, \ - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \ .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ .indexed =3D 1, \ - .differential =3D 1, \ - .channel =3D 2 * (index), \ - .channel2 =3D 2 * (index) + 1, \ + .differential =3D (diff), \ + .channel =3D (diff) ? (2 * (index)) : (index), \ + .channel2 =3D (diff) ? (2 * (index) + 1) : 0, \ .scan_index =3D (index), \ .scan_type =3D { \ .sign =3D 's', \ @@ -87,15 +91,23 @@ struct ad7380_chip_info { }, \ } =20 -#define DEFINE_AD7380_2_CHANNEL(name, bits) \ -static const struct iio_chan_spec name[] =3D { \ - AD7380_CHANNEL(0, bits), \ - AD7380_CHANNEL(1, bits), \ - IIO_CHAN_SOFT_TIMESTAMP(2), \ +#define DEFINE_AD7380_2_CHANNEL(name, bits, diff) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits, diff), \ + AD7380_CHANNEL(1, bits, diff), \ + IIO_CHAN_SOFT_TIMESTAMP(2), \ } =20 -DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16); -DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14); +/* fully differential */ +DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1); +DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1); +/* pseudo differential */ +DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0); +DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0); + +static const char * const ad7380_2_channel_vcm_supplies[] =3D { + "aina", "ainb", +}; =20 /* Since this is simultaneous sampling, we don't allow individual channels= . */ static const unsigned long ad7380_2_channel_scan_masks[] =3D { @@ -115,11 +127,28 @@ static const struct ad7380_chip_info ad7381_chip_info= =3D { .num_channels =3D ARRAY_SIZE(ad7381_channels), }; =20 +static const struct ad7380_chip_info ad7383_chip_info =3D { + .name =3D "ad7383", + .channels =3D ad7383_channels, + .num_channels =3D ARRAY_SIZE(ad7383_channels), + .vcm_supplies =3D ad7380_2_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), +}; + +static const struct ad7380_chip_info ad7384_chip_info =3D { + .name =3D "ad7384", + .channels =3D ad7384_channels, + .num_channels =3D ARRAY_SIZE(ad7384_channels), + .vcm_supplies =3D ad7380_2_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; struct regmap *regmap; unsigned int vref_mv; + unsigned int vcm_mv[2]; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. @@ -304,6 +333,11 @@ static int ad7380_read_raw(struct iio_dev *indio_dev, *val2 =3D chan->scan_type.realbits; =20 return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_OFFSET: + *val =3D st->vcm_mv[chan->channel] * (1 << chan->scan_type.realbits) + / st->vref_mv; + + return IIO_VAL_INT; } =20 return -EINVAL; @@ -350,7 +384,7 @@ static int ad7380_probe(struct spi_device *spi) struct iio_dev *indio_dev; struct ad7380_state *st; struct regulator *vref; - int ret; + int ret, i; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); if (!indio_dev) @@ -394,6 +428,40 @@ static int ad7380_probe(struct spi_device *spi) st->vref_mv =3D AD7380_INTERNAL_REF_MV; } =20 + if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) + return dev_err_probe(&spi->dev, -EINVAL, + "invalid number of VCM supplies\n"); + + /* + * pseudo-differential chips have common mode supplies for the negative + * input pin. + */ + for (i =3D 0; i < st->chip_info->num_vcm_supplies; i++) { + struct regulator *vcm; + + vcm =3D devm_regulator_get_optional(&spi->dev, + st->chip_info->vcm_supplies[i]); + if (IS_ERR(vcm)) + return dev_err_probe(&spi->dev, PTR_ERR(vcm), + "Failed to get %s regulator\n", + st->chip_info->vcm_supplies[i]); + + ret =3D regulator_enable(vcm); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&spi->dev, + ad7380_regulator_disable, vcm); + if (ret) + return ret; + + ret =3D regulator_get_voltage(vcm); + if (ret < 0) + return ret; + + st->vcm_mv[i] =3D ret / 1000; + } + st->regmap =3D devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_confi= g); if (IS_ERR(st->regmap)) return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), @@ -422,12 +490,16 @@ static int ad7380_probe(struct spi_device *spi) static const struct of_device_id ad7380_of_match_table[] =3D { { .compatible =3D "adi,ad7380", .data =3D &ad7380_chip_info }, { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, + { .compatible =3D "adi,ad7383", .data =3D &ad7383_chip_info }, + { .compatible =3D "adi,ad7384", .data =3D &ad7384_chip_info }, { } }; =20 static const struct spi_device_id ad7380_id_table[] =3D { { "ad7380", (kernel_ulong_t)&ad7380_chip_info }, { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, + { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, + { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, { } }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-5-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan X-Mailer: b4 0.13.0 The current driver supports only parts with 2 channels. In order to prepare the support of new compatible ADCs with more channels, this commit: - defines MAX_NUM_CHANNEL to specify the maximum number of channels currently supported by the driver - adds available_scan_mask member in ad7380_chip_info structure - fixes spi xfer struct len depending on number of channels - fixes scan_data.raw buffer size to handle more channels - adds a timing specifications structure in ad7380_chip_info structure Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 996ca83feaed..3aca41ce9a14 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -29,6 +29,7 @@ #include #include =20 +#define MAX_NUM_CHANNELS 2 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 =20 @@ -65,12 +66,19 @@ #define AD7380_ALERT_LOW_TH GENMASK(11, 0) #define AD7380_ALERT_HIGH_TH GENMASK(11, 0) =20 +#define T_CONVERT_NS 190 /* conversion time */ +struct ad7380_timing_specs { + const unsigned int t_csh_ns; /* CS minimum high time */ +}; + struct ad7380_chip_info { const char *name; const struct iio_chan_spec *channels; unsigned int num_channels; const char * const *vcm_supplies; unsigned int num_vcm_supplies; + const unsigned long *available_scan_masks; + const struct ad7380_timing_specs *timing_specs; }; =20 #define AD7380_CHANNEL(index, bits, diff) { \ @@ -115,16 +123,24 @@ static const unsigned long ad7380_2_channel_scan_mask= s[] =3D { 0 }; =20 +static const struct ad7380_timing_specs ad7380_timing =3D { + .t_csh_ns =3D 10, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, .num_channels =3D ARRAY_SIZE(ad7380_channels), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7381_chip_info =3D { .name =3D "ad7381", .channels =3D ad7381_channels, .num_channels =3D ARRAY_SIZE(ad7381_channels), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7383_chip_info =3D { @@ -133,6 +149,8 @@ static const struct ad7380_chip_info ad7383_chip_info = =3D { .num_channels =3D ARRAY_SIZE(ad7383_channels), .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 static const struct ad7380_chip_info ad7384_chip_info =3D { @@ -141,6 +159,8 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .num_channels =3D ARRAY_SIZE(ad7384_channels), .vcm_supplies =3D ad7380_2_channel_vcm_supplies, .num_vcm_supplies =3D ARRAY_SIZE(ad7380_2_channel_vcm_supplies), + .available_scan_masks =3D ad7380_2_channel_scan_masks, + .timing_specs =3D &ad7380_timing, }; =20 struct ad7380_state { @@ -148,15 +168,15 @@ struct ad7380_state { struct spi_device *spi; struct regmap *regmap; unsigned int vref_mv; - unsigned int vcm_mv[2]; + unsigned int vcm_mv[MAX_NUM_CHANNELS]; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. - * Make the buffer large enough for 2 16-bit samples and one 64-bit + * Make the buffer large enough for MAX_NUM_CHANNELS 16-bit samples and o= ne 64-bit * aligned 64 bit timestamp. */ struct { - u16 raw[2]; + u16 raw[MAX_NUM_CHANNELS]; =20 s64 ts __aligned(8); } scan_data __aligned(IIO_DMA_MINALIGN); @@ -194,7 +214,7 @@ static int ad7380_regmap_reg_read(void *context, unsign= ed int reg, .tx_buf =3D &st->tx, .cs_change =3D 1, .cs_change_delay =3D { - .value =3D 10, /* t[CSH] */ + .value =3D st->chip_info->timing_specs->t_csh_ns, .unit =3D SPI_DELAY_UNIT_NSECS, }, }, { @@ -255,7 +275,8 @@ static irqreturn_t ad7380_trigger_handler(int irq, void= *p) struct ad7380_state *st =3D iio_priv(indio_dev); struct spi_transfer xfer =3D { .bits_per_word =3D st->chip_info->channels[0].scan_type.realbits, - .len =3D 4, + .len =3D (st->chip_info->num_channels - 1) * + ((st->chip_info->channels->scan_type.storagebits > 16) ? 4 : 2), .rx_buf =3D st->scan_data.raw, }; int ret; @@ -282,21 +303,22 @@ static int ad7380_read_direct(struct ad7380_state *st, .speed_hz =3D AD7380_REG_WR_SPEED_HZ, .bits_per_word =3D chan->scan_type.realbits, .delay =3D { - .value =3D 190, /* t[CONVERT] */ + .value =3D T_CONVERT_NS, .unit =3D SPI_DELAY_UNIT_NSECS, }, .cs_change =3D 1, .cs_change_delay =3D { - .value =3D 10, /* t[CSH] */ + .value =3D st->chip_info->timing_specs->t_csh_ns, .unit =3D SPI_DELAY_UNIT_NSECS, }, }, - /* then read both channels */ + /* then read all channels */ { .speed_hz =3D AD7380_REG_WR_SPEED_HZ, .bits_per_word =3D chan->scan_type.realbits, .rx_buf =3D st->scan_data.raw, - .len =3D 4, + .len =3D (st->chip_info->num_channels - 1) * + ((chan->scan_type.storagebits > 16) ? 4 : 2), }, }; int ret; @@ -472,7 +494,7 @@ static int ad7380_probe(struct spi_device *spi) indio_dev->name =3D st->chip_info->name; indio_dev->info =3D &ad7380_info; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->available_scan_masks =3D ad7380_2_channel_scan_masks; + indio_dev->available_scan_masks =3D st->chip_info->available_scan_masks; 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Tue, 19 Mar 2024 03:11:35 -0700 (PDT) From: Julien Stephan Date: Tue, 19 Mar 2024 11:11:27 +0100 Subject: [PATCH v5 6/7] dt-bindings: iio: adc: ad7380: add support for ad738x-4 4 channels variants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-6-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan X-Mailer: b4 0.13.0 Add compatible support for ad7380/1/3/4-4 parts which are 4 channels variants from ad7380/1/3/4 Signed-off-by: Julien Stephan Acked-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index de3d28a021ae..899b777017ce 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -15,6 +15,10 @@ description: | * https://www.analog.com/en/products/ad7381.html * https://www.analog.com/en/products/ad7383.html * https://www.analog.com/en/products/ad7384.html + * https://www.analog.com/en/products/ad7380-4.html + * https://www.analog.com/en/products/ad7381-4.html + * https://www.analog.com/en/products/ad7383-4.html + * https://www.analog.com/en/products/ad7384-4.html =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -25,6 +29,10 @@ properties: - adi,ad7381 - adi,ad7383 - adi,ad7384 + - adi,ad7380-4 + - adi,ad7381-4 + - adi,ad7383-4 + - adi,ad7384-4 =20 reg: maxItems: 1 @@ -56,6 +64,16 @@ properties: The common mode voltage supply for the AINB- pin on pseudo-different= ial chips. =20 + ainc-supply: + description: + The common mode voltage supply for the AINC- pin on pseudo-different= ial + chips. + + aind-supply: + description: + The common mode voltage supply for the AIND- pin on pseudo-different= ial + chips. + interrupts: description: When the device is using 1-wire mode, this property is used to optio= nally @@ -79,6 +97,8 @@ allOf: enum: - adi,ad7383 - adi,ad7384 + - adi,ad7383-4 + - adi,ad7384-4 then: required: - aina-supply @@ -87,6 +107,20 @@ allOf: properties: aina-supply: false ainb-supply: false + - if: + properties: + compatible: + enum: + - adi,ad7383-4 + - adi,ad7384-4 + then: + required: + - ainc-supply + - aind-supply + else: + properties: + ainc-supply: false + aind-supply: false =20 examples: - | --=20 2.44.0 From nobody Fri Dec 19 17:43:31 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 787227EEF5 for ; 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Tue, 19 Mar 2024 03:11:36 -0700 (PDT) Received: from [192.168.1.63] ([2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id je2-20020a05600c1f8200b004133072017csm21096384wmb.42.2024.03.19.03.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:11:36 -0700 (PDT) From: Julien Stephan Date: Tue, 19 Mar 2024 11:11:28 +0100 Subject: [PATCH v5 7/7] iio: adc: ad7380: add support for ad738x-4 4 channels variants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240319-adding-new-ad738x-driver-v5-7-ce7df004ceb3@baylibre.com> References: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> In-Reply-To: <20240319-adding-new-ad738x-driver-v5-0-ce7df004ceb3@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot , Julien Stephan X-Mailer: b4 0.13.0 Add support for ad7380/1/2/3-4 parts which are 4 channels variants from ad7380/1/2/3 Signed-off-by: Julien Stephan --- drivers/iio/adc/ad7380.c | 75 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index 3aca41ce9a14..cf9d2ace5f20 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -8,6 +8,9 @@ * Datasheets of supported parts: * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data= -sheets/AD7380-7381.pdf * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7383-7384.pdf + * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7380-4.pdf + * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data= -sheets/ad7381-4.pdf + * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/da= ta-sheets/ad7383-4-ad7384-4.pdf */ =20 #include @@ -29,7 +32,7 @@ #include #include =20 -#define MAX_NUM_CHANNELS 2 +#define MAX_NUM_CHANNELS 4 /* 2.5V internal reference voltage */ #define AD7380_INTERNAL_REF_MV 2500 =20 @@ -106,27 +109,53 @@ static const struct iio_chan_spec name[] =3D { \ IIO_CHAN_SOFT_TIMESTAMP(2), \ } =20 +#define DEFINE_AD7380_4_CHANNEL(name, bits, diff) \ +static const struct iio_chan_spec name[] =3D { \ + AD7380_CHANNEL(0, bits, diff), \ + AD7380_CHANNEL(1, bits, diff), \ + AD7380_CHANNEL(2, bits, diff), \ + AD7380_CHANNEL(3, bits, diff), \ + IIO_CHAN_SOFT_TIMESTAMP(4), \ +} + /* fully differential */ DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1); DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1); +DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1); +DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1); /* pseudo differential */ DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0); DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0); +DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0); +DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0); =20 static const char * const ad7380_2_channel_vcm_supplies[] =3D { "aina", "ainb", }; =20 +static const char * const ad7380_4_channel_vcm_supplies[] =3D { + "aina", "ainb", "ainc", "aind", +}; + /* Since this is simultaneous sampling, we don't allow individual channels= . */ static const unsigned long ad7380_2_channel_scan_masks[] =3D { GENMASK(1, 0), 0 }; =20 +static const unsigned long ad7380_4_channel_scan_masks[] =3D { + GENMASK(3, 0), + 0 +}; + static const struct ad7380_timing_specs ad7380_timing =3D { .t_csh_ns =3D 10, }; =20 +static const struct ad7380_timing_specs ad7380_4_timing =3D { + .t_csh_ns =3D 20, +}; + static const struct ad7380_chip_info ad7380_chip_info =3D { .name =3D "ad7380", .channels =3D ad7380_channels, @@ -163,6 +192,42 @@ static const struct ad7380_chip_info ad7384_chip_info = =3D { .timing_specs =3D &ad7380_timing, }; =20 +static const struct ad7380_chip_info ad7380_4_chip_info =3D { + .name =3D "ad7380-4", + .channels =3D ad7380_4_channels, + .num_channels =3D ARRAY_SIZE(ad7380_4_channels), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7381_4_chip_info =3D { + .name =3D "ad7381-4", + .channels =3D ad7381_4_channels, + .num_channels =3D ARRAY_SIZE(ad7381_4_channels), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7383_4_chip_info =3D { + .name =3D "ad7383-4", + .channels =3D ad7383_4_channels, + .num_channels =3D ARRAY_SIZE(ad7383_4_channels), + .vcm_supplies =3D ad7380_4_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + +static const struct ad7380_chip_info ad7384_4_chip_info =3D { + .name =3D "ad7384-4", + .channels =3D ad7384_4_channels, + .num_channels =3D ARRAY_SIZE(ad7384_4_channels), + .vcm_supplies =3D ad7380_4_channel_vcm_supplies, + .num_vcm_supplies =3D ARRAY_SIZE(ad7380_4_channel_vcm_supplies), + .available_scan_masks =3D ad7380_4_channel_scan_masks, + .timing_specs =3D &ad7380_4_timing, +}; + struct ad7380_state { const struct ad7380_chip_info *chip_info; struct spi_device *spi; @@ -514,6 +579,10 @@ static const struct of_device_id ad7380_of_match_table= [] =3D { { .compatible =3D "adi,ad7381", .data =3D &ad7381_chip_info }, { .compatible =3D "adi,ad7383", .data =3D &ad7383_chip_info }, { .compatible =3D "adi,ad7384", .data =3D &ad7384_chip_info }, + { .compatible =3D "adi,ad7380-4", .data =3D &ad7380_4_chip_info }, + { .compatible =3D "adi,ad7381-4", .data =3D &ad7381_4_chip_info }, + { .compatible =3D "adi,ad7383-4", .data =3D &ad7383_4_chip_info }, + { .compatible =3D "adi,ad7384-4", .data =3D &ad7384_4_chip_info }, { } }; =20 @@ -522,6 +591,10 @@ static const struct spi_device_id ad7380_id_table[] = =3D { { "ad7381", (kernel_ulong_t)&ad7381_chip_info }, { "ad7383", (kernel_ulong_t)&ad7383_chip_info }, { "ad7384", (kernel_ulong_t)&ad7384_chip_info }, + { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info }, + { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info }, + { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info }, + { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7380_id_table); --=20 2.44.0