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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:07 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:39:55 +0800 Subject: [PATCH v3 2/7] riscv: smp: fail booting up smp if inconsistent vlen is detected Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240318-zve-detection-v3-2-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.13-dev-a684c Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vect= or context") Reported-by: Conor Dooley Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8= eb5fe5730@spud/ Signed-off-by: Andy Chiu --- Changelog v2: - update commit message to explain asm code change (Conor) --- arch/riscv/kernel/head.S | 14 +++++++------- arch/riscv/kernel/smpboot.c | 14 +++++++++----- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..a158fa9f2656 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -165,9 +165,15 @@ secondary_start_sbi: #endif call .Lsetup_trap_vector scs_load_current - tail smp_callin + call smp_callin #endif /* CONFIG_SMP */ =20 +.align 2 +.Lsecondary_park: + /* We lack SMP support or have too many harts, so park this hart */ + wfi + j .Lsecondary_park + .align 2 .Lsetup_trap_vector: /* Set trap vector to exception handler */ @@ -181,12 +187,6 @@ secondary_start_sbi: csrw CSR_SCRATCH, zero ret =20 -.align 2 -.Lsecondary_park: - /* We lack SMP support or have too many harts, so park this hart */ - wfi - j .Lsecondary_park - SYM_CODE_END(_start) =20 SYM_CODE_START(_start_kernel) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index cfbe4b840d42..1f86ee10192f 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -218,6 +218,15 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm =3D &init_mm; unsigned int curr_cpuid =3D smp_processor_id(); =20 + if (has_vector()) { + /* + * Return as early as possible so the hart with a mismatching + * vlen won't boot. + */ + if (riscv_v_setup_vsize()) + return; + } + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm =3D mm; @@ -230,11 +239,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); =20 - if (has_vector()) { - if (riscv_v_setup_vsize()) - elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; - } - riscv_user_isa_enable(); =20 /* --=20 2.44.0.rc2