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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:04 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:39:54 +0800 Subject: [PATCH v3 1/7] riscv: vector: add a comment when calling riscv_setup_vsize() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240318-zve-detection-v3-1-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.13-dev-a684c The function would fail when it detects the calling hart's vlen doesn't match the first one's. The boot hart is the first hart calling this function during riscv_fill_hwcap, so it is impossible to fail here. Add a comment about this behavior. Signed-off-by: Andy Chiu --- Changelog v2: - update the comment (Conor) --- arch/riscv/kernel/cpufeature.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index afeae3ff43dc..db9fb90cb272 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -658,6 +658,10 @@ void __init riscv_fill_hwcap(void) } =20 if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + /* + * This callsite can't fail here. It cannot fail when called on + * the boot hart. + */ riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but --=20 2.44.0.rc2 From nobody Sun Feb 8 05:28:42 2026 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 905652EB14 for ; Mon, 18 Mar 2024 10:40:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710758410; cv=none; b=WFIya6flHOOy7f6m+4nOX0Ke2k1A+WYDm2SA0dXswvZz6eUBjZasO/rr89/sr+s4uLbJ53FiWe5GoVPqs4X36leRwTwHyyjxKcaKvJODCDCMOX4L+xZ2B3ix7ShgIPuLn56RyKowOrRfUlWL3NHHAygZq4wsHTEo6g4CIHi48f8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710758410; c=relaxed/simple; bh=mWlzxMbIZuWLXbPXbdzePV4/OdHCOixoEUI0M1hFEvU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TbeXiMsfhYD2wE7tUMw/URo3YVBizTjxo8bjg8U8udC7AMfDqJnwaix4ktjDavBFxyLaL/Mf1WDis3Qsjf876lv/24POlWD6FVVezj9pFp1xRkAau8V/lmaZ9P8mxUXru9DVTOJiGSJOKpkY/7VS9eZ+t9UAE8CPYyTvdhMkq/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=L/KAllU8; arc=none smtp.client-ip=209.85.210.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="L/KAllU8" Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-6e6adc557b6so3926326b3a.2 for ; Mon, 18 Mar 2024 03:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1710758408; x=1711363208; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lQUHrqHWjcyGyF/NEsfpZqczPZC6iW3/Q7JuMvHiRfE=; b=L/KAllU8PCNCdT2CgaOP6jFTNz3qN/DAHOezgjsWw4wOf/+UTTcT2m4weM7wpXoHeM SdnttVQscSw6wtu/ACVl+S53YkbW3nJOjV8DPaxrWlm6SgYhx2TkE91bCBUNKAiILXfR ozaA97Kp6ZNgyCBhQ2gD1tWxP6bFtS+wpnVFI2vmlUmyIAuviddnKiZwwsFXZ53JJqb3 Tx5yruLTcmuTrfewQ0vmrLUR5O5O9oOw9ZMkqz6xgmYSjuOEsIXVxyarvthgK5ztVNoJ EoQ/9MEHT8IcetgD6GG0beUJa76yZr6LRq25CaGajw4sUVxN0bUMlaAOytqiFpx71Wqp stkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710758408; x=1711363208; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lQUHrqHWjcyGyF/NEsfpZqczPZC6iW3/Q7JuMvHiRfE=; b=F/47bJ8lspLBzG6Rs5sm2hsyF5u7WsISMs5mxJwgnlBZud/vqOtVtfPfDmg6OBvfrd fqh8Gd5vNwcy4u11FIYjUtWKM7rOH+e5BB3EzU2UxWRamMijmREGQyECacHSClRAqaar LJTW765IaTn0rvieh+Y1i9sm8CzQMCgSwE6l3p7FPkN6IZo/Xt5S8rgOpwdSPJ0tBXnL 8yzrAhlES9QlV708nwJK5K7GD8jlwjxz5uN9VT7fd/RNSv09nlfoDuFyxyybitehM5SD NoZGF/fjMuLw3zdPUN72e0eneLYWsGsbOSpSSr/Xutz8SGlaBVuuydR32f1E8mSN7H8h vXCw== X-Forwarded-Encrypted: i=1; AJvYcCXKEovIbsHCYuLJbzPLUiw6BJrdZnJ8gz8GMFO6XcMQDfcRH6aX/pRjCaujimKdGwjAFidjPOuNy9dJMDo/VUDcXTGO0iqLOGadCIVS X-Gm-Message-State: AOJu0YyN5FpI7pxzZdWT0BNo3shkO7Q0PWEcB9wEpBfmv27gB3y/V/gs S6THzHHMXd546mgGo9dDFihUt8UGqT2okqPKBCcXEIxVsvtjIqs/9otsgNTcBGA= X-Google-Smtp-Source: AGHT+IHBRt10B3JNwV8vX+UWPVBlF2Eg87pHt2EqyuL8zRUXC32dZPfWh7m+ZkrSI2TISV+eofA7Yg== X-Received: by 2002:a05:6a00:816:b0:6e7:2018:aabd with SMTP id m22-20020a056a00081600b006e72018aabdmr4873937pfk.8.1710758408088; Mon, 18 Mar 2024 03:40:08 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:07 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:39:55 +0800 Subject: [PATCH v3 2/7] riscv: smp: fail booting up smp if inconsistent vlen is detected Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240318-zve-detection-v3-2-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.13-dev-a684c Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vect= or context") Reported-by: Conor Dooley Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8= eb5fe5730@spud/ Signed-off-by: Andy Chiu --- Changelog v2: - update commit message to explain asm code change (Conor) --- arch/riscv/kernel/head.S | 14 +++++++------- arch/riscv/kernel/smpboot.c | 14 +++++++++----- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..a158fa9f2656 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -165,9 +165,15 @@ secondary_start_sbi: #endif call .Lsetup_trap_vector scs_load_current - tail smp_callin + call smp_callin #endif /* CONFIG_SMP */ =20 +.align 2 +.Lsecondary_park: + /* We lack SMP support or have too many harts, so park this hart */ + wfi + j .Lsecondary_park + .align 2 .Lsetup_trap_vector: /* Set trap vector to exception handler */ @@ -181,12 +187,6 @@ secondary_start_sbi: csrw CSR_SCRATCH, zero ret =20 -.align 2 -.Lsecondary_park: - /* We lack SMP support or have too many harts, so park this hart */ - wfi - j .Lsecondary_park - SYM_CODE_END(_start) =20 SYM_CODE_START(_start_kernel) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index cfbe4b840d42..1f86ee10192f 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -218,6 +218,15 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm =3D &init_mm; unsigned int curr_cpuid =3D smp_processor_id(); =20 + if (has_vector()) { + /* + * Return as early as possible so the hart with a mismatching + * vlen won't boot. + */ + if (riscv_v_setup_vsize()) + return; + } + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm =3D mm; @@ -230,11 +239,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); =20 - if (has_vector()) { - if (riscv_v_setup_vsize()) - elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; - } - riscv_user_isa_enable(); =20 /* --=20 2.44.0.rc2 From nobody Sun Feb 8 05:28:42 2026 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEDAD364A7 for ; Mon, 18 Mar 2024 10:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:11 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:39:56 +0800 Subject: [PATCH v3 3/7] riscv: cpufeature: call match_isa_ext() for single-letter extensions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240318-zve-detection-v3-3-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.13-dev-a684c Single-letter extensions may also imply multiple subextensions. For example, Vector extension implies zve64d, and zve64d implies zve64f. Extension parsing for "riscv,isa-extensions" has the ability to resolve the dependency by calling match_isa_ext(). This patch makes deprecated parser call the same function for single letter extensions. Signed-off-by: Andy Chiu --- Changelog v3: - Remove set_bit for single-letter extensions as they are all checked in match_isa_ext. (Cl=C3=A9ment) --- arch/riscv/kernel/cpufeature.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index db9fb90cb272..cbdd63165e85 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -457,16 +457,15 @@ static void __init riscv_parse_isa_string(unsigned lo= ng *this_hwcap, struct risc =20 if (unlikely(ext_err)) continue; + + for (int i =3D 0; i < riscv_isa_ext_count; i++) + match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); + if (!ext_long) { int nr =3D tolower(*ext) - 'a'; =20 - if (riscv_isa_extension_check(nr)) { + if (riscv_isa_extension_check(nr)) *this_hwcap |=3D isa2hwcap[nr]; - set_bit(nr, isainfo->isa); - } - } else { - for (int i =3D 0; i < riscv_isa_ext_count; i++) - match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); } } } --=20 2.44.0.rc2 From nobody Sun Feb 8 05:28:42 2026 Received: from mail-oi1-f173.google.com (mail-oi1-f173.google.com [209.85.167.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61EEC36AF8 for ; Mon, 18 Mar 2024 10:40:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710758417; cv=none; b=mLewXOwscK9h240K/xKeu0Y6LXuvZTuwphnS0zSv+6aJQRNH8YP0wzD3/zcqf2zXiFhcLAfJ2ph8bI7Y8uAQEQnIdCxDyESbVg5/QS9uU/692FhmND3mnHC+IQJAGAR69yIMxVu8DuVFtcM+zwast12EpBvYsoiEN2ZIzgR8B4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710758417; c=relaxed/simple; bh=DJ3PWtnNU805CN/0jpeY/+ABkiC+sQKo9gh6Hsyv3SE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PzYrPH6DQKap+F4HW/+yi9NmCMXtUc1/coWq9PTV+YStq3U0owS/VgFrLUr4AfY14t2cuowrzNyxS4itHZyCRjtFskJnzGeZDnAcyerKr5DV1564iTFCC3tlWgZTFY34kzL+HDtwJq8BAoknhMBd+I2g+fHb3QylFsUo6kVZuPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=bnjHSg5I; arc=none smtp.client-ip=209.85.167.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="bnjHSg5I" Received: by mail-oi1-f173.google.com with SMTP id 5614622812f47-3c38855957cso679603b6e.3 for ; Mon, 18 Mar 2024 03:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1710758414; x=1711363214; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=iCQe6vm/oJxMTsi/9kKYpE7XwZ+h04uGmZi4xHD22QU=; b=bnjHSg5II2IEccumtfH8sR++/nlkTnFLMUptkD8ofUj6Q172e4YN5Ji6suaASYcnzX cuQgowLqBzvjYPdaCMdggeaVFwbS9o1N2Dxy/UJt5at9xeUIvpjNjs4VOIf4nH9xiVt2 nsl0dIOUQWScYUSAs+eIHzzPH87ZFx40c1YS+eIqGiZljdFSVnzJ9s7MX9om27inIdM5 T52uTFkkNWZglG0uJsDIcoh6Q6OoLkYzXc2YwVXa32dXEw+jrzFHysCzDAI5kwBTACsU SxtsTVoOdoYtcn9Zz/1nC3aBpHrmRQqR62h8fjm3OKVbvZGr6LOd8Eb7dRLX0hCyauYz to0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710758414; x=1711363214; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iCQe6vm/oJxMTsi/9kKYpE7XwZ+h04uGmZi4xHD22QU=; b=riX/lATrXKRoraCzOMT3qJ5s4zL//hCwiIGg6roQ/kzuFfn+ERPJBzJRZwKuyrT/wC 2p32vDEqRN+KtMjM3iKlgPYizhb2Ib5yq6QL6ZTVCo7nYDLGN4bCoi3C26oRZZEKHZCr vmwguwQhcdbbcYp2Z78ilW0d48BvQ6+bu5ZCKc5lFnQn0qWioLAjDlO11yHGLgb0RoYP EFtClai8nfW43ZmDsAK8R9TgBV4+q9z8mfTGyeTPhatRkm08nzlUY4/NyJOc7ghHir9e gdiME+UT/Wdh0n77/Hnfl1ySgTBjK530wOtsJXaMvn8MEy3MKdOUY3a+z33u8ce5zKrt 7BBQ== X-Forwarded-Encrypted: i=1; AJvYcCXGNGJkaehCbXD2p14ksNIZAsRyOFBhTvKaQLLDwsMe57kdo8g75S4bdiRpwxE8LBC3qUCLwwsux+vGpFqVB9NDSJ+LneTjrEP1hfHa X-Gm-Message-State: AOJu0YyoLuZ9+sOLnyEHtS+0m4jCYGkRawd0FM4O4HEGHmujMPFoABGr 4PDdP42m0QnaUgncXGDdEaQ2kEOygbIQ3vB2HMIC1IlhzeEv4/d1soZSACAk0zo= X-Google-Smtp-Source: AGHT+IGdrnrLbW+USxO7ZpyEu3j4S8IlYwCytamjxZATZlbSTeWt8QSbTr/yKlh7P89dlOk6bQ1eFA== X-Received: by 2002:a05:6808:19a1:b0:3c2:355c:e68 with SMTP id bj33-20020a05680819a100b003c2355c0e68mr13595173oib.5.1710758414484; Mon, 18 Mar 2024 03:40:14 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:14 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:39:57 +0800 Subject: [PATCH v3 4/7] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240318-zve-detection-v3-4-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org X-Mailer: b4 0.13-dev-a684c Multiple Vector subextensions are added. Also, the patch takes care of the dependencies of Vector subextensions by macro expansions. So, if some "embedded" platform only reports "zve64f" on the ISA string, the parser is able to expand it to zve32x zve32f zve64x and zve64f. Signed-off-by: Andy Chiu --- Changelog v3: - renumber RISCV_ISA_EXT_ZVE* to rebase on top of 6.9 - alphabetically sort added extensions (Cl=C3=A9ment) Changelog v2: - remove the extension itself from its isa_exts[] list (Cl=C3=A9ment) - use riscv_zve64d_exts for v's extension list (Samuel) --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index bae7eac76c18..0a05c4e6dcec 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,11 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_ZVE32X 75 +#define RISCV_ISA_EXT_ZVE32F 76 +#define RISCV_ISA_EXT_ZVE64X 77 +#define RISCV_ISA_EXT_ZVE64F 78 +#define RISCV_ISA_EXT_ZVE64D 79 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index cbdd63165e85..6e294a35a4b0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -187,6 +187,35 @@ static const unsigned int riscv_zvbb_exts[] =3D { RISCV_ISA_EXT_ZVKB }; =20 +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE32X, + +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64X, \ + RISCV_ISA_EXT_ZVE32F, \ + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST + +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64F, \ + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST + +static const unsigned int riscv_zve32f_exts[] =3D { + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST +}; + +static const unsigned int riscv_zve64f_exts[] =3D { + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST +}; + +static const unsigned int riscv_zve64d_exts[] =3D { + RISCV_ISA_EXT_ZVE64D_IMPLY_LIST +}; + +static const unsigned int riscv_zve64x_exts[] =3D { + RISCV_ISA_EXT_ZVE32X, + RISCV_ISA_EXT_ZVE64X +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -234,7 +263,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), - __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_zve64d_exts), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), @@ -269,6 +298,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), + __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), + __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), + __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), + __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), --=20 2.44.0.rc2 From nobody Sun Feb 8 05:28:42 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ACEE37159 for ; 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Signed-off-by: Andy Chiu --- Changelog v3: - Correct extension names and their order (Stefan) Changelog v2: - new patch since v2 --- .../devicetree/bindings/riscv/extensions.yaml | 30 ++++++++++++++++++= ++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..cfed80ad5540 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -381,6 +381,36 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + - const: zve32f + description: + The standard Zve32f extension for embedded processors, as rati= fied + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve32x + description: + The standard Zve32x extension for embedded processors, as rati= fied + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64d + description: + The standard Zve64d extension for embedded processors, as rati= fied + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64f + description: + The standard Zve64f extension for embedded processors, as rati= fied + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64x + description: + The standard Zve64x extension for embedded processors, as rati= fied + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + - const: zvfh description: The standard Zvfh extension for vectored half-precision --=20 2.44.0.rc2 From nobody Sun Feb 8 05:28:42 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 995D63770C for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:20 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:39:59 +0800 Subject: [PATCH v3 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240318-zve-detection-v3-6-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= X-Mailer: b4 0.13-dev-a684c The following Vector subextensions for "embedded" platforms are added into RISCV_HWPROBE_KEY_IMA_EXT_0: - ZVE32X - ZVE32F - ZVE64X - ZVE64F - ZVE64D Extensions ending with an X indicates that the platform doesn't have a vector FPU. Extensions ending with F/D mean that whether single (F) or double (D) precision vector operation is supported. The number 32 or 64 follows from ZVE tells the maximum element length. Signed-off-by: Andy Chiu Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- Changelog v2: - zve* extensions in hwprobe depends on whether kernel supports v, so include them after has_vector(). Fix a typo. (Cl=C3=A9ment) --- Documentation/arch/riscv/hwprobe.rst | 15 +++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_hwprobe.c | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index b2bcc9eed9aa..d0b02e012e5d 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -188,6 +188,21 @@ The following keys are defined: manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is + supported, as defined by version 1.0 of the RISC-V Vector extension ma= nual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is + supported, as defined by version 1.0 of the RISC-V Vector extension ma= nual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is + supported, as defined by version 1.0 of the RISC-V Vector extension ma= nual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is + supported, as defined by version 1.0 of the RISC-V Vector extension ma= nual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is + supported, as defined by version 1.0 of the RISC-V Vector extension ma= nual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 9f2a8e3ff204..b9a0876e969f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -59,6 +59,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) +#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 40) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 8cae41a502dd..c8219b82fbfc 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -113,6 +113,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, EXT_KEY(ZICOND); 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:23 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:40:00 +0800 Subject: [PATCH v3 7/7] riscv: vector: adjust minimum Vector requirement to ZVE32X Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240318-zve-detection-v3-7-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Joel Granados X-Mailer: b4 0.13-dev-a684c Make has_vector take one argument. This argument represents the minimum Vector subextension that the following Vector actions assume. Also, change riscv_v_first_use_handler(), and boot code that calls riscv_v_setup_vsize() to accept the minimum Vector sub-extension, ZVE32X. Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs compiled and run with ZVE32X should be supported by the kernel on most aspects. This includes context-switch, signal, ptrace, prctl, and hwprobe. One exception is that ELF_HWCAP returns 'V' only if full V is supported on the platform. This means that the system without a full V must not rely on ELF_HWCAP to tell whether it is allowable to execute Vector without first invoking a prctl() check. Signed-off-by: Andy Chiu Acked-by: Joel Granados --- Changelog v2: - update the comment in hwprobe. --- arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 21 ++++++++++++++------- arch/riscv/include/asm/xor.h | 2 +- arch/riscv/kernel/cpufeature.c | 5 ++++- arch/riscv/kernel/kernel_mode_vector.c | 4 ++-- arch/riscv/kernel/process.c | 4 ++-- arch/riscv/kernel/signal.c | 6 +++--- arch/riscv/kernel/smpboot.c | 2 +- arch/riscv/kernel/sys_hwprobe.c | 8 ++++++-- arch/riscv/kernel/vector.c | 15 +++++++++------ arch/riscv/lib/uaccess.S | 2 +- 11 files changed, 44 insertions(+), 27 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7efdb0584d47..df1adf196c4f 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -78,7 +78,7 @@ do { \ struct task_struct *__next =3D (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ - if (has_vector()) \ + if (has_vector(ZVE32X)) \ __switch_to_vector(__prev, __next); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index 731dcd0ed4de..b96750493dfb 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -18,6 +18,7 @@ #include #include #include +#include =20 extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -35,10 +36,16 @@ static inline u32 riscv_v_flags(void) return READ_ONCE(current->thread.riscv_v_flags); } =20 -static __always_inline bool has_vector(void) -{ - return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); -} +#define has_vector(VEXT) \ +({ \ + static_assert(RISCV_ISA_EXT_##VEXT =3D=3D RISCV_ISA_EXT_ZVE32X || \ + RISCV_ISA_EXT_##VEXT =3D=3D RISCV_ISA_EXT_ZVE32F || \ + RISCV_ISA_EXT_##VEXT =3D=3D RISCV_ISA_EXT_ZVE64X || \ + RISCV_ISA_EXT_##VEXT =3D=3D RISCV_ISA_EXT_ZVE64F || \ + RISCV_ISA_EXT_##VEXT =3D=3D RISCV_ISA_EXT_ZVE64D || \ + RISCV_ISA_EXT_##VEXT =3D=3D RISCV_ISA_EXT_v); \ + riscv_has_extension_unlikely(RISCV_ISA_EXT_##VEXT); \ +}) =20 static inline void __riscv_v_vstate_clean(struct pt_regs *regs) { @@ -131,7 +138,7 @@ static inline void __riscv_v_vstate_restore(struct __ri= scv_v_ext_state *restore_ riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vle8.v v0, (%1)\n\t" "add %1, %1, %0\n\t" @@ -153,7 +160,7 @@ static inline void __riscv_v_vstate_discard(void) riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vmv.v.i v0, -1\n\t" "vmv.v.i v8, -1\n\t" @@ -267,7 +274,7 @@ bool riscv_v_vstate_ctrl_user_allowed(void); struct pt_regs; =20 static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } -static __always_inline bool has_vector(void) { return false; } +static __always_inline bool has_vector(unsigned long min_sub_ext) { return= false; } static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { retur= n false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return fal= se; } static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h index 96011861e46b..46042ef5a2f7 100644 --- a/arch/riscv/include/asm/xor.h +++ b/arch/riscv/include/asm/xor.h @@ -61,7 +61,7 @@ static struct xor_block_template xor_block_rvv =3D { do { \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_32regs); \ - if (has_vector()) { \ + if (has_vector(ZVE32X)) { \ xor_speed(&xor_block_rvv);\ } \ } while (0) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6e294a35a4b0..3e2a62873f55 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -690,12 +690,15 @@ void __init riscv_fill_hwcap(void) elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; } =20 - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { /* * This callsite can't fail here. It cannot fail when called on * the boot hart. */ riscv_v_setup_vsize(); + } + + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/ker= nel_mode_vector.c index 6afe80c7f03a..0d4d1a03d1c7 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -208,7 +208,7 @@ void kernel_vector_begin(void) { bool nested =3D false; =20 - if (WARN_ON(!has_vector())) + if (WARN_ON(!has_vector(ZVE32X))) return; =20 BUG_ON(!may_use_simd()); @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin); */ void kernel_vector_end(void) { - if (WARN_ON(!has_vector())) + if (WARN_ON(!has_vector(ZVE32X))) return; =20 riscv_v_disable(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 92922dbd5b5c..919e72f9fff6 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -178,7 +178,7 @@ void flush_thread(void) void arch_release_task_struct(struct task_struct *tsk) { /* Free the vector context of datap. */ - if (has_vector()) + if (has_vector(ZVE32X)) riscv_v_thread_free(tsk); } =20 @@ -225,7 +225,7 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) p->thread.s[0] =3D 0; } p->thread.riscv_v_flags =3D 0; - if (has_vector()) + if (has_vector(ZVE32X)) riscv_v_thread_alloc(p); p->thread.ra =3D (unsigned long)ret_from_fork; p->thread.sp =3D (unsigned long)childregs; /* kernel sp */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 501e66debf69..a96e6e969a3f 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -188,7 +188,7 @@ static long restore_sigcontext(struct pt_regs *regs, =20 return 0; case RISCV_V_MAGIC: - if (!has_vector() || !riscv_v_vstate_query(regs) || + if (!has_vector(ZVE32X) || !riscv_v_vstate_query(regs) || size !=3D riscv_v_sc_size) return -EINVAL; =20 @@ -210,7 +210,7 @@ static size_t get_rt_frame_size(bool cal_all) =20 frame_size =3D sizeof(*frame); =20 - if (has_vector()) { + if (has_vector(ZVE32X)) { if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size +=3D riscv_v_sc_size; } @@ -283,7 +283,7 @@ static long setup_sigcontext(struct rt_sigframe __user = *frame, if (has_fpu()) err |=3D save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if (has_vector() && riscv_v_vstate_query(regs)) + if (has_vector(ZVE32X) && riscv_v_vstate_query(regs)) err |=3D save_v_state(regs, (void __user **)&sc_ext_ptr); /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |=3D __put_user(0, &sc->sc_extdesc.reserved); diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 1f86ee10192f..4eb36d75f091 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -218,7 +218,7 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm =3D &init_mm; unsigned int curr_cpuid =3D smp_processor_id(); =20 - if (has_vector()) { + if (has_vector(ZVE32X)) { /* * Return as early as possible so the hart with a mismatching * vlen won't boot. diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index c8219b82fbfc..e7c3fcac62a1 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -69,7 +69,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (riscv_isa_extension_available(NULL, c)) pair->value |=3D RISCV_HWPROBE_IMA_C; =20 - if (has_vector()) + if (has_vector(v)) pair->value |=3D RISCV_HWPROBE_IMA_V; =20 /* @@ -112,7 +112,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, EXT_KEY(ZACAS); EXT_KEY(ZICOND); =20 - if (has_vector()) { + /* + * Vector crypto and ZVE* extensions are supported only if + * kernel has minimum V support of ZVE32X. + */ + if (has_vector(ZVE32X)) { EXT_KEY(ZVE32X); EXT_KEY(ZVE32F); EXT_KEY(ZVE64X); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 6727d1d3b8f2..e8a47fa72351 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -53,7 +53,7 @@ int riscv_v_setup_vsize(void) =20 void __init riscv_v_setup_ctx_cache(void) { - if (!has_vector()) + if (!has_vector(ZVE32X)) return; =20 riscv_v_user_cachep =3D kmem_cache_create_usercopy("riscv_vector_ctx", @@ -173,8 +173,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 __user *epc =3D (u32 __user *)regs->epc; u32 insn =3D (u32)regs->badaddr; =20 + if (!has_vector(ZVE32X)) + return false; + /* Do not handle if V is not supported, or disabled */ - if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V)) + if (!riscv_v_vstate_ctrl_user_allowed()) return false; =20 /* If V has been enabled then it is not the first-use trap */ @@ -213,7 +216,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!has_vector(ZVE32X)) return; =20 next =3D riscv_v_ctrl_get_next(tsk); @@ -235,7 +238,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) =20 long riscv_v_vstate_ctrl_get_current(void) { - if (!has_vector()) + if (!has_vector(ZVE32X)) return -EINVAL; =20 return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; @@ -246,7 +249,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!has_vector(ZVE32X)) return -EINVAL; =20 if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) @@ -296,7 +299,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = =3D { =20 static int __init riscv_v_sysctl_init(void) { - if (has_vector()) + if (has_vector(ZVE32X)) if (!register_sysctl("abi", riscv_v_default_vstate_table)) return -EINVAL; return 0; diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index bc22c078aba8..bbe143bb32a0 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -14,7 +14,7 @@ =20 SYM_FUNC_START(__asm_copy_to_user) #ifdef CONFIG_RISCV_ISA_V - ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONF= IG_RISCV_ISA_V) + ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X,= CONFIG_RISCV_ISA_V) REG_L t0, riscv_v_usercopy_threshold bltu a2, t0, fallback_scalar_usercopy tail enter_vector_usercopy --=20 2.44.0.rc2