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charset="utf-8" Reorder the attributes and child nodes of the PCIe Controller node to meet the DTS style guidelines. Signed-off-by: Justin Swartz Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- arch/mips/boot/dts/ralink/mt7621.dtsi | 68 +++++++++++++++++---------- 1 file changed, 43 insertions(+), 25 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ral= ink/mt7621.dtsi index f6418201b..aa06d12ac 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -495,70 +495,88 @@ pcie: pcie@1e140000 { <0x1e142000 0x100>, /* pcie port 0 RC control registers */ <0x1e143000 0x100>, /* pcie port 1 RC control registers */ <0x1e144000 0x100>; /* pcie port 2 RC control registers */ + ranges =3D <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci mem= ory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ + #address-cells =3D <3>; + #interrupt-cells =3D <1>; #size-cells =3D <2>; =20 - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie_pins>; - device_type =3D "pci"; =20 - ranges =3D <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci mem= ory */ - <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0xF800 0 0 0>; - interrupt-map =3D <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + interrupt-map-mask =3D <0xf800 0 0 0>; + interrupt-map =3D <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; =20 - status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins>; =20 reset-gpios =3D <&gpio 19 GPIO_ACTIVE_LOW>; =20 + status =3D "disabled"; + pcie@0,0 { reg =3D <0x0000 0 0 0 0>; + ranges; + #address-cells =3D <3>; + #interrupt-cells =3D <1>; #size-cells =3D <2>; + + clocks =3D <&sysc MT7621_CLK_PCIE0>; + device_type =3D "pci"; - #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; interrupt-map =3D <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets =3D <&sysc MT7621_RST_PCIE0>; - clocks =3D <&sysc MT7621_CLK_PCIE0>; - phys =3D <&pcie0_phy 1>; + phy-names =3D "pcie-phy0"; - ranges; + phys =3D <&pcie0_phy 1>; + + resets =3D <&sysc MT7621_RST_PCIE0>; }; =20 pcie@1,0 { reg =3D <0x0800 0 0 0 0>; + ranges; + #address-cells =3D <3>; + #interrupt-cells =3D <1>; #size-cells =3D <2>; + + clocks =3D <&sysc MT7621_CLK_PCIE1>; + device_type =3D "pci"; - #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; interrupt-map =3D <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets =3D <&sysc MT7621_RST_PCIE1>; - clocks =3D <&sysc MT7621_CLK_PCIE1>; - phys =3D <&pcie0_phy 1>; + phy-names =3D "pcie-phy1"; - ranges; + phys =3D <&pcie0_phy 1>; + + resets =3D <&sysc MT7621_RST_PCIE1>; }; =20 pcie@2,0 { reg =3D <0x1000 0 0 0 0>; + ranges; + #address-cells =3D <3>; + #interrupt-cells =3D <1>; #size-cells =3D <2>; + + clocks =3D <&sysc MT7621_CLK_PCIE2>; + device_type =3D "pci"; - #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; interrupt-map =3D <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets =3D <&sysc MT7621_RST_PCIE2>; - clocks =3D <&sysc MT7621_CLK_PCIE2>; - phys =3D <&pcie2_phy 0>; + phy-names =3D "pcie-phy2"; - ranges; + phys =3D <&pcie2_phy 0>; + + resets =3D <&sysc MT7621_RST_PCIE2>; }; }; =20 --