From nobody Mon Feb 9 02:42:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A631379DE; Fri, 15 Mar 2024 02:45:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710470742; cv=none; b=TwocCCXU3tE0ZJHc/WS7cBy1BXJQNDNT3WeFtVdpGDuP0vNg6ogL2xO+IGJpxqPYq/WKmZ4XQGjyqhUejX4Zu2RnwNyC7Qvp121aMX/lXUkO5JOpwlFTg+M6W/WdOtHMCCjDP1UQecqKu+Kcga7UK3mtd44X63Tj12p5NDH3s0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710470742; c=relaxed/simple; bh=E33cKRU/0bnIopCBLTQiUg1CEGllwAlLq2Nw4I1WmE8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=hiLmKSE1CE5Ja0t1fpKDhrevtLdpVbgfnXN6vDgILsyjN07rRdWnoyzjeUxK8z47oe42DANW2ogRecGvOmvAM/JrQPOiEEcj+Kg+zmivdsV6/EThdmCblYMyuJoaorxmHmRpu0WLo+uZBulCFzLsb2JF6LDEgQQBz4KzLUZG1GU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 638C9C433C7; Fri, 15 Mar 2024 02:45:38 +0000 (UTC) From: Huacai Chen To: Arnd Bergmann , Huacai Chen Cc: loongarch@lists.linux.dev, linux-arch@vger.kernel.org, Xuefeng Li , Guo Ren , Xuerui Wang , Jiaxun Yang , linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn, Huacai Chen , stable@vger.kernel.org, Xiaotian Wu , Miao Wang , Xing Li , Hongchen Zhang , Rui Wang Subject: [PATCH] LoongArch: Change __my_cpu_offset definition to avoid mis-optimization Date: Fri, 15 Mar 2024 10:45:26 +0800 Message-ID: <20240315024526.394772-1-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From GCC commit 3f13154553f8546a ("df-scan: remove ad-hoc handling of global regs in asms"), global registers will no longer be forced to add to the def-use chain. Then current_thread_info(), current_stack_pointer and __my_cpu_offset may be lifted out of the loop because they are no longer treated as "volatile variables". This optimization is still correct for the current_thread_info() and current_stack_pointer usages because they are associated to a thread. However it is wrong for __my_cpu_offset because it is associated to a CPU rather than a thread: if the thread migrates to a different CPU in the loop, __my_cpu_offset should be changed. Change __my_cpu_offset definition to treat it as a "volatile variable", in order to avoid such a mis-optimization. Cc: stable@vger.kernel.org Reported-by: Xiaotian Wu Reported-by: Miao Wang Signed-off-by: Xing Li Signed-off-by: Hongchen Zhang Signed-off-by: Rui Wang Signed-off-by: Huacai Chen --- arch/loongarch/include/asm/percpu.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/percpu.h b/arch/loongarch/include/a= sm/percpu.h index 9b36ac003f89..03b98491d301 100644 --- a/arch/loongarch/include/asm/percpu.h +++ b/arch/loongarch/include/asm/percpu.h @@ -29,7 +29,12 @@ static inline void set_my_cpu_offset(unsigned long off) __my_cpu_offset =3D off; csr_write64(off, PERCPU_BASE_KS); } -#define __my_cpu_offset __my_cpu_offset + +#define __my_cpu_offset \ +({ \ + __asm__ __volatile__("":"+r"(__my_cpu_offset)); \ + __my_cpu_offset; \ +}) =20 #define PERCPU_OP(op, asm_op, c_op) \ static __always_inline unsigned long __percpu_##op(void *ptr, \ --=20 2.43.0