From nobody Sun Feb 8 00:49:23 2026 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 979B95C617; Thu, 14 Mar 2024 07:21:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400904; cv=none; b=HZT4ldDMfcynJRrWkchJ3m+ROt3f801T15/pqeRfiIvxgfqOTfJACd5np6O5BaxZoLkAxIgDh53M2dlSjLrfODx9WEM8QWDm9WzhaO/9tEKhOrkkTHqbgYXWSwPdNhZkjjregtIbiTicutxqPfu0Rojt6lf01AvvZ2kUD9QvWmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400904; c=relaxed/simple; bh=iU0P/pPN0hf8+78Gl8OOHKQuX55sbJAVM462l+Xpo/Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RKQC8CVEoEFuRUc5YrrTjOzo2A2aS/PGvrXpyntgyZ6kbnks3FKxrUcq1bx2vr+Q/bATD4WYxca61p425MI4Agzm32c2obkI/B7BIkKPXJdn6EvfV6NhD0e6t3o8Vd5lX69OQVP70FQE7XN52enMQITYhG1OpYmgXDmlQ4Bxi8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bRyq7DCD; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bRyq7DCD" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LYf0024881; Thu, 14 Mar 2024 02:21:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1710400894; bh=N/r4yeeJCniqbNU4n+Oorp8eaNGK16nfzVidvodlDqk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bRyq7DCDn0g9KARh85f4Q2tuRmfoJC+59UP5Pnm641jgkvef3ZYCS64G+RHmN6NNU kY7QzbpgkbTlfp6K2/9z7DIO7Am4uBCGhVPZ8CemRaBKlteVLjTrxGpWjEgwXBic3P SkxQmEeFTph2L21iYCNIhY/Rla7IIuV9n9dRimjE= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42E7LY3h021688 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 Mar 2024 02:21:34 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 14 Mar 2024 02:21:33 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 14 Mar 2024 02:21:33 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LWc3120529; Thu, 14 Mar 2024 02:21:33 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v5 1/5] arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G Date: Thu, 14 Mar 2024 12:51:25 +0530 Message-ID: <20240314072129.1520475-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314072129.1520475-1-c-vankar@ti.com> References: <20240314072129.1520475-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 81fd7afac8c5..1f390c22844e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -27,6 +27,7 @@ aliases { mmc1 =3D &main_sdhci1; i2c0 =3D &wkup_i2c0; i2c3 =3D &main_i2c0; + ethernet0 =3D &mcu_cpsw_port1; }; =20 memory@80000000 { --=20 2.34.1 From nobody Sun Feb 8 00:49:23 2026 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE4645C616; Thu, 14 Mar 2024 07:21:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400913; cv=none; b=bmaAuaodUBi6cgy3Q5sxfnwIMW4pAwdqR1/rJSNgA8RdUeWOxh6AL0YIfT+08r3JckGWwYMx77Ph6g9MMwboWvxHbiAaYfgE0PMjscf8TIgxcTO31T4x1dx+GRJzGCOeCVKumQg2ORF0PO/lJ56hSVASQBznupOTLd0nQxyqvic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400913; c=relaxed/simple; bh=L+yCD2qgN5jMbl5z1ERQ0EKgIJiAhEdSwIF16JdbZc4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TDFRQquA1/o2JMHygji39mWWgrc6eiumzxOzDiZI8L4iLsCJ8kUFF4Ezjb1+6epu3vB0udQUyv/RcvTydbAqOtyePGS9sbYzzKb9D8msPT3MFJ19V0eVQWqs4TftLTnvJZi2LiH9PZCF5ielxPiF7nLDN8TOMuxmQa3WDo+gtlc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=RNrDM4BZ; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RNrDM4BZ" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LZKY021111; Thu, 14 Mar 2024 02:21:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1710400895; bh=g/WsjfnXeyDveufVEIKJWhGaYtBXjGff5M+bbdAy2kg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RNrDM4BZMbLre4kQP96cH21e03wfe4LzkczDv2Vz/+XAFM8mDZebDvfmfP6WaNgEQ RjgUCXNJbwby5X3KtZ8rpCOF3U1tF2UjvM7D6mIJvoW3gr5Rb9zzpMCxLLKF07kPee rR2hWEsvA6cl+JyFgq6d5itA3y8mVmv/Znsbs2q8= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42E7LZ0u021698 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 Mar 2024 02:21:35 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 14 Mar 2024 02:21:35 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 14 Mar 2024 02:21:35 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LYin101242; Thu, 14 Mar 2024 02:21:34 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v5 2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes Date: Thu, 14 Mar 2024 12:51:26 +0530 Message-ID: <20240314072129.1520475-3-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314072129.1520475-1-c-vankar@ti.com> References: <20240314072129.1520475-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has MAIN CPSW2G and CPSW9G instances of the CPSW Ethernet Switch. CPSW2G has 1 external port and 1 host port while CPSW9G has 8 external ports and 1 host port. Add device-tree nodes for MAIN CPSW2G and CPSW9G and disable them by default. MAIN CPSW2G will be enabled in the board file while device-tree overlays will be used to enable CPSW9G. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 187 +++++++++++++++++++++ 1 file changed, 187 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index b67c37460a73..ddf28b2143aa 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -48,6 +48,19 @@ scm_conf: bus@100000 { #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x1c000>; =20 + cpsw1_phy_gmii_sel: phy@4034 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x4034 0x4>; + #phy-cells =3D <1>; + }; + + cpsw0_phy_gmii_sel: phy@4044 { + compatible =3D "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports =3D <7>, <7>; + reg =3D <0x4044 0x20>; + #phy-cells =3D <1>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x00004080 0x30>; @@ -1439,6 +1452,180 @@ cpts@310d0000 { }; }; =20 + main_cpsw0: ethernet@c000000 { + compatible =3D "ti,j784s4-cpswxg-nuss"; + reg =3D <0x00 0xc000000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw0_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg =3D <2>; + label =3D "port2"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg =3D <3>; + label =3D "port3"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg =3D <4>; + label =3D "port4"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg =3D <5>; + label =3D "port5"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg =3D <6>; + label =3D "port6"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg =3D <7>; + label =3D "port7"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg =3D <8>; + label =3D "port8"; + ti,mac-only; + status =3D "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 64 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + + main_cpsw1: ethernet@c200000 { + compatible =3D "ti,j721e-cpsw-nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0x00 0xc200000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw1_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + phys =3D <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status =3D "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio", "ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 62 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.34.1 From nobody Sun Feb 8 00:49:23 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8F585DF38; Thu, 14 Mar 2024 07:21:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400917; cv=none; b=eejY6ewXeYnpHmwg05Yz6NZEzKHeJJzJa1vRWiN/f9HS5QlAh3HVru5P49lejgEDD8j7BnlgZ8XKqP4e49pJ+NJo4eLK8NsoFat2JURHcw40QvnM0gkB9aYf3OkweTIlxW0vFXcOOZXsn103OAugeCCKl6Nvs4JVFywWO64yYD0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400917; c=relaxed/simple; bh=wDO2v52/Jhz1dO6jngGrH6v2PVhcnQt2WwAc/kUzz+M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PZpKhpcko0h+zNkXtIQTJgv6hh+xqo4fi1XxBjsY7IywQJeyyf5nb3k3td8i2CdeTzFOVMDo2qC5m8kP60laOMWYA/ib21oVBiMqE3SaoC2D8XrJpIrIK8nm8k1XW2IhhNP+M+EmdxO4qfgA9Egy3UsEHUsvNcefHLiz0JyQyWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=jrnRdME7; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jrnRdME7" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LbfS065159; Thu, 14 Mar 2024 02:21:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1710400897; bh=EqYT8bErUGPP3hgcFP27YRB7SfjO5pnIYidrWDI/DeU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jrnRdME7CpfYfn1VDigIl2LLqi/lXOSMz6Qi75DxIl8xhZmMCdpBNt/twLS+nKJv8 Zk96FOOfFaT7PlNP3CRH9WrUHcQ4kveHcVhA16MaiziHfcmTkHc89b9FaeNIE+jiEl 4U/m1fAxGW7Wmf+6uCVMZvF/HmCiEo7of3rxmZ48= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42E7Lbmc086709 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 Mar 2024 02:21:37 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 14 Mar 2024 02:21:36 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 14 Mar 2024 02:21:36 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LZDl101268; Thu, 14 Mar 2024 02:21:36 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Jayesh Choudhary , Chintan Vankar Subject: [PATCH v5 3/5] arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it Date: Thu, 14 Mar 2024 12:51:27 +0530 Message-ID: <20240314072129.1520475-4-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314072129.1520475-1-c-vankar@ti.com> References: <20240314072129.1520475-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli Enable MAIN CPSW2G and add alias for it to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 1f390c22844e..49195349a156 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -28,6 +28,7 @@ aliases { i2c0 =3D &wkup_i2c0; i2c3 =3D &main_i2c0; ethernet0 =3D &mcu_cpsw_port1; + ethernet1 =3D &main_cpsw1_port1; }; =20 memory@80000000 { @@ -281,6 +282,30 @@ &wkup_gpio0 { =20 &main_pmx0 { bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL = */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL = */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + main_uart8_pins_default: main-uart8-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -833,6 +858,31 @@ &mcu_cpsw_port1 { phy-handle =3D <&mcu_phy0>; }; =20 +&main_cpsw1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_default_pins>; +}; + +&main_cpsw1_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_mdio_default_pins>; + + main_cpsw1_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status =3D "okay"; + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&main_cpsw1_phy0>; +}; + &mailbox0_cluster0 { status =3D "okay"; interrupts =3D <436>; --=20 2.34.1 From nobody Sun Feb 8 00:49:23 2026 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE1B55D478; Thu, 14 Mar 2024 07:21:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400914; cv=none; b=LAw9iCSL0lgNbUttvXYq1v14vrvCFVF0DgC2L2yp++E/uWNKAHznRSPsh79uHkpSuBkqvD8DGfZ2AJuiE15csiTV4laYfBrOUEymP5mKTnTYIg4U5BSNG+6IGgtLkl4kzwQZkSNk49kS8ejPrmQOZe744HIQt7zeUGpqKmjfg4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400914; c=relaxed/simple; bh=P+/NIZKhm/9pDc2iN0YzaSzbWc0AzHBIalfiRtKuqJM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gcOwpp1UHnIQ+8o71lN93r8y2NrcF91dZcOgNps2vD+vOzn5LXF1GZgWjwhFPF7/k89Ue+5sHJtv0huIxV6TQcpst7iHf+tDBtSkJXQ4IYRCiJ21vxuqKVw9b9g1qKtraG8QTdThk0OtsUrbcmSSe9mf+9yOBoy8+3PTivurW0o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Z3QBsM75; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Z3QBsM75" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LcOr065437; Thu, 14 Mar 2024 02:21:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1710400898; bh=Dl7DfpR+zhfFY4c+ehXXtopvfIl11RBHoKLNXTe5U2k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Z3QBsM75Wt2g+gTfQ/zuBndQ0c2srpljJH8E4XMN0J5oL4j87NGYroOL4pdxTVuDX 1MvTFGWK56vtjcFJcqOkIsDXMsD+ISY3xSc+R1BPfPp7RvpLUmNZJcX28BzDcg6QB/ u7hcOVtg/6UGdrmSUAuwsaNwFcgayOaWgfw5br98= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42E7LcRH015731 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 Mar 2024 02:21:38 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 14 Mar 2024 02:21:38 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 14 Mar 2024 02:21:38 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LbeL101284; Thu, 14 Mar 2024 02:21:37 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v5 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G Date: Thu, 14 Mar 2024 12:51:28 +0530 Message-ID: <20240314072129.1520475-5-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314072129.1520475-1-c-vankar@ti.com> References: <20240314072129.1520475-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode with the Add-On Ethernet Card connected to the ENET Expansion 1 slot on the EVM. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/Makefile | 7 +- .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 147 ++++++++++++++++++ 2 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 9a722c2473fb..f8e47278df43 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ @@ -145,6 +146,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs :=3D k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -165,7 +168,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am69-sk-csi2-dual-imx219-dtbs \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219-dtbs \ - k3-j721s2-evm-pcie1-ep.dtb + k3-j721s2-evm-pcie1-ep.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ @@ -181,3 +185,4 @@ DTC_FLAGS_k3-am69-sk +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ +DTC_FLAGS_k3-j784s4-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b= /arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso new file mode 100644 index 000000000000..0667389b07be --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On = Ethernet Card with + * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expans= ion 1 slot on the + * board. + * + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf + * + * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-pinctrl.h" +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; + ethernet2 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; + ethernet3 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; + ethernet4 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; + ethernet5 =3D "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_cpsw0 { + status =3D "okay"; +}; + +&main_cpsw0_port5 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy1>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port6 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy2>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port7 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy0>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port8 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy3>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_default_pins>; + bus_freq =3D <1000000>; + reset-gpios =3D <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us =3D <120000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpsw9g_phy0: ethernet-phy@16 { + reg =3D <16>; + }; + cpsw9g_phy1: ethernet-phy@17 { + reg =3D <17>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg =3D <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg =3D <19>; + }; +}; + +&exp2 { + /* Power-up ENET1 EXPANDER PHY. */ + qsgmii-line-hog { + gpio-hog; + gpios =3D <16 GPIO_ACTIVE_HIGH>; + output-low; + }; + + /* Toggle MUX2 for MDIO lines */ + mux-sel-hog { + gpio-hog; + gpios =3D <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_= HIGH>; + output-high; + }; +}; + +&main_pmx0 { + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ + J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz2 { + status =3D "okay"; +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + serdes2_qsgmii_link: phy@0 { + reg =3D <2>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>; + }; +}; --=20 2.34.1 From nobody Sun Feb 8 00:49:23 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CADB55E224; Thu, 14 Mar 2024 07:21:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400919; cv=none; b=nbqoZAopfT2dOxwHZ4SK8/uq2HoOg4bHerBzEHcAB3P7qWFoKCPeqi5RVyC1lvXMR7AZKMp2c4fi0vAuHqkhdGLl7+sy2UGNBKod85EKYprFSzxjh098hvdeOXLLY+PIdsgKAOjDOh8LiiOrhyh2ZopZydBfXKqkCoCR2QX+/Io= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710400919; c=relaxed/simple; bh=UcBcGukgguSoA+8PNtQc1UjtJFCatvGk6EJx682SMsM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sFID3fUSMTUW6YGpmqm+ae/oIismUDefuZvzJT8UYB2mp//lK7ZC5ahzC+98IFiuv3Hx1x8RI2j1IZgXAYtpjY+pQ4E0n8FEenvtTsEA83MFaPsuFBBL8XUAUdYeQWqybc35Mtir1r824T6Tx9C/Zdg9ojHO/Psi3dog7VrEuCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=OXpS/5Ko; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="OXpS/5Ko" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LeOq065182; Thu, 14 Mar 2024 02:21:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1710400900; bh=EKTarbR5ODKlrx6YKTvE9DTK3VZbyWvX/vtA06anwgE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OXpS/5KoZJcavatc86sT7k7ykAC1bE410nXv4hu0QFxAn5zxSt3nu/Z7CjVkZDP0g Bdhsf9v9nLcQCzmMs9s5bJlC6/A6ZrCwdverVo591YqalFkrNCk33aFMYXGea/ROGP m27TDZxBaXpQ9MsC8Y06RJpyUOALaZlPyMiAAgo0= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42E7LeUg031098 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 14 Mar 2024 02:21:40 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 14 Mar 2024 02:21:39 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 14 Mar 2024 02:21:39 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42E7LcVN120617; Thu, 14 Mar 2024 02:21:39 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v5 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Date: Thu, 14 Mar 2024 12:51:29 +0530 Message-ID: <20240314072129.1520475-6-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240314072129.1520475-1-c-vankar@ti.com> References: <20240314072129.1520475-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode with MAC Ports 1 and 2 of the instance, which are connected to ENET Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through the Serdes2 instance of the SERDES. Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode at 5 Gbps each. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/Makefile | 6 +- .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 +++++++++++++++++++ 2 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.= dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index f8e47278df43..2d798ef415e4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ @@ -148,6 +149,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo +k3-j784s4-evm-usxgmii-exp1-exp2.dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -169,7 +172,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219-dtbs \ k3-j721s2-evm-pcie1-ep.dtb \ - k3-j784s4-evm-quad-port-eth-exp1.dtb + k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/= arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso new file mode 100644 index 000000000000..b8e7fed6105a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 =3D "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_cpsw0 { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&main_cpsw0_port1 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + status =3D "okay"; + assigned-clock-parents =3D <&k3_clks 406 9>; /* Use 156.25 MHz clock for = USXGMII */ +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + serdes2_usxgmii_link: phy@2 { + reg =3D <2>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; --=20 2.34.1