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Use the counter mask (cmask) to show the number of cycles taken to retire the instructions. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 86 +++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 9ef30e5d3e25..4ac419212b3d 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -2,7 +2,7 @@ # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMe= tric, JsonEncodeMetricGroupDescriptions, Literal, LoadEvents, - Metric, MetricGroup, MetricRef, Select) + Metric, MetricConstraint, MetricGroup, MetricRef, Sele= ct) import argparse import json import math @@ -508,6 +508,89 @@ def IntelSwpf() -> Optional[MetricGroup]: ], description=3D"Sofware prefetch instruction breakdown") =20 =20 +def IntelLdSt() -> Optional[MetricGroup]: + if _args.model in [ + "bonnell", + "nehalemep", + "nehalemex", + "westmereep-dp", + "westmereep-sp", + "westmereex", + ]: + return None + LDST_LD =3D Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LO= ADS") + LDST_ST =3D Event("MEM_INST_RETIRED.ALL_STORES", "MEM_UOPS_RETIRED.ALL_S= TORES") + LDST_LDC1 =3D Event(f"{LDST_LD.name}/cmask=3D1/") + LDST_STC1 =3D Event(f"{LDST_ST.name}/cmask=3D1/") + LDST_LDC2 =3D Event(f"{LDST_LD.name}/cmask=3D2/") + LDST_STC2 =3D Event(f"{LDST_ST.name}/cmask=3D2/") + LDST_LDC3 =3D Event(f"{LDST_LD.name}/cmask=3D3/") + LDST_STC3 =3D Event(f"{LDST_ST.name}/cmask=3D3/") + ins =3D Event("instructions") + LDST_CYC =3D Event("CPU_CLK_UNHALTED.THREAD", + "CPU_CLK_UNHALTED.CORE_P", + "CPU_CLK_UNHALTED.THREAD_P") + LDST_PRE =3D None + try: + LDST_PRE =3D Event("LOAD_HIT_PREFETCH.SWPF", "LOAD_HIT_PRE.SW_PF") + except: + pass + LDST_AT =3D None + try: + LDST_AT =3D Event("MEM_INST_RETIRED.LOCK_LOADS") + except: + pass + cyc =3D LDST_CYC + + ld_rate =3D d_ratio(LDST_LD, interval_sec) + st_rate =3D d_ratio(LDST_ST, interval_sec) + pf_rate =3D d_ratio(LDST_PRE, interval_sec) if LDST_PRE else None + at_rate =3D d_ratio(LDST_AT, interval_sec) if LDST_AT else None + + ldst_ret_constraint =3D MetricConstraint.GROUPED_EVENTS + if LDST_LD.name =3D=3D "MEM_UOPS_RETIRED.ALL_LOADS": + ldst_ret_constraint =3D MetricConstraint.NO_GROUP_EVENTS_NMI + + return MetricGroup("ldst", [ + MetricGroup("ldst_total", [ + Metric("ldst_total_loads", "Load/store instructions total loads", + ld_rate, "loads"), + Metric("ldst_total_stores", "Load/store instructions total store= s", + st_rate, "stores"), + ]), + MetricGroup("ldst_prcnt", [ + Metric("ldst_prcnt_loads", "Percent of all instructions that are= loads", + d_ratio(LDST_LD, ins), "100%"), + Metric("ldst_prcnt_stores", "Percent of all instructions that ar= e stores", + d_ratio(LDST_ST, ins), "100%"), + ]), + MetricGroup("ldst_ret_lds", [ + Metric("ldst_ret_lds_1", "Retired loads in 1 cycle", + d_ratio(max(LDST_LDC1 - LDST_LDC2, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_lds_2", "Retired loads in 2 cycles", + d_ratio(max(LDST_LDC2 - LDST_LDC3, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_lds_3", "Retired loads in 3 or more cycles", + d_ratio(LDST_LDC3, cyc), "100%"), + ]), + MetricGroup("ldst_ret_sts", [ + Metric("ldst_ret_sts_1", "Retired stores in 1 cycle", + d_ratio(max(LDST_STC1 - LDST_STC2, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_sts_2", "Retired stores in 2 cycles", + d_ratio(max(LDST_STC2 - LDST_STC3, 0), cyc), "100%", + constraint =3D ldst_ret_constraint), + Metric("ldst_ret_sts_3", "Retired stores in 3 more cycles", + d_ratio(LDST_STC3, cyc), "100%"), + ]), + Metric("ldst_ld_hit_swpf", "Load hit software prefetches per second", + pf_rate, "swpf/s") if pf_rate else None, + Metric("ldst_atomic_lds", "Atomic loads per second", + at_rate, "loads/s") if at_rate else None, + ], description =3D "Breakdown of load/store instructions") + + def main() -> None: global _args =20 @@ -537,6 +620,7 @@ def main() -> None: Tsx(), IntelBr(), IntelL2(), + IntelLdSt(), IntelPorts(), IntelSwpf(), ]) --=20 2.44.0.278.ge034bb2e1d-goog