From nobody Mon Feb 9 09:29:18 2026 Received: from mail-oo1-f53.google.com (mail-oo1-f53.google.com [209.85.161.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BA7C142634 for ; Tue, 12 Mar 2024 19:47:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272877; cv=none; b=Vbl+D0hnT4q2YJvp8iZmvBuk0LsD4yYB3mcspTSyejnUiTxc7VP+YCT7h72krUXBnYHRzYaQDLyxtav1CIllzgCnFLKeyij9Y3lnvI6lup/Crfn21awsQrv39nbj5SDPzbRzjsZkItNhxBNMKKuap2XFaIdo7IHysn/yryYHFvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272877; c=relaxed/simple; bh=U1yCIqRq0duvpJX2nz5FFSagYRqS2vPnAY5Af8ygvZo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qILXuyRVbuCPBS4+cNSzKwW1DbjmsHvblECXPw7zhjQx4D9vpFaKr6TQLfoFUSZBoDLLe1t5UXRGL779yGxX3RtwOifg2zF4tlvc2tl0KswLtnVYofX5eAKBS1wPOmRswc3N9EpbaUK83kiopPO8wKfqIbGeQAheFNFLT95ePSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=XBlu3+39; arc=none smtp.client-ip=209.85.161.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="XBlu3+39" Received: by mail-oo1-f53.google.com with SMTP id 006d021491bc7-5a19de33898so221161eaf.0 for ; Tue, 12 Mar 2024 12:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1710272874; x=1710877674; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JOqRUTnz4dMY1mDsAaQqT8RlSz6vNVMJhwSPPEU0/Tk=; b=XBlu3+39DS35WQKvpj1l1k9QknOGZUQRwfMYYFXgJjjnGdIw4UioCcFjGfq3RtOHfw SMOd1B165Xxq10WCu/lLNqp0o1jv8eqcOcTuLx3Ze/u5b6epq1OrjR3Ax4h+JkDWM8Ub mA329ajlsEElbTBwabifjORjGbMA/5ypYwgLRBxmWQr8T4AUM6FPDZuyLT7xtNzojfbD duJtDz/hxl9RfVONEw1+Vv3Tlw01yf+fUOswsSgw+TCVQwaSUbaLpNqBDE75wr5SGF5y GNVy4drxIgFOEDF4ZzzXN38PGJKjnhw9npIjvxJKtmpv9AHIerw23wKJP51J+DteflAJ TrXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710272874; x=1710877674; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JOqRUTnz4dMY1mDsAaQqT8RlSz6vNVMJhwSPPEU0/Tk=; b=KmPMUVE4hg2OcHaF/3XLETwqobnePKfnlLR4BBaVKEsrm+fzfXq93IrtqEmAuxJgBP nwIHewub837vZ2XNsHkQKzagtlWIiZvWekrxxqAfbUo9g7udjb33IbGjlS0ylAlRLBpg toYM7LIpEaur9VHGeTApqyh8VUj2ZZMaLwFoKX4rDpbm3OYrLb0ETClc3agqOZMcY1W1 Af79oW/qa+ikQKhQ4EoBzEHXMJBDKYbz2jhWrywspyrlXW6ZS/Iz/L94FilaKqv2ZBo8 h2YjL4CEZEnus66IA30rzHpoEpWWW9r+zNFq1wxy1sGYHccgoUaGFA/I7Zrw/rwPdQr2 7aww== X-Forwarded-Encrypted: i=1; AJvYcCXLDTurNX2Us7dQCzGcX3wkbqbnXZOWHqSa0PeAs34JraRRb+hMDHOpHxMpJRystffWMUZVGYz6fVMwqLnR0AwxJpNsD04nft7HwCgG X-Gm-Message-State: AOJu0YwqEHn8OgPCt66ZcpkfAZv/RQzaQYJ/pA/fIn255fTtUimZVRWp /n7WwmEB2TdF1qyu9AL2r57Zyni8jpr0xVltt8CS48nt74NwlLI1ytwCcInOCXg= X-Google-Smtp-Source: AGHT+IGI3bdfpp+X8J+ZAKrqf6mS+YBT6i2j3SsCGQcUF6D9lLzGReHwzZfu7T6A9BAy8M6S+dJeAg== X-Received: by 2002:a05:6358:3228:b0:17e:6924:e4ef with SMTP id a40-20020a056358322800b0017e6924e4efmr4693399rwe.24.1710272874205; Tue, 12 Mar 2024 12:47:54 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id z69-20020a633348000000b005dc884e9f5bsm6433495pgz.38.2024.03.12.12.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 12:47:53 -0700 (PDT) From: Charlie Jenkins Date: Tue, 12 Mar 2024 12:47:51 -0700 Subject: [PATCH v12 1/4] riscv: Remove unnecessary irqflags processor.h include Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240312-fencei-v12-1-0f340f004ce7@rivosinc.com> References: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> In-Reply-To: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1710272871; l=696; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=U1yCIqRq0duvpJX2nz5FFSagYRqS2vPnAY5Af8ygvZo=; b=B4BSJn3Ds/uhAQxDonyv5DKERy7Fsrbt2TvkM0fPKhogZvT+pJ7QmCDUxVLS6ckX7qedOXG0u KalC8LH+1ZCD46M/5bI5dIEnZ3XJ5XlRQEEBBBsLpauEY6z5ACcZhlV X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= This include is not used. Remove it to avoid a circular dependency in the next patch in the series. Signed-off-by: Charlie Jenkins Reviewed-by: Samuel Holland --- arch/riscv/include/asm/irqflags.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irq= flags.h index 08d4d6a5b7e9..6fd8cbfcfcc7 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -7,7 +7,6 @@ #ifndef _ASM_RISCV_IRQFLAGS_H #define _ASM_RISCV_IRQFLAGS_H =20 -#include #include =20 /* read interrupt enabled status */ --=20 2.43.2 From nobody Mon Feb 9 09:29:18 2026 Received: from mail-ot1-f41.google.com (mail-ot1-f41.google.com [209.85.210.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 056AB1E53F for ; Tue, 12 Mar 2024 19:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272878; cv=none; b=MuxrWhHM8y5QEVhT7f8DIaXaCr9fKBByYQXgdebkgF6VizC02MSLZE8sUaw2lBQQmbodq/7GBm+3KEvWb7DoNyqIR9WLdUK4JS1lxsB4ACg8cFqwdyCHpTUya+AGWiQtAwNTw1SxZgye81jO+K5PffbO9l2CchtiPnGLWeD43hM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272878; c=relaxed/simple; bh=y0iHy2miMpDFLFnKlKYIXzwWxBVtlvqnR0lBsS/F5pE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j2qgzhVYQ+LZGJzm0yXoJ8hNrXmFwDpYZLSEYbtXmNaZIy1oCRfUZcASATGVCn1LOy2yTUk22nJldAMXo/nlRkHNjEVzUOY9U3jaBjxjFbFZwX9trZYi29mcz1At2sx4Bjnx1Woa0gU8Gh0fusJJpB0L817J/5uUdS8JmzsljK0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=GGhiV0cH; arc=none smtp.client-ip=209.85.210.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="GGhiV0cH" Received: by mail-ot1-f41.google.com with SMTP id 46e09a7af769-6e4f7975121so1432824a34.1 for ; Tue, 12 Mar 2024 12:47:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1710272876; x=1710877676; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TbLEjYOuTew9WKxjWnEBs/gb9DjkFzs8yvYm9yYSkps=; b=GGhiV0cHDUFYEkEoxTWzs0BQgfnedOfOG/0hFpuUpE2NFSkhkm6I28JdwU+MD6Y7BQ ebls3pdk6glvOCxvxryPmPl04oSHYBNbz/8oYtSc+qPlxzBs9N9PkxEIn+TZKJ0W2mJQ 40+wMkzQRGVmtK/mJbsFbMXDUxVCEls8/lla29hoOQ8/iDxxD9mFclk/03kGavM10IeB PWGHP9N8N1Y6mXgCMJICdJykgkhJGJ97XNO9a99MCBj91UrUx54WYDKwFQ3JyPnnHfuy Cxki3adCDdpjaew3aXJpZSJJzATWoCua99EigFATeD64vOl3l/54mt/2A1+Yx/x4XIkq cIrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710272876; x=1710877676; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TbLEjYOuTew9WKxjWnEBs/gb9DjkFzs8yvYm9yYSkps=; b=rq5WrUI5d9KAAGCixBffvzEr33M92Kc3gPBQ+2W/CSvlybG7vSmQmGNY9wN6057Ub+ ZOOfQAmq8zwGVBXgIW0pEUYG2Nn7kbJKr8vh1b+HMt26LASQEW0RloQLEJ2+nSW6RR7+ CwzwJJnPCoittAQysiRX8O+hxdg8bAjUhMnc+e5NTUYVW+IuUJYG+oOu+/CaehpZ1Fir 43A+9PZYtwfZOs9ChdX0MQv2pYnuWneP8UhXFaGMmzPJipfXnjx8GjljGkILAwyelLD0 BlExaqHITH86fEZZqoLItSQsJpBnhkmaGzN20oneZi1t1XJIuv766aX2sZEtPO3+UXOP VFPQ== X-Forwarded-Encrypted: i=1; AJvYcCU7+Nx6ryz8O/OsNXL4HOc9CKgxCggpYubuzJum5BAwLpdAsFO9XmKhYY1RzbQqcZoAcAnMwIhUCYjLUHbclUMTvFC6iOwhzzRpB/bW X-Gm-Message-State: AOJu0YyzUfssL4em5eVlYE0aQ9Z/wHctWymHzmZiUNUzzk8HWPLqR7qq sfN3MzzHJfuvMenpsU2rPNt2yR84kYvhORltOiDZ9AazK9nHoY8jTa2x2T0NzM0= X-Google-Smtp-Source: AGHT+IF2aSSUeVtzGh+bJy4A6t0EvJqrjDOCZp8dq0KsrKHUL+cxiRjvySCn+x/5hiWy8j7i/KkLsg== X-Received: by 2002:a05:6870:169b:b0:21f:d9e0:c0a8 with SMTP id j27-20020a056870169b00b0021fd9e0c0a8mr1231003oae.41.1710272876049; Tue, 12 Mar 2024 12:47:56 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id z69-20020a633348000000b005dc884e9f5bsm6433495pgz.38.2024.03.12.12.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 12:47:54 -0700 (PDT) From: Charlie Jenkins Date: Tue, 12 Mar 2024 12:47:52 -0700 Subject: [PATCH v12 2/4] riscv: Include riscv_set_icache_flush_ctx prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240312-fencei-v12-2-0f340f004ce7@rivosinc.com> References: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> In-Reply-To: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1710272871; l=11022; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=y0iHy2miMpDFLFnKlKYIXzwWxBVtlvqnR0lBsS/F5pE=; b=dOzo758qkRTMcWfdtocUy7mLqCFzVaOc6TCvL0Y8xxJTeLVntgkV4VpkKSM2ZMlyIfVOfE8Zg hx29a8V8wgyAm+L9DW1N5Nvpu112IWgA6NxbhwlOfTlaRGhgP+Wk4sO X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable optimization of cross modifying code. This prctl enables userspace code to use icache flushing instructions such as fence.i with the guarantee that the icache will continue to be clean after thread migration. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 10 ++++ arch/riscv/include/asm/switch_to.h | 23 ++++++++++ arch/riscv/mm/cacheflush.c | 94 ++++++++++++++++++++++++++++++++++= ++++ arch/riscv/mm/context.c | 17 +++++-- include/uapi/linux/prctl.h | 6 +++ kernel/sys.c | 6 +++ 7 files changed, 153 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..60be458e94da 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -19,6 +19,8 @@ typedef struct { #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; + /* Force local icache flush on all migrations. */ + bool force_icache_flush; #endif #ifdef CONFIG_BINFMT_ELF_FDPIC unsigned long exec_fdpic_loadmap; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index a8509cc31ab2..cca62013c3c0 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -69,6 +69,7 @@ #endif =20 #ifndef __ASSEMBLY__ +#include =20 struct task_struct; struct pt_regs; @@ -123,6 +124,12 @@ struct thread_struct { struct __riscv_v_ext_state vstate; unsigned long align_ctl; struct __riscv_v_ext_state kernel_vstate; +#ifdef CONFIG_SMP + /* Flush the icache on migration */ + bool force_icache_flush; + /* A forced icache flush is not needed if migrating to the previous cpu. = */ + unsigned int prev_cpu; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -184,6 +191,9 @@ extern int set_unalign_ctl(struct task_struct *tsk, uns= igned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) =20 +#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(= arg1, arg2) +extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per= _thread); + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7efdb0584d47..7594df37cc9f 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -72,14 +73,36 @@ static __always_inline bool has_fpu(void) { return fals= e; } extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); =20 +static inline bool switch_to_should_flush_icache(struct task_struct *task) +{ +#ifdef CONFIG_SMP + bool stale_mm =3D task->mm && task->mm->context.force_icache_flush; + bool stale_thread =3D task->thread.force_icache_flush; + bool thread_migrated =3D smp_processor_id() !=3D task->thread.prev_cpu; + + return thread_migrated && (stale_mm || stale_thread); +#else + return false; +#endif +} + +#ifdef CONFIG_SMP +#define __set_prev_cpu(thread) ((thread).prev_cpu =3D smp_processor_id()) +#else +#define __set_prev_cpu(thread) +#endif + #define switch_to(prev, next, last) \ do { \ struct task_struct *__prev =3D (prev); \ struct task_struct *__next =3D (next); \ + __set_prev_cpu(__prev->thread); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ if (has_vector()) \ __switch_to_vector(__prev, __next); \ + if (switch_to_should_flush_icache(__next)) \ + local_flush_icache_all(); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 55a34f2020a8..329b95529580 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include =20 @@ -152,3 +153,96 @@ void __init riscv_init_cbo_blocksizes(void) if (cboz_block_size) riscv_cboz_block_size =3D cboz_block_size; } + +/** + * riscv_set_icache_flush_ctx() - Enable/disable icache flushing instructi= ons in + * userspace. + * @ctx: Set the type of icache flushing instructions permitted/prohibited= in + * userspace. Supported values described below. + * + * Supported values for ctx: + * + * * %PR_RISCV_CTX_SW_FENCEI_ON: Allow fence.i in user space. + * + * * %PR_RISCV_CTX_SW_FENCEI_OFF: Disallow fence.i in user space. All thre= ads in + * a process will be affected when ``scope =3D=3D PR_RISCV_SCOPE_PER_PRO= CESS``. + * Therefore, caution must be taken; use this flag only when you can gua= rantee + * that no thread in the process will emit fence.i from this point onwar= d. + * + * @scope: Set scope of where icache flushing instructions are allowed to = be + * emitted. Supported values described below. + * + * Supported values for scope: + * + * * %PR_RISCV_SCOPE_PER_PROCESS: Ensure the icache of any thread in this = process + * is coherent with instruction storage upon + * migration. + * + * * %PR_RISCV_SCOPE_PER_THREAD: Ensure the icache of the current thread is + * coherent with instruction storage upon + * migration. + * + * When ``scope =3D=3D PR_RISCV_SCOPE_PER_PROCESS``, all threads in the pr= ocess are + * permitted to emit icache flushing instructions. Whenever any thread in = the + * process is migrated, the corresponding hart's icache will be guaranteed= to be + * consistent with instruction storage. This does not enforce any guarante= es + * outside of migration. If a thread modifies an instruction that another = thread + * may attempt to execute, the other thread must still emit an icache flus= hing + * instruction before attempting to execute the potentially modified + * instruction. This must be performed by the user-space program. + * + * In per-thread context (eg. ``scope =3D=3D PR_RISCV_SCOPE_PER_THREAD``) = only the + * thread calling this function is permitted to emit icache flushing + * instructions. When the thread is migrated, the corresponding hart's ica= che + * will be guaranteed to be consistent with instruction storage. + * + * On kernels configured without SMP, this function is a nop as migrations + * across harts will not occur. + */ +int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long scope) +{ +#ifdef CONFIG_SMP + switch (ctx) { + case PR_RISCV_CTX_SW_FENCEI_ON: + switch (scope) { + case PR_RISCV_SCOPE_PER_PROCESS: + current->mm->context.force_icache_flush =3D true; + break; + case PR_RISCV_SCOPE_PER_THREAD: + current->thread.force_icache_flush =3D true; + break; + default: + return -EINVAL; + } + break; + case PR_RISCV_CTX_SW_FENCEI_OFF: + switch (scope) { + case PR_RISCV_SCOPE_PER_PROCESS: + case PR_RISCV_SCOPE_PER_THREAD: + bool stale_cpu; + cpumask_t *mask; + + current->mm->context.force_icache_flush =3D false; + + /* + * Mark every other hart's icache as needing a flush for + * this MM. Maintain the previous value of the current + * cpu to handle the case when this function is called + * concurrently on different harts. + */ + mask =3D ¤t->mm->context.icache_stale_mask; + stale_cpu =3D cpumask_test_cpu(smp_processor_id(), mask); + + cpumask_setall(mask); + assign_bit(cpumask_check(smp_processor_id()), cpumask_bits(mask), stale= _cpu); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } +#endif + return 0; +} diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 217fd4de6134..3e27e5c8c3c6 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #ifdef CONFIG_MMU =20 @@ -297,21 +298,27 @@ static inline void set_mm(struct mm_struct *prev, * * The "cpu" argument must be the current local CPU number. */ -static inline void flush_icache_deferred(struct mm_struct *mm, unsigned in= t cpu) +static inline void flush_icache_deferred(struct mm_struct *mm, unsigned in= t cpu, + struct task_struct *task) { #ifdef CONFIG_SMP cpumask_t *mask =3D &mm->context.icache_stale_mask; =20 - if (cpumask_test_cpu(cpu, mask)) { + if (cpumask_test_and_clear_cpu(cpu, mask)) { cpumask_clear_cpu(cpu, mask); + /* * Ensure the remote hart's writes are visible to this hart. * This pairs with a barrier in flush_icache_mm. */ smp_mb(); - local_flush_icache_all(); - } =20 + /* + * If cache will be flushed in switch_to, no need to flush here. + */ + if (!(task && switch_to_should_flush_icache(task))) + local_flush_icache_all(); + } #endif } =20 @@ -332,5 +339,5 @@ void switch_mm(struct mm_struct *prev, struct mm_struct= *next, =20 set_mm(prev, next, cpu); =20 - flush_icache_deferred(next, cpu); + flush_icache_deferred(next, cpu, task); } diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..524d546d697b 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -306,4 +306,10 @@ struct prctl_mm_map { # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f =20 +#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71 +# define PR_RISCV_CTX_SW_FENCEI_ON 0 +# define PR_RISCV_CTX_SW_FENCEI_OFF 1 +# define PR_RISCV_SCOPE_PER_PROCESS 0 +# define PR_RISCV_SCOPE_PER_THREAD 1 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index e219fcfa112d..69afdd8b430f 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -146,6 +146,9 @@ #ifndef RISCV_V_GET_CONTROL # define RISCV_V_GET_CONTROL() (-EINVAL) #endif +#ifndef RISCV_SET_ICACHE_FLUSH_CTX +# define RISCV_SET_ICACHE_FLUSH_CTX(a, b) (-EINVAL) +#endif =20 /* * this is where the system-wide overflow UID and GID are defined, for @@ -2743,6 +2746,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, ar= g2, unsigned long, arg3, case PR_RISCV_V_GET_CONTROL: error =3D RISCV_V_GET_CONTROL(); break; + case PR_RISCV_SET_ICACHE_FLUSH_CTX: + error =3D RISCV_SET_ICACHE_FLUSH_CTX(arg2, arg3); + break; default: error =3D -EINVAL; break; --=20 2.43.2 From nobody Mon Feb 9 09:29:18 2026 Received: from mail-oo1-f50.google.com (mail-oo1-f50.google.com [209.85.161.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EC781428E5 for ; Tue, 12 Mar 2024 19:47:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272880; cv=none; b=QqfmtkUja9tubIuHOfPLA2mxEAtJxdb2cJkR3u7e5CdZJ1e5LFkyWiAiJVmRYUFUZYOpCaVfXu7l3CNL90YURMDUMSKFTG2YtYwT175j2MHoo5BWDcd5/Di+UL2wpLWDa5cLoxny7xuNyhZVafN4JdWZNepuh3MYJ4aQr2ITMFk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272880; c=relaxed/simple; bh=VhbTJ9D/d65WnO+JrY1SIvIOPQdT9MHfEzWOw+OIGSo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XJ1UrCPgQPAsAOMnv/fKg320yxPiKCgojCW08lunMGoCPRXJsY3+WnkW3wPXcWNFkuRhNJlStL0L664Eu9F1KF7CuKR4LX5klJTdb/rnBHNlDF74RjPsJ+BvRHGrDrWCPiLeTZSSAM5T7Ya6U8JTccR05sJRLBAk4+5O8DT8YtI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=QtFhgdbK; arc=none smtp.client-ip=209.85.161.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="QtFhgdbK" Received: by mail-oo1-f50.google.com with SMTP id 006d021491bc7-5a228309c93so655284eaf.3 for ; Tue, 12 Mar 2024 12:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1710272877; x=1710877677; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Xy5TOqSKX3DblYxEOD5MVVtHMk7JBMIm4GkKJlZsbS8=; b=QtFhgdbKcCy0hrAkJpd39PXZVQ6lDUQX6kq9H9oNgZpu2uTpO/g12cv37ENG5wBogN H+nTYPRFAIAWQuiYfh1GApdp98K/9NMkYDHNCiCv6KyIuV3nmTIVNPDPyxuIf/UzjGVI sOVjTUNhHFv24+f2TwqfMXx+Zhv5mwrf+qsdEfMX962irZfDsb07V6srJS+e7jcFRjOJ PdLmGI1C6XY2+wu88ehdPxYAXUTQpe6E6eRaj4ICwwr9IDy+ZGg1/Tm67b/5yynTtXq0 wGCZrlU64tVqi+rUcFJ5uYbfvKeanEyGAKUEsnU2vqbQcIFbfKmVwD5vHO7eKK7G3iz0 DORg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710272877; x=1710877677; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xy5TOqSKX3DblYxEOD5MVVtHMk7JBMIm4GkKJlZsbS8=; b=KNe/cvmWciGGleGDoR6li6Ke8tdtpwgwbjgujnSeFDltsUG7aPGOo/qx8YLfeD5erB IoYFyxP6LN8oEwRsaTUM3ClGs+YaWpSuzg0EjHIwjTg2u9xCcQ/RhD9u4cfLR2Y2m8wP QBEmDzmWmGpgEhccREc1RkQHa+nEckDdPF00gyeHXYMwx+UMBW3lbsdH1BKctIQ5epxe mt1zCg2fUM5Cx/fWeBgP6CdoFe95th6z1J70cuuOXlqc24q3Q7Yu0iF441TwhueW3LHS D47vbWZl0kzqW0vK/W6AS0cPE8KvToJuX3l3mzygod7VIRwSd1pagpF64HJF8q88wspv Bj3g== X-Forwarded-Encrypted: i=1; AJvYcCX8EyjFvx6OULTC9o/vqvYm2n3XV78KTV0sHJ4Ndoedl+fikbEndV1QDtQnTuYkSkrlSdVsDMtjPImjepaAMkcw6t6ESanUe0lPhCUK X-Gm-Message-State: AOJu0Yxfal/HwIAwZ1s3PAz3LZD6PNzi73iL+3rj/QhwwN8Wol14K7wB p+yoAXKuQGvqbxwfl7v0ZLAjRFxpQBS3F8z56Nhx/nTGI38G2YQxh1S5LV6CXr4= X-Google-Smtp-Source: AGHT+IFd0bZPr6/Tvi+JuSoOyuixgtJ6WAYK/olTHFvdOw4qN2FQVd8SGzL4/UjSf4c9J6b7yNldzw== X-Received: by 2002:a05:6358:890:b0:17e:8b57:df56 with SMTP id m16-20020a056358089000b0017e8b57df56mr2915905rwj.5.1710272877364; Tue, 12 Mar 2024 12:47:57 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id z69-20020a633348000000b005dc884e9f5bsm6433495pgz.38.2024.03.12.12.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 12:47:56 -0700 (PDT) From: Charlie Jenkins Date: Tue, 12 Mar 2024 12:47:53 -0700 Subject: [PATCH v12 3/4] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240312-fencei-v12-3-0f340f004ce7@rivosinc.com> References: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> In-Reply-To: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1710272871; l=4601; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=VhbTJ9D/d65WnO+JrY1SIvIOPQdT9MHfEzWOw+OIGSo=; b=S4Q4g0OL9AJrAQOCaFiNRjCCUHmDz6cnpcZDAWNuFSLRFGJkYKZODksUzU2K0QWVnOLzgR8qC ctajQdPe12QC2H9MPFlltFUNQPxIkrJ/gFbKGLR5Dp9mRPYZJLteExZ X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Provide documentation that explains how to properly do CMODX in riscv. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra Reviewed-by: Alexandre Ghiti --- Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++++= ++++ Documentation/arch/riscv/index.rst | 1 + 2 files changed, 99 insertions(+) diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/= cmodx.rst new file mode 100644 index 000000000000..1c0ca06b6c97 --- /dev/null +++ b/Documentation/arch/riscv/cmodx.rst @@ -0,0 +1,98 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V L= inux +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +CMODX is a programming technique where a program executes instructions tha= t were +modified by the program itself. Instruction storage and the instruction ca= che +(icache) are not guaranteed to be synchronized on RISC-V hardware. Therefo= re, the +program must enforce its own synchronization with the unprivileged fence.i +instruction. + +However, the default Linux ABI prohibits the use of fence.i in userspace +applications. At any point the scheduler may migrate a task onto a new har= t. If +migration occurs after the userspace synchronized the icache and instructi= on +storage with fence.i, the icache on the new hart will no longer be clean. = This +is due to the behavior of fence.i only affecting the hart that it is calle= d on. +Thus, the hart that the task has been migrated to may not have synchronized +instruction storage and icache. + +There are two ways to solve this problem: use the riscv_flush_icache() sys= call, +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in +userspace. The syscall performs a one-off icache flushing operation. The p= rctl +changes the Linux ABI to allow userspace to emit icache flushing operation= s. + +As an aside, "deferred" icache flushes can sometimes be triggered in the k= ernel. +At the time of writing, this only occurs during the riscv_flush_icache() s= yscall +and when the kernel uses copy_to_user_page(). These deferred flushes happe= n only +when the memory map being used by a hart changes. If the prctl() context c= aused +an icache flush, this deferred icache flush will be skipped as it is redun= dant. +Therefore, there will be no additional flush when using the riscv_flush_ic= ache() +syscall inside of the prctl() context. + +prctl() Interface +--------------------- + +Call prctl() with ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` as the first argument.= The +remaining arguments will be delegated to the riscv_set_icache_flush_ctx +function detailed below. + +.. kernel-doc:: arch/riscv/mm/cacheflush.c + :identifiers: riscv_set_icache_flush_ctx + +Example usage: + +The following files are meant to be compiled and linked with each other. T= he +modify_instruction() function replaces an add with 0 with an add with one, +causing the instruction sequence in get_value() to change from returning a= zero +to returning a one. + +cmodx.c:: + + #include + #include + + extern int get_value(); + extern void modify_instruction(); + + int main() + { + int value =3D get_value(); + printf("Value before cmodx: %d\n", value); + + // Call prctl before first fence.i is called inside modify_instruction + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_ON, PR_RISCV_CTX_SW_FENCEI, PR_RISCV= _SCOPE_PER_PROCESS); + modify_instruction(); + // Call prctl after final fence.i is called in process + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_OFF, PR_RISCV_CTX_SW_FENCEI, PR_RISC= V_SCOPE_PER_PROCESS); + + value =3D get_value(); + printf("Value after cmodx: %d\n", value); + return 0; + } + +cmodx.S:: + + .option norvc + + .text + .global modify_instruction + modify_instruction: + lw a0, new_insn + lui a5,%hi(old_insn) + sw a0,%lo(old_insn)(a5) + fence.i + ret + + .section modifiable, "awx" + .global get_value + get_value: + li a0, 0 + old_insn: + addi a0, a0, 0 + ret + + .data + new_insn: + addi a0, a0, 1 diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/= index.rst index 4dab0cb4b900..eecf347ce849 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -13,6 +13,7 @@ RISC-V architecture patch-acceptance uabi vector + cmodx =20 features =20 --=20 2.43.2 From nobody Mon Feb 9 09:29:18 2026 Received: from mail-oo1-f44.google.com (mail-oo1-f44.google.com [209.85.161.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0ED514290B for ; Tue, 12 Mar 2024 19:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272881; cv=none; b=kiJtaIfaN5i8VAZ1t3QLoEVXg37S2PvlBxQPb0uReRhU06cw0ZLfhwBRAFC+hHLt2GhNdRn0/CeWfxAfzGm+kzvycAziU7kmgV49Gr14HZJi56/B7r7BkYVLL4Scc3hYWlamn43jHr84toV0kV2PDbn1x8+l8cat7Y400uEWu/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710272881; c=relaxed/simple; bh=BFOeXqJe9VyECGMuWiCNLoTZwBpuu0T2u1Mq+P/cqDo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RdmffKgz/i4cKypxg1LnSK9sXHFNCLHI6wSwr3g9r4uY3fWJP3LZdOB6NnIjfVPSjle7/L96TxOv8bKr+M4E08ZFbeq+DrHP51h1HGkyy2J3hIjilMoCfPJL5Sghp+7q78p0fuvP+Fz/KRqnyDhboiFYCn5+pNTzlPa4ItTQm7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=3H5ZUf6R; arc=none smtp.client-ip=209.85.161.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="3H5ZUf6R" Received: by mail-oo1-f44.google.com with SMTP id 006d021491bc7-5a22d940ff4so462291eaf.1 for ; Tue, 12 Mar 2024 12:47:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1710272879; x=1710877679; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=k4XSa/PSXORT4uTdUR+bw2OZtjIlaWQWlwg5OyZv4ig=; b=3H5ZUf6RU1lQQGj/bvMwxqw2skT0BM2V1JAvhbJWo3pFIADpfHK69fFU3QwTjE//IH RuTZZp/foAv6eTPyrIiWUJ4lrOAEBPHqNQzGdlMiwykUNBmlhKZ3KA3dJK/ZmcWdJ2W6 YcOFyt638PyoLlYPXWybdKbK0kwz5Hp5jJy8G8n9/kTwxNArZwGAZDDq4EJ+zmqt4jKj odx7M6PcT/c/a2NOhu1ZFYYAIzhYQEyeCv0g34GmkI35rjkERxxsZqEH5yWPAV2rASRr bEqAhKy2PGOux2RCXvKQQnpDHqiaeIygOlcOV4Ht2bayTsdH1c2JhrsQ/pRL/yYE4Gmz 3rJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710272879; x=1710877679; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k4XSa/PSXORT4uTdUR+bw2OZtjIlaWQWlwg5OyZv4ig=; b=arZk0ztWD4YBJ+Go+hhIkOeM49GLega5Qid9lUNIwvGD9XgzE6lNQ4xmYwLSxYVcCD vMC7pK6DZ05uLTXnRBV2vNmcH85cnuxsahkaDj/8SNJHjXrLObvUP6fSovH2vA78Ur23 gHJDhYAclQGN9uu2bt2WI0V6ya6ls3JAWFB6D2n34jZhJDDUO+kd4sukhUgrN3Qc0rYP JqW4g9zaRTgVl2psEDr6ZzhoVMmG9S15dfVu0pGiTdRjuzgxhf/UhliSdik1mDp/dtId kX+jWF024zA5jqU05n7+X6Kmx+QyWhXoQK0CZbKhozGF1OSsjCPM+qIhmeOdAiS3P0L/ 5PDg== X-Forwarded-Encrypted: i=1; AJvYcCWXL63JmtHexceV/Ut5zYirb/iZMkVSZkzyWjQRO1oyYFe5FViK61qfEMD+qxDAnWslUppeEULPH8mFxJfy1pmufxTxxAZ+7vdWz0iw X-Gm-Message-State: AOJu0Yy8msJTRYRGOl5pCAC63KTRqGkCVLBf1UcfFMAB8T073U2q+ljG vr0YVAgd0RTlhMALyVcdcuH8id0g3ERl+54R5PwMjlH6HiwUNP5jsuagkNv55EA= X-Google-Smtp-Source: AGHT+IE+Yl3rd4VRKQ0Xgn0vLA0/IXGphbXEbzUjbknciDm6FUQ1nMtO8B6Nv0KNcv+QR9Td6lCSWw== X-Received: by 2002:a05:6359:5f9f:b0:17b:88c2:5c13 with SMTP id lh31-20020a0563595f9f00b0017b88c25c13mr12958442rwc.7.1710272878964; Tue, 12 Mar 2024 12:47:58 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id z69-20020a633348000000b005dc884e9f5bsm6433495pgz.38.2024.03.12.12.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 12:47:58 -0700 (PDT) From: Charlie Jenkins Date: Tue, 12 Mar 2024 12:47:54 -0700 Subject: [PATCH v12 4/4] cpumask: Add assign cpu Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240312-fencei-v12-4-0f340f004ce7@rivosinc.com> References: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> In-Reply-To: <20240312-fencei-v12-0-0f340f004ce7@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1710272871; l=1746; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=BFOeXqJe9VyECGMuWiCNLoTZwBpuu0T2u1Mq+P/cqDo=; b=dUaXZnD9VQ8vsLYsKXOkCevPuNYqjQqs4wBvroTCyGKXR0MwtTqi+kVmNS6cpmRfvj+9eBpTV UJ9TU9gIUSeDYCpY+ggkBt8sv4yB1OqY2YjqtfD0d/3rv858ooSwNYg X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Standardize an assign_cpu function for cpumasks. Signed-off-by: Charlie Jenkins --- arch/riscv/mm/cacheflush.c | 2 +- include/linux/cpumask.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 329b95529580..2e16ed19e957 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -234,7 +234,7 @@ int riscv_set_icache_flush_ctx(unsigned long ctx, unsig= ned long scope) stale_cpu =3D cpumask_test_cpu(smp_processor_id(), mask); =20 cpumask_setall(mask); - assign_bit(cpumask_check(smp_processor_id()), cpumask_bits(mask), stale= _cpu); + cpumask_assign_cpu(smp_processor_id(), mask, stale_cpu); break; default: return -EINVAL; diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h index cfb545841a2c..1b85e09c4ba5 100644 --- a/include/linux/cpumask.h +++ b/include/linux/cpumask.h @@ -492,6 +492,22 @@ static __always_inline void __cpumask_clear_cpu(int cp= u, struct cpumask *dstp) __clear_bit(cpumask_check(cpu), cpumask_bits(dstp)); } =20 +/** + * cpumask_assign_cpu - assign a cpu in a cpumask + * @cpu: cpu number (< nr_cpu_ids) + * @dstp: the cpumask pointer + * @bool: the value to assign + */ +static __always_inline void cpumask_assign_cpu(int cpu, struct cpumask *ds= tp, bool value) +{ + assign_bit(cpumask_check(cpu), cpumask_bits(dstp), value); +} + +static __always_inline void __cpumask_assign_cpu(int cpu, struct cpumask *= dstp, bool value) +{ + __assign_bit(cpumask_check(cpu), cpumask_bits(dstp), value); +} + /** * cpumask_test_cpu - test for a cpu in a cpumask * @cpu: cpu number (< nr_cpu_ids) --=20 2.43.2