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Define those as part of the schema. Fixes: 76126a5129b5 ("clk: qcom: Add camcc clock driver for x1e80100") Signed-off-by: Bryan O'Donoghue --- .../bindings/clock/qcom,sm8450-camcc.yaml | 37 ++++++++++++++++++= ---- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index fa0e5b6b02b81..eae9b73ae1f16 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -19,9 +19,6 @@ description: | include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h =20 -allOf: - - $ref: qcom,gcc.yaml# - properties: compatible: enum: @@ -38,9 +35,8 @@ properties: - description: Sleep clock source =20 power-domains: - maxItems: 1 - description: - A phandle and PM domain specifier for the MMCX power domain. + minItems: 1 + maxItems: 2 =20 required-opps: maxItems: 1 @@ -56,6 +52,35 @@ required: - power-domains - required-opps =20 +allOf: + - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-camcc + - qcom,sm8450-camcc + - qcom,sm8550-camcc + then: + properties: + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-camcc + then: + properties: + power-domains: + items: + - description: A phandle and PM domain specifier for the MXC p= ower domain. + - description: A phandle and PM domain specifier for the MMCX = power domain. + unevaluatedProperties: false =20 examples: --=20 2.43.1 From nobody Sun Feb 8 15:53:16 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4586410F1 for ; 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Sun, 10 Mar 2024 17:33:29 -0700 (PDT) Received: from [127.0.0.1] ([176.61.106.68]) by smtp.gmail.com with ESMTPSA id m38-20020a05600c3b2600b00412b6fbb9b5sm13881720wms.8.2024.03.10.17.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Mar 2024 17:33:28 -0700 (PDT) From: Bryan O'Donoghue Date: Mon, 11 Mar 2024 00:33:26 +0000 Subject: [PATCH 2/2] clk: qcom: camcc-x1e80100: Set titan_top_gdsc as the parent GDSC of subordinate GDSCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240311-linux-next-camcc-fixes-v1-2-d126ae0b9350@linaro.org> References: <20240311-linux-next-camcc-fixes-v1-0-d126ae0b9350@linaro.org> In-Reply-To: <20240311-linux-next-camcc-fixes-v1-0-d126ae0b9350@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vladimir Zapolskiy , Abel Vesa , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-26615 The Titan TOP GDSC is the parent GDSC for all other GDSCs in the CAMCC block. None of the subordinate blocks will switch on without the parent GDSC switched on. Fixes: 76126a5129b5 ("clk: qcom: Add camcc clock driver for x1e80100") Signed-off-by: Bryan O'Donoghue Acked-by: Rajendra Nayak Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/camcc-x1e80100.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e= 80100.c index 46bb225906bff..d421da57697a2 100644 --- a/drivers/clk/qcom/camcc-x1e80100.c +++ b/drivers/clk/qcom/camcc-x1e80100.c @@ -2212,6 +2212,8 @@ static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = =3D { }, }; =20 +static struct gdsc cam_cc_titan_top_gdsc; + static struct gdsc cam_cc_bps_gdsc =3D { .gdscr =3D 0x10004, .en_rest_wait_val =3D 0x2, @@ -2221,6 +2223,7 @@ static struct gdsc cam_cc_bps_gdsc =3D { .name =3D "cam_cc_bps_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &cam_cc_titan_top_gdsc.pd, .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; =20 @@ -2233,6 +2236,7 @@ static struct gdsc cam_cc_ife_0_gdsc =3D { .name =3D "cam_cc_ife_0_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &cam_cc_titan_top_gdsc.pd, .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; =20 @@ -2245,6 +2249,7 @@ static struct gdsc cam_cc_ife_1_gdsc =3D { .name =3D "cam_cc_ife_1_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &cam_cc_titan_top_gdsc.pd, .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; =20 @@ -2257,6 +2262,7 @@ static struct gdsc cam_cc_ipe_0_gdsc =3D { .name =3D "cam_cc_ipe_0_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &cam_cc_titan_top_gdsc.pd, .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; =20 @@ -2269,6 +2275,7 @@ static struct gdsc cam_cc_sfe_0_gdsc =3D { .name =3D "cam_cc_sfe_0_gdsc", }, .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &cam_cc_titan_top_gdsc.pd, .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; =20 --=20 2.43.1