From nobody Sun Feb 8 14:11:18 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F54453E01 for ; Fri, 8 Mar 2024 10:40:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709894437; cv=none; b=F2g5XdVIMCSLHEsC1yCY/h6qwUHDzxcwCkU9gB4lsbsPKUpBikUjWWQAWFuy3ejfqR/s3Jr8kl4Ar9uGJbdjmvQMHIuP1vgqjjJmye7qcy9Fxq6SIwfVbRTfmNDpMT7inFCa/AmElby7M5sIVXZKUNhtI8LN1PuYT4SuV2OniXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709894437; c=relaxed/simple; bh=2uhKxWGX+9u6EoIE9yYtUoG0SbRFNtgP+LuuIWdCVYo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=K+f7b9lTeGRtn7RqOzkBS+i1qWR/keKvqahbCWP2mJzA93i70EXAvW+wc0ItCMCna10/igzS5LNTZhPQhO2TN1ByBHDPnpvQQZh1pobD8CsTCO3pPgPMz98YacFhN0PhQ7sKNZ9BTUkGTL/8ZeNd2yic4U71MG/rTuVFp9gzNgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eQD+8iqq; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eQD+8iqq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709894436; x=1741430436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2uhKxWGX+9u6EoIE9yYtUoG0SbRFNtgP+LuuIWdCVYo=; b=eQD+8iqqZn1LRERp2e6KkyKz8IRAsYG58Tk7PVb+mgGmbcSHbg/LtcnC FBzLkdnQXUorSuOpi1I6LXtwv9m+TMx5XgTKQuyXLluHyGEVcDn6hQk8a 42foekOsJC/l91bGotTsb+/kn4Mw0Vr+Y+osOXJ2LJzCDLz0HE3wHd+qr xzjDuJfowRkEASCQT9ToZDRzDJOfjjoetJAIpCAepcVgf3S/EUZAfNhUy qUTPZcuXE0cMYrywEMCdDW3f1TvSllMLaE5VyCpG1iZrFyX26Mzqjzvs5 970/jJUR2iOCS1F8KpyOUPLvRlQtlAOa0iyM19ulxiX0G5QUMRK8i5JLR g==; X-IronPort-AV: E=McAfee;i="6600,9927,11006"; a="4468246" X-IronPort-AV: E=Sophos;i="6.07,109,1708416000"; d="scan'208";a="4468246" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2024 02:40:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,109,1708416000"; d="scan'208";a="10327730" Received: from cascade.sh.intel.com ([10.239.48.141]) by fmviesa007.fm.intel.com with ESMTP; 08 Mar 2024 02:40:33 -0800 From: Jingqi Liu To: iommu@lists.linux.dev, Lu Baolu , Tian Kevin , Joerg Roedel , Will Deacon , Robin Murphy Cc: linux-kernel@vger.kernel.org, Jingqi Liu Subject: [PATCH 1/2] iommu/vt-d: Remove debugfs use of private data field Date: Fri, 8 Mar 2024 18:38:10 +0800 Message-Id: <20240308103811.76744-2-Jingqi.liu@intel.com> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20240308103811.76744-1-Jingqi.liu@intel.com> References: <20240308103811.76744-1-Jingqi.liu@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the page fault report and response have been tracked by ftrace, the users can easily calculate the time used for a page fault handling. There's no need to expose the similar functionality in debugfs. Hence, remove the corresponding operations in debugfs. Signed-off-by: Jingqi Liu --- drivers/iommu/intel/debugfs.c | 7 ------- drivers/iommu/intel/perf.h | 1 - drivers/iommu/intel/svm.c | 9 --------- 3 files changed, 17 deletions(-) diff --git a/drivers/iommu/intel/debugfs.c b/drivers/iommu/intel/debugfs.c index 86b506af7daa..affbf4a1558d 100644 --- a/drivers/iommu/intel/debugfs.c +++ b/drivers/iommu/intel/debugfs.c @@ -706,7 +706,6 @@ static ssize_t dmar_perf_latency_write(struct file *fil= p, dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB); dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB); dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC); - dmar_latency_disable(iommu, DMAR_LATENCY_PRQ); } rcu_read_unlock(); break; @@ -728,12 +727,6 @@ static ssize_t dmar_perf_latency_write(struct file *fi= lp, dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC); rcu_read_unlock(); break; - case 4: - rcu_read_lock(); - for_each_active_iommu(iommu, drhd) - dmar_latency_enable(iommu, DMAR_LATENCY_PRQ); - rcu_read_unlock(); - break; default: return -EINVAL; } diff --git a/drivers/iommu/intel/perf.h b/drivers/iommu/intel/perf.h index fd6db8049d1a..df9a36942d64 100644 --- a/drivers/iommu/intel/perf.h +++ b/drivers/iommu/intel/perf.h @@ -11,7 +11,6 @@ enum latency_type { DMAR_LATENCY_INV_IOTLB =3D 0, DMAR_LATENCY_INV_DEVTLB, DMAR_LATENCY_INV_IEC, - DMAR_LATENCY_PRQ, DMAR_LATENCY_NUM }; =20 diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index c1bed89b1026..4b2eeb55489d 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -583,12 +583,6 @@ static void intel_svm_prq_report(struct intel_iommu *i= ommu, struct device *dev, event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA; event.fault.prm.private_data[0] =3D desc->priv_data[0]; event.fault.prm.private_data[1] =3D desc->priv_data[1]; - } else if (dmar_latency_enabled(iommu, DMAR_LATENCY_PRQ)) { - /* - * If the private data fields are not used by hardware, use it - * to monitor the prq handle latency. - */ - event.fault.prm.private_data[0] =3D ktime_to_ns(ktime_get()); } =20 iommu_report_device_fault(dev, &event); @@ -768,9 +762,6 @@ void intel_svm_page_response(struct device *dev, struct= iopf_fault *evt, if (private_present) { desc.qw2 =3D prm->private_data[0]; desc.qw3 =3D prm->private_data[1]; - } else if (prm->private_data[0]) { - dmar_latency_update(iommu, DMAR_LATENCY_PRQ, - ktime_to_ns(ktime_get()) - prm->private_data[0]); } =20 qi_submit_sync(iommu, &desc, 1, 0); --=20 2.21.3 From nobody Sun Feb 8 14:11:18 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54C7F55788 for ; Fri, 8 Mar 2024 10:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709894439; cv=none; b=hUo62OS+aQwKXerdtpm99ThKlrHG4DN8sul0t1HYUJqFohAaXUc2JCFGNJPm5veQVTU0KYUJbVsoq6P7eoIFYns9zUDw032kDupingdKn9/Yb/vEHTJ/Kv7aiAblu7clbthwTOD7zPQi+2aToS1JmOiDzpvaRDHYqS2O9mME/GY= ARC-Message-Signature: i=1; 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08 Mar 2024 02:40:35 -0800 From: Jingqi Liu To: iommu@lists.linux.dev, Lu Baolu , Tian Kevin , Joerg Roedel , Will Deacon , Robin Murphy Cc: linux-kernel@vger.kernel.org, Jingqi Liu Subject: [PATCH 2/2] iommu/vt-d: Remove private data use in fault message Date: Fri, 8 Mar 2024 18:38:11 +0800 Message-Id: <20240308103811.76744-3-Jingqi.liu@intel.com> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20240308103811.76744-1-Jingqi.liu@intel.com> References: <20240308103811.76744-1-Jingqi.liu@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to Intel VT-d specification revision 4.0, "Private Data" field has been removed from Page Request/Response. Since the private data field is not used in fault message, remove the related definitions in page request descriptor and remove the related code in page request/response handler, as Intel hasn't shipped any products which support private data in the page request message. Signed-off-by: Jingqi Liu --- drivers/iommu/intel/iommu.h | 1 - drivers/iommu/intel/svm.c | 75 ++++++++----------------------------- include/linux/iommu.h | 3 +- 3 files changed, 16 insertions(+), 63 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 404d2476a877..9ee326f7bf62 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -455,7 +455,6 @@ enum { =20 /* Page group response descriptor QW0 */ #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4) -#define QI_PGRP_PDP(p) (((u64)(p)) << 5) #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12) #define QI_PGRP_DID(rid) (((u64)(rid)) << 16) #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 4b2eeb55489d..699bef9b9197 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -418,8 +418,7 @@ struct page_req_dsc { struct { u64 type:8; u64 pasid_present:1; - u64 priv_data_present:1; - u64 rsvd:6; + u64 rsvd:7; u64 rid:16; u64 pasid:20; u64 exe_req:1; @@ -438,7 +437,8 @@ struct page_req_dsc { }; u64 qw_1; }; - u64 priv_data[2]; + u64 qw_2; + u64 qw_3; }; =20 static bool is_canonical_address(u64 addr) @@ -572,18 +572,6 @@ static void intel_svm_prq_report(struct intel_iommu *i= ommu, struct device *dev, event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID; } - if (desc->priv_data_present) { - /* - * Set last page in group bit if private data is present, - * page response is required as it does for LPIG. - * iommu_report_device_fault() doesn't understand this vendor - * specific requirement thus we set last_page as a workaround. - */ - event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; - event.fault.prm.flags |=3D IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA; - event.fault.prm.private_data[0] =3D desc->priv_data[0]; - event.fault.prm.private_data[1] =3D desc->priv_data[1]; - } =20 iommu_report_device_fault(dev, &event); } @@ -591,39 +579,23 @@ static void intel_svm_prq_report(struct intel_iommu *= iommu, struct device *dev, static void handle_bad_prq_event(struct intel_iommu *iommu, struct page_req_dsc *req, int result) { - struct qi_desc desc; + struct qi_desc desc =3D { }; =20 pr_err("%s: Invalid page request: %08llx %08llx\n", iommu->name, ((unsigned long long *)req)[0], ((unsigned long long *)req)[1]); =20 - /* - * Per VT-d spec. v3.0 ch7.7, system software must - * respond with page group response if private data - * is present (PDP) or last page in group (LPIG) bit - * is set. This is an additional VT-d feature beyond - * PCI ATS spec. - */ - if (!req->lpig && !req->priv_data_present) + if (!req->lpig) return; =20 desc.qw0 =3D QI_PGRP_PASID(req->pasid) | QI_PGRP_DID(req->rid) | QI_PGRP_PASID_P(req->pasid_present) | - QI_PGRP_PDP(req->priv_data_present) | QI_PGRP_RESP_CODE(result) | QI_PGRP_RESP_TYPE; desc.qw1 =3D QI_PGRP_IDX(req->prg_index) | QI_PGRP_LPIG(req->lpig); =20 - if (req->priv_data_present) { - desc.qw2 =3D req->priv_data[0]; - desc.qw3 =3D req->priv_data[1]; - } else { - desc.qw2 =3D 0; - desc.qw3 =3D 0; - } - qi_submit_sync(iommu, &desc, 1, 0); } =20 @@ -691,7 +663,7 @@ static irqreturn_t prq_event_thread(int irq, void *d) =20 intel_svm_prq_report(iommu, dev, req); trace_prq_report(iommu, dev, req->qw_0, req->qw_1, - req->priv_data[0], req->priv_data[1], + req->qw_2, req->qw_3, iommu->prq_seq_number++); mutex_unlock(&iommu->iopf_lock); prq_advance: @@ -730,7 +702,7 @@ void intel_svm_page_response(struct device *dev, struct= iopf_fault *evt, struct intel_iommu *iommu =3D info->iommu; u8 bus =3D info->bus, devfn =3D info->devfn; struct iommu_fault_page_request *prm; - bool private_present; + struct qi_desc desc; bool pasid_present; bool last_page; u16 sid; @@ -738,34 +710,17 @@ void intel_svm_page_response(struct device *dev, stru= ct iopf_fault *evt, prm =3D &evt->fault.prm; sid =3D PCI_DEVID(bus, devfn); pasid_present =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; - private_present =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA; last_page =3D prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; =20 - /* - * Per VT-d spec. v3.0 ch7.7, system software must respond - * with page group response if private data is present (PDP) - * or last page in group (LPIG) bit is set. This is an - * additional VT-d requirement beyond PCI ATS spec. - */ - if (last_page || private_present) { - struct qi_desc desc; - - desc.qw0 =3D QI_PGRP_PASID(prm->pasid) | QI_PGRP_DID(sid) | - QI_PGRP_PASID_P(pasid_present) | - QI_PGRP_PDP(private_present) | - QI_PGRP_RESP_CODE(msg->code) | - QI_PGRP_RESP_TYPE; - desc.qw1 =3D QI_PGRP_IDX(prm->grpid) | QI_PGRP_LPIG(last_page); - desc.qw2 =3D 0; - desc.qw3 =3D 0; - - if (private_present) { - desc.qw2 =3D prm->private_data[0]; - desc.qw3 =3D prm->private_data[1]; - } + desc.qw0 =3D QI_PGRP_PASID(prm->pasid) | QI_PGRP_DID(sid) | + QI_PGRP_PASID_P(pasid_present) | + QI_PGRP_RESP_CODE(msg->code) | + QI_PGRP_RESP_TYPE; + desc.qw1 =3D QI_PGRP_IDX(prm->grpid) | QI_PGRP_LPIG(last_page); + desc.qw2 =3D 0; + desc.qw3 =3D 0; =20 - qi_submit_sync(iommu, &desc, 1, 0); - } + qi_submit_sync(iommu, &desc, 1, 0); } =20 static void intel_svm_domain_free(struct iommu_domain *domain) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index af6c367ed673..523bcb672efe 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -69,8 +69,7 @@ enum iommu_fault_type { struct iommu_fault_page_request { #define IOMMU_FAULT_PAGE_REQUEST_PASID_VALID (1 << 0) #define IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE (1 << 1) -#define IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA (1 << 2) -#define IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID (1 << 3) +#define IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID (1 << 2) u32 flags; u32 pasid; u32 grpid; --=20 2.21.3