From nobody Sun Feb 8 21:41:52 2026 Received: from smtp-42ac.mail.infomaniak.ch (smtp-42ac.mail.infomaniak.ch [84.16.66.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24AE01DFE8 for ; Fri, 8 Mar 2024 15:46:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709912790; cv=none; b=hoZmbGdY0zY7kKnLRUv6NJVWJev8N5O5UNbfROh83q8b9/AlaiHTgeW0wGPvfk1BG6EciY6iCDNM+1edDzT+c+okkWjwKHZI5dGpNYe4x5hK+PU++ETKBzT9DhW/vTR8Bm9Mn5GKN/BYRiOuzIXRTDEx6TgK4N8UTsXLfp0hS1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709912790; c=relaxed/simple; bh=CsxBBBSHXzQ815mZ6jxRjFfX677ayQW2fERBzYakubA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NObbA7Pbp1EudFSFDMC5zpG+dnw6EpLBGzS89oDGbMtmPQgiDHg3YYVKy0JhQ4IoY/0cCKK8KF49IUzylIVpoYQm2XxK+78IbxO40f0RDGg7lEi7QbVTovurmrsSsndw0HNo0AaQ7goSr187feC19wsKsf6o95ZZln3qpbBPJiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (unknown [10.4.36.107]) by smtp-3-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4TrrB90RFXzMpvmL; Fri, 8 Mar 2024 16:46:25 +0100 (CET) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4TrrB83sMlz3g; Fri, 8 Mar 2024 16:46:24 +0100 (CET) From: Quentin Schulz Date: Fri, 08 Mar 2024 16:46:07 +0100 Subject: [PATCH v2 1/3] arm64: dts: rockchip: enable internal pull-up on Q7_USB_ID for RK3399 Puma Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240308-puma-diode-pu-v2-1-309f83da110a@theobroma-systems.com> References: <20240308-puma-diode-pu-v2-0-309f83da110a@theobroma-systems.com> In-Reply-To: <20240308-puma-diode-pu-v2-0-309f83da110a@theobroma-systems.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Klaus Goger , Quentin Schulz , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.13.0 X-Infomaniak-Routing: alpha From: Quentin Schulz The Q7_USB_ID has a diode used as a level-shifter, and is used as an input pin. The SoC default for this pin is a pull-up, which is correct but the pinconf in the introducing commit missed that, so let's fix this oversight. Fixes: ed2c66a95c0c ("arm64: dts: rockchip: fix rk3399-puma-haikou USB OTG = mode") Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3399-puma.dtsi index 214ea62b24a5b..a51ebb8f8b80f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -459,7 +459,7 @@ vcc5v0_host_en: vcc5v0-host-en { usb3 { usb3_id: usb3-id { rockchip,pins =3D - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; --=20 2.44.0 From nobody Sun Feb 8 21:41:52 2026 Received: from smtp-190b.mail.infomaniak.ch (smtp-190b.mail.infomaniak.ch [185.125.25.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA5361DFFD for ; Fri, 8 Mar 2024 15:46:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.125.25.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709912790; cv=none; b=JaEI/GeNzUryE679MkZqr8GH8U05yAwhdhGH9NHhi6b/1Dqq/a5LqCx6TLru5Ki/VtXwjVKnXbIIPO6dGSihvWul5PK+vUPs42ZTKfEl5AwfYi37zEy8YaNZKajxhhwNpIHQNDHmNHhZjb7uygQrJIvGvsbwqRlFj2mJRRSEPwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709912790; c=relaxed/simple; bh=ibhmQTmHbyVWDQ1/jhwBdjYkiEqKWfrsbIvKFq155A8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d+rPdgq0dH1l7OGoH8Vw8AJxrp09LUeC4EjZBgkM/XUpqk3Pc1L5yX3I124BaiiMmU21tcdb91Edx+rlNhED9hDU4PnVKWlUh+rHcQpbBcNgZOcowyAQDB/XvNGUw1eZ6PNaKlOZiw03Lsqo67on7xTxgK2mZWcBKYiFlCFaggg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=185.125.25.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (smtp-3-0000.mail.infomaniak.ch [10.4.36.107]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4TrrB94fWyz179d; Fri, 8 Mar 2024 16:46:25 +0100 (CET) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4TrrB90Knxzr1; Fri, 8 Mar 2024 16:46:25 +0100 (CET) From: Quentin Schulz Date: Fri, 08 Mar 2024 16:46:08 +0100 Subject: [PATCH v2 2/3] arm64: dts: rockchip: enable internal pull-up on PCIE_WAKE# for RK3399 Puma Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240308-puma-diode-pu-v2-2-309f83da110a@theobroma-systems.com> References: <20240308-puma-diode-pu-v2-0-309f83da110a@theobroma-systems.com> In-Reply-To: <20240308-puma-diode-pu-v2-0-309f83da110a@theobroma-systems.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Klaus Goger , Quentin Schulz , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.13.0 X-Infomaniak-Routing: alpha From: Quentin Schulz The PCIE_WAKE# has a diode used as a level-shifter, and is used as an input pin. While the SoC default is to enable the pull-up, the core rk3399 pinconf for this pin opted for pull-none. So as to not disturb the behaviour of other boards which may rely on pull-none instead of pull-up, set the needed pull-up only for RK3399 Puma. Fixes: 60fd9f72ce8a ("arm64: dts: rockchip: add Haikou baseboard with RK339= 9-Q7 SoM") Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3399-puma.dtsi index a51ebb8f8b80f..2484ad2bd86fc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -416,6 +416,11 @@ &io_domains { gpio1830-supply =3D <&vcc_1v8>; }; =20 +&pcie_clkreqn_cpm { + rockchip,pins =3D + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; +}; + &pinctrl { pinctrl-names =3D "default"; pinctrl-0 =3D <&q7_thermal_pin>; --=20 2.44.0 From nobody Sun Feb 8 21:41:52 2026 Received: from smtp-8fa9.mail.infomaniak.ch (smtp-8fa9.mail.infomaniak.ch [83.166.143.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0D2F3BBE2 for ; Fri, 8 Mar 2024 15:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=83.166.143.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709912796; cv=none; b=jxgqGI5DKuOkekFdBpPohJn1d/irFQjfhmnJuzG9XEq9Zgbo6DZ895HyCKuiqNd8VlQ+oaV8yKX7Q2fKvZwH8fh++2mrubJAX75LHWLGqkn9slMBZ0Gxj7mGFu+Qs5o5HWg4PQGAvn4HuwDJA426gwf9mRMXL4kZ3IzydFXUqYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709912796; c=relaxed/simple; bh=2lDcs35zMlrFWBoz1f+V+xz2jDVMtjyyAVMGf9MUILU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lpNoK8/TURkSfKkJWcX2PRliDpdX8GGPLCbhL2qX7vLdeMPO5UQjid3uxCKEnwutNlSpihGTBJBdWQpk7fbxAjFhmuphsTo5NF9DGMpFh3xhw+wXQWwJEaPhoSt6iBMi+nUVoYy8OWR5AFvvxfqwsKScF49maWzXnuDA8RUwWTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=83.166.143.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (smtp-3-0000.mail.infomaniak.ch [10.4.36.107]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4TrrBB2DqHz14Qt; Fri, 8 Mar 2024 16:46:26 +0100 (CET) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4TrrB9553Rzr7; Fri, 8 Mar 2024 16:46:25 +0100 (CET) From: Quentin Schulz Date: Fri, 08 Mar 2024 16:46:09 +0100 Subject: [PATCH v2 3/3] arm64: dts: rockchip: add regulators for PCIe on RK3399 Puma Haikou Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240308-puma-diode-pu-v2-3-309f83da110a@theobroma-systems.com> References: <20240308-puma-diode-pu-v2-0-309f83da110a@theobroma-systems.com> In-Reply-To: <20240308-puma-diode-pu-v2-0-309f83da110a@theobroma-systems.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Klaus Goger , Quentin Schulz , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , Dragan Simic X-Mailer: b4 0.13.0 X-Infomaniak-Routing: alpha From: Quentin Schulz The PCIe PHY requires two regulators and are present on the SoM directly, while the PCIe connector also exposes 3V3 and 12V power rails which are available on the baseboard. Considering that 3/4 regulators are always-on on HW level and that the last one depends on a regulator from the PMIC that is specified as always on, this commit should be purely cosmetic and no change in behavior is expected. Let's add all regulators for PCIe on RK3399 Puma Haikou. Reviewed-by: Dragan Simic Signed-off-by: Quentin Schulz --- .../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 2 ++ arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 26 ++++++++++++++++++= ++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm= 64/boot/dts/rockchip/rk3399-puma-haikou.dts index 18a98c4648eae..66ebb148bbc9a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -194,6 +194,8 @@ &pcie0 { num-lanes =3D <4>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie_clkreqn_cpm>; + vpcie3v3-supply =3D <&vcc3v3_baseboard>; + vpcie12v-supply =3D <&dc_12v>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3399-puma.dtsi index 2484ad2bd86fc..ccbe3a7a1d2c2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -79,6 +79,26 @@ vcc5v0_sys: vcc5v0-sys { regulator-max-microvolt =3D <5000000>; }; =20 + vcca_0v9: vcca-0v9-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <&vcc_1v8>; + }; + + vcca_1v8: vcca-1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc3v3_sys>; + }; + vdd_log: vdd-log { compatible =3D "pwm-regulator"; pwms =3D <&pwm2 0 25000 1>; @@ -416,6 +436,12 @@ &io_domains { gpio1830-supply =3D <&vcc_1v8>; }; =20 +&pcie0 { + /* PCIe PHY supplies */ + vpcie0v9-supply =3D <&vcca_0v9>; + vpcie1v8-supply =3D <&vcca_1v8>; +}; + &pcie_clkreqn_cpm { rockchip,pins =3D <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; --=20 2.44.0