From nobody Fri Sep 20 01:21:32 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44F246AB6 for ; Thu, 7 Mar 2024 01:35:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709775308; cv=none; b=aWqIPXWAXRCknxvW20swqRgqMrhEn8h0yQkpYaToNK2ZCZaQ/zO324a6gFO55qGIwpMOJQBHBDFfhzY5icYlvAepcPm77/TGh3GncVKZp5FG6Jug0kJmXxmdh1FTJN0H0t4gi2r4FieukheVn+PTcrq2bLB9HGGjR/6ideubkyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709775308; c=relaxed/simple; bh=u/qdQKxxHWxdR7mQ6yXNAv14RbtVmZcngF2KU/ZM66Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GCMGNWoxbZZrPU7Pw1UNnKKPAAHT3a4QitqF0AD2a2sLGm8OV0wgGCduZgmDlrTg2Taya5DfhVr+Pj42qXDriBO0FAcx7Gp+L7V+6B38Lv5bAwg2rUfNiulBKbBZYjDhIg9RZZbbhp0C8AXBb+YAnd61wKnXy4/t3LKv4YoFCzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=QuW23RSo; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="QuW23RSo" X-UUID: ea7fbf00dc2211eeb8927bc1f75efef4-20240307 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=iVlDUuKVmuA7JnvVmCn0d4WsSJI5tUjOae/sjyXi08c=; b=QuW23RSoYuSmsY3VKcJ+n15ExFsEOn4Lh6WVA5CtMPEv0z8lk79MYcvakJWIBE4B8bUqL/IKlRLo37xcLGTi7TecdcB3BiGRsTG1wyAhQpaaphZOdZuxa9vbaopqYOY4BQXK7Qm0nIX3KmUErUx1ydkCcnwhao4TGky3NaLChTM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:19991ab9-b85c-4640-b785-cfb45e644317,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6f543d0,CLOUDID:d6353481-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ea7fbf00dc2211eeb8927bc1f75efef4-20240307 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 69131937; Thu, 07 Mar 2024 09:35:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 7 Mar 2024 09:35:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 7 Mar 2024 09:35:00 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [PATCH v2 1/4] soc: mediatek: mtk-cmdq: Add specific purpose register definitions for GCE Date: Thu, 7 Mar 2024 09:34:55 +0800 Message-ID: <20240307013458.23550-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240307013458.23550-1-jason-jh.lin@mediatek.com> References: <20240307013458.23550-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add specific purpose register definitions for GCE, so CMDQ users can use them as a buffer to store data. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno --- include/linux/soc/mediatek/mtk-cmdq.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index 649955d2cf5c..1dae80185f9f 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -14,6 +14,15 @@ #define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) #define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1)) =20 +/* + * Every cmdq thread has its own SPRs (Specific Purpose Registers), + * so there are 4 * N (threads) SPRs in GCE that shares the same indexes b= elow. + */ +#define CMDQ_THR_SPR_IDX0 (0) +#define CMDQ_THR_SPR_IDX1 (1) +#define CMDQ_THR_SPR_IDX2 (2) +#define CMDQ_THR_SPR_IDX3 (3) + struct cmdq_pkt; =20 struct cmdq_client_reg { --=20 2.18.0 From nobody Fri Sep 20 01:21:32 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0EC84689 for ; Thu, 7 Mar 2024 01:35:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709775310; cv=none; b=q+wvPX+S31lVRkwPNbacQFfD++widfCyR9s5/QlKTMLkWlsHrs4aZrjO0sPp05AouNbnK8iCytXtTg7UzvgTeiNHCaj4v5dAyzK3RzQrmGpguNHXLUpUUL4i3X+4wavHhLTfRHtG8aDCPa5DCOk4uTCmS2yIteOnB2Z8+uSOnN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709775310; c=relaxed/simple; bh=R/P93C+nqKjNKCG4RARbCb1k/JmGUftQywMIFpKDj7s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Th7QYUO2zDddSLBVxBl7cQW1yxo1DdeDTwPePBOX1ze79+ILhj/8bC7u4U32Pkal+8oMDZufKqJD4kum6poa4bAYICvE8Q8T0Eqp+nbM5t5J3O5UGyNPZj402GcWFycTET8GRAYcwr4HN5DVsOnXukXBgugz9zvFXEt3m8wQpZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=BxgMekuo; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="BxgMekuo" X-UUID: eab59080dc2211eeb8927bc1f75efef4-20240307 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8IVxyUh81LU6YKFwdjw+QHiZscbAIjJJqLNb5lFP15s=; b=BxgMekuoy3sIxhgP/GyqRyCKSAm4/l/2OwuBQbsKkxp3VEXtsvy378UqmuwXALIP+MvKREOKgWJr3nfYUQQI6lDAp/CejQmxOfVe0IiOzLHH7EBzBg3ONEHeHTo37ijo9goNNALcca0rBakMsQVO7uqNwQ5wIytpn9wKRe2ctSk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:b3581e90-60a6-41c0-b047-ae350ae1cf6c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6f543d0,CLOUDID:d7353481-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: eab59080dc2211eeb8927bc1f75efef4-20240307 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 325059637; Thu, 07 Mar 2024 09:35:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 7 Mar 2024 09:35:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 7 Mar 2024 09:35:00 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [PATCH v2 2/4] soc: mediatek: mtk-cmdq: Add cmdq_pkt_mem_move() function Date: Thu, 7 Mar 2024 09:34:56 +0800 Message-ID: <20240307013458.23550-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240307013458.23550-1-jason-jh.lin@mediatek.com> References: <20240307013458.23550-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cmdq_pkt_mem_move() function to support CMDQ user making an instruction for moving a value from a source address to a destination address. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 26 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 12 ++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index b0cd071c4719..111b5b47ac8f 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -299,6 +299,32 @@ int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, = u8 high_addr_reg_idx, } EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value); =20 +int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_= t dst_addr) +{ + const u16 high_addr_reg_idx =3D CMDQ_THR_SPR_IDX0; + const u16 value_reg_idx =3D CMDQ_THR_SPR_IDX1; + int ret; + + /* read the value of src_addr into high_addr_reg_idx */ + ret =3D cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(src_addr)); + if (ret < 0) + return ret; + ret =3D cmdq_pkt_read_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(src_addr), = value_reg_idx); + if (ret < 0) + return ret; + + /* write the value of value_reg_idx into dst_addr */ + ret =3D cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(dst_addr)); + if (ret < 0) + return ret; + ret =3D cmdq_pkt_write_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(dst_addr),= value_reg_idx); + if (ret < 0) + return ret; + + return 0; +} +EXPORT_SYMBOL(cmdq_pkt_mem_move); + int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear) { struct cmdq_instruction inst =3D { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index 1dae80185f9f..f07c9e2e0855 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -182,6 +182,18 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 hi= gh_addr_reg_idx, int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u16 addr_low, u32 value, u32 mask); =20 +/** + * cmdq_pkt_mem_move() - append memory move command to the CMDQ packet + * @pkt: the CMDQ packet + * @src_addr: source address + * @dst_addr: destination address + * + * Appends a CMDQ command to copy the value found in `src_addr` to `dst_ad= dr`. + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_= t dst_addr); + /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet * @pkt: the CMDQ packet --=20 2.18.0 From nobody Fri Sep 20 01:21:32 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E45E5522A for ; Thu, 7 Mar 2024 01:35:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709775310; cv=none; b=ieEvIkkWARJQGoaM/+f+uFgL4PQWn5jUHBd6HWHEvmTxS7BV269NrqtLE4NqSXG4cfdFuGkfhsXtg+OpXqKsvsF+Uq2f7BmqfIq8rMc2p6VubC0N5bQC6UQVrxWBLoL+XbOzNY7DASGCfE3OY+WEcBma2E8Ya2PPf5hByuiomG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709775310; 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Thu, 07 Mar 2024 09:35:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 7 Mar 2024 09:35:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 7 Mar 2024 09:35:00 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [PATCH v2 3/4] soc: mediatek: mtk-cmdq: Add cmdq_pkt_poll_addr() function Date: Thu, 7 Mar 2024 09:34:57 +0800 Message-ID: <20240307013458.23550-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240307013458.23550-1-jason-jh.lin@mediatek.com> References: <20240307013458.23550-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cmdq_pkt_poll_addr function to support CMDQ user making an instruction for polling a specific address of hardware rigster to check the value with or without mask. POLL is a legacy operation in GCE, so it does not support SPR and CMDQ_CODE_LOGIC. To support polling the register address which doesn't have the subsys id, CMDQ users need to make an instruction with GPR and CMDQ_CODE_MASK operation to move the register address to be poll into GPR. Then users can make an POLL instruction with GPR to poll the register address assigned in previous instruction. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 49 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 16 +++++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index 111b5b47ac8f..4f69df743505 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -12,6 +12,8 @@ =20 #define CMDQ_WRITE_ENABLE_MASK BIT(0) #define CMDQ_POLL_ENABLE_MASK BIT(0) +/* dedicate the last GPR_R15 to assign the register address to be poll */ +#define CMDQ_POLL_ADDR_GPR (15) #define CMDQ_EOC_IRQ_EN BIT(0) #define CMDQ_REG_TYPE 1 #define CMDQ_JUMP_RELATIVE 1 @@ -406,6 +408,53 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, } EXPORT_SYMBOL(cmdq_pkt_poll_mask); =20 +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u= 32 mask) +{ + struct cmdq_instruction inst =3D { {0} }; + u8 use_mask =3D 0; + int ret; + + /* + * Append an MASK instruction to set the mask for following POLL instruct= ion + * which enables use_mask bit. + */ + if (mask !=3D GENMASK(31, 0)) { + inst.op =3D CMDQ_CODE_MASK; + inst.mask =3D ~mask; + ret =3D cmdq_pkt_append_command(pkt, inst); + if (ret < 0) + return ret; + use_mask =3D CMDQ_POLL_ENABLE_MASK; + } + + /* + * POLL is an legacy operation in GCE and it does not support SPR and CMD= Q_CODE_LOGIC, + * so it can not use cmdq_pkt_assign to keep polling register address to = SPR. + * If user wants to poll a register address which doesn't have a subsys i= d, + * user needs to use GPR and CMDQ_CODE_MASK to move polling register addr= ess to GPR. + */ + inst.op =3D CMDQ_CODE_MASK; + inst.dst_t =3D CMDQ_REG_TYPE; + inst.sop =3D CMDQ_POLL_ADDR_GPR; + inst.value =3D addr; + ret =3D cmdq_pkt_append_command(pkt, inst); + if (ret < 0) + return ret; + + /* Append POLL instruction to poll the register address assign to GPR pre= viously. */ + inst.op =3D CMDQ_CODE_POLL; + inst.dst_t =3D CMDQ_REG_TYPE; + inst.sop =3D CMDQ_POLL_ADDR_GPR; + inst.offset =3D use_mask; + inst.value =3D value; + ret =3D cmdq_pkt_append_command(pkt, inst); + if (ret < 0) + return ret; + + return 0; +} +EXPORT_SYMBOL(cmdq_pkt_poll_addr); + int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) { struct cmdq_instruction inst =3D {}; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index f07c9e2e0855..b0004d097e23 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -255,6 +255,22 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value, u32 mask); =20 +/** + * cmdq_pkt_poll_addr() - Append blocking POLL command to CMDQ packet + * @pkt: the CMDQ packet + * @addr: the hardware register address + * @value: the specified target register value + * @mask: the specified target register mask + * + * Appends a polling (POLL) command to the CMDQ packet and asks the GCE + * to execute an instruction that checks for the specified `value` (with + * or without `mask`) to appear in the specified hardware register `addr`. + * All GCE threads will be blocked by this instruction. + * + * Return: 0 for success or negative error code + */ +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u= 32 mask); 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Thu, 7 Mar 2024 09:35:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 7 Mar 2024 09:35:00 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Shawn Sung , , , , Subject: [PATCH v2 4/4] soc: mediatek: mtk-cmdq: Add cmdq_pkt_acquire_event() function Date: Thu, 7 Mar 2024 09:34:58 +0800 Message-ID: <20240307013458.23550-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240307013458.23550-1-jason-jh.lin@mediatek.com> References: <20240307013458.23550-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.190000-8.000000 X-TMASE-MatchedRID: tjEGPsGKY1JYXTxImR5ZvLmIzqGFh/g8Xru95hSuhjQGW3hFnC9N1ayR DZpBnTnXX7ScFOAZsbSZymPU+pWEZyZ/E6AE4WkioS0guoV6SZcIYICTzfK2geOxOq7LQlGLEXF HklABLo7T01A2vEikVhDmbwdZ+OOfn/UkTj3EvcbhuXUWQoMQty6GDroi1vrlwDR44lliPu0bSl ebxhFF4jSbvF4uwAVxd6AheSID9qkfE8yM4pjsDwtuKBGekqUpnH7sbImOEBSxQ8vJIdbM4nTgE k8+6RMtbhjW7XFm5idqOdkqmO7+hgrJ3mkvzPSnPdI/7BAgjh+tEClvIxjOUeE71tGkbKASh5sU 2Hf8T1pJmt82E/eyBQGH0CAFIQWsmb5gmylW+PbGS+seVPx64j6Qrn3xh/cy X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.190000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: A380A694E5424FE041146DD541B7A1E4D8A5BF088CCF76C4B401026939EB66892000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cmdq_pkt_acquire_event() function to support CMDQ user making an instruction for acquiring event. CMDQ users can use cmdq_pkt_acquire_event() as `mutex_lock` and cmdq_pkt_clear_event() as `mutex_unlock` to protect the global resource modified instructions between them. cmdq_pkt_acquire_event() would wait for event to be cleared. After event is cleared by cmdq_pkt_clear_event() in other GCE threads, cmdq_pkt_acquire_event() would set event and keep executing next instruction. So the mutex would work like this: cmdq_pkt_acquire_event() /* mutex lock */ /* critical secton instructions that modified global resource */ cmdq_pkt_clear_event() /* mutex unlock */ Prevent the critical section instructions from being affected by other GCE threads. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index 4f69df743505..8acd8e38283e 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -343,6 +343,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool= clear) } EXPORT_SYMBOL(cmdq_pkt_wfe); =20 +int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event) +{ + struct cmdq_instruction inst =3D {}; + + if (event >=3D CMDQ_MAX_EVENT) + return -EINVAL; + + inst.op =3D CMDQ_CODE_WFE; + inst.value =3D CMDQ_WFE_UPDATE | CMDQ_WFE_UPDATE_VALUE | CMDQ_WFE_WAIT; + inst.event =3D event; + + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_acquire_event); + int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) { struct cmdq_instruction inst =3D { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index b0004d097e23..f708bcfebdd8 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -204,6 +204,21 @@ int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t= src_addr, dma_addr_t dst_ */ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear); =20 +/** + * cmdq_pkt_acquire_event() - append acquire event command to the CMDQ pac= ket + * @pkt: the CMDQ packet + * @event: the desired event to be acquired + * + * User can use cmdq_pkt_acquire_event() as `mutex_lock` and cmdq_pkt_clea= r_event() + * as `mutex_unlock` to protect some `critical section` instructions betwe= en them. + * cmdq_pkt_acquire_event() would wait for event to be cleared. + * After event is cleared by cmdq_pkt_clear_event in other GCE threads, + * cmdq_pkt_acquire_event() would set event and keep executing next instru= ction. + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event); + /** * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet * @pkt: the CMDQ packet --=20 2.18.0