From nobody Sun Feb 8 03:03:31 2026 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2E424A1E for ; Thu, 7 Mar 2024 01:13:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709774031; cv=none; b=jnuZIdG+BdGZ1m4biUGFwAflXC5eACXBjLQRXA6HG4u6WGTpjPeMcbZg6eqLhEHE1k1Iljnk3wophB/CqAM3wNgMgtGiz72kLvWbK8pgmzS1o7iLEKA4Pnp4WfauH5PULLjVr2rsZ9dH+xnnPvBAF856O0fjxzh97roeEj4dbko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709774031; c=relaxed/simple; bh=AVNvdObNYsvBPRRwBeScCDec7JNA2zRkhx+8VadcPaQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=OxWKhWH/e5Cdz/CIZlz76K2xO/NvY383rVRU7r5uW8uDSXByBdWjq7Yw4xuqk7bUGBSWibYyXH1mfkINwLiyZnlMXr1h0x+EmiZ7fHw7fZIRXWmNlKaBmGUPI9vLgzolso+zcVpc05SoHdDAbBpev4anheuJ1mNsveyWbSkXFDQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Rx+W4kyP; arc=none smtp.client-ip=209.85.128.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Rx+W4kyP" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-5ee22efe5eeso6158017b3.3 for ; Wed, 06 Mar 2024 17:13:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1709774029; x=1710378829; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=d9OkLWkUpGFKgtUTAFhUfP4KpjC4oBcPSpydtAFPWEY=; b=Rx+W4kyP8nbTCsQFCieZSroaLaXIGarCskUht94vg6kNKpZTE+W+gFdluMIxNo5XaT 5EXK1AlfSWXqb0AqX41Lrq9iP/hnN9/c8HaizZWKakq8wXiiJVnD5lWBbrfBnIxJXORG Qi8rSuWXg5CgxuS2WZIQ78iGiVoaj2Fv0AuIlUfFtaRI3ft2Z+oVOBdNIcJIEIFr+AAj gB3lnLq9v6CEPd7EyNdCK1Fe49LCSM6wulwMLwT4s45hupv+goeRNXJPSPOm4d7vtMEb 4HTCwipQBfw+P+2l+vYwxnEa/Zlw3g6UdZ24y1T0/cP/yYp5UczMfyG5QXZ1n+d/26lx ad5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709774029; x=1710378829; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=d9OkLWkUpGFKgtUTAFhUfP4KpjC4oBcPSpydtAFPWEY=; b=ZjLh+Dord9F9IYeuKzVlXfve4cgu+XUeVf9JTh631SBXxiNvp7MOD+pY/4KlYJS0JJ +xztw7mbgbbocZAeu3WNJhwOG4mIdU7+Hbn9wInrjSsYYTVOi35t9X5LyH0yaXVtDb7R uOGqUqRYFYoBLv+bkXl4mtzmNYyrGuyCLx9228ETt7pW3V0DTX3QDc4tActptlrsbz0j bYkQczwVGUhm2nM2h+m28se9KmTFw4T2HX1gVkmzV/euOWMhBb5s/mR1UPqyHiF4mY30 VUpMPXOcfdTcj8VZCb+k5NDRYCv4TKDhho+ssQRItgB7FTNto0BQHXzwtavlmzfUjpYa 6gjw== X-Forwarded-Encrypted: i=1; AJvYcCXyNZeQ8aTirU8J+9hiX3j+JL9XZz5lxON0RrCr4Bj98qdMh517L1PutDrCBhhrL19L3jdBvXudNRL6Ayk/cqx06A6JPBrzaFMdO25d X-Gm-Message-State: AOJu0YystaWVoIVgAbaDYSSB8qW5KjFgQYayNZ4fcm0zBUiKtHNpIRCO lZllf7E0mMZZSmciwIluGctUiSHVqxvjYSOqYvO+rdgCMAi0+ZSTJCNGNxU+RBeQboEnwWcEBzJ JTA== X-Google-Smtp-Source: AGHT+IF9xs3HsjzFSBIAjqUyPXm38m51wM1HHA12Wsf9f2APNF16rnLMBv/VUvy/axmyL5EwvqJpcpdBut8= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:690c:b9a:b0:609:6719:5660 with SMTP id ck26-20020a05690c0b9a00b0060967195660mr3471394ywb.9.1709774028810; Wed, 06 Mar 2024 17:13:48 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 6 Mar 2024 17:13:42 -0800 In-Reply-To: <20240307011344.835640-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240307011344.835640-1-seanjc@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Message-ID: <20240307011344.835640-2-seanjc@google.com> Subject: [PATCH 1/3] KVM: VMX: Snapshot LBR capabilities during module initialization From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Mingwei Zhang , Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Snapshot VMX's LBR capabilities once during module initialization instead of calling into perf every time a vCPU reconfigures its vPMU. This will allow massaging the LBR capabilities, e.g. if the CPU doesn't support callstacks, without having to remember to update multiple locations. Opportunistically tag vmx_get_perf_capabilities() with __init, as it's only called from vmx_set_cpu_caps(). Signed-off-by: Sean Christopherson Reviewed-by: Mingwei Zhang --- arch/x86/kvm/vmx/pmu_intel.c | 2 +- arch/x86/kvm/vmx/vmx.c | 9 +++++---- arch/x86/kvm/vmx/vmx.h | 2 ++ 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 12ade343a17e..be40474de6e4 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -535,7 +535,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) perf_capabilities =3D vcpu_get_perf_capabilities(vcpu); if (cpuid_model_is_consistent(vcpu) && (perf_capabilities & PMU_CAP_LBR_FMT)) - x86_perf_get_lbr(&lbr_desc->records); + memcpy(&lbr_desc->records, &vmx_lbr_caps, sizeof(vmx_lbr_caps)); else lbr_desc->records.nr =3D 0; =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 7a74388f9ecf..2a7cd66988a5 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -217,6 +217,8 @@ module_param(ple_window_max, uint, 0444); int __read_mostly pt_mode =3D PT_MODE_SYSTEM; module_param(pt_mode, int, S_IRUGO); =20 +struct x86_pmu_lbr __ro_after_init vmx_lbr_caps; + static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); static DEFINE_MUTEX(vmx_l1d_flush_mutex); @@ -7844,10 +7846,9 @@ static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu= *vcpu) vmx_update_exception_bitmap(vcpu); } =20 -static u64 vmx_get_perf_capabilities(void) +static __init u64 vmx_get_perf_capabilities(void) { u64 perf_cap =3D PMU_CAP_FW_WRITES; - struct x86_pmu_lbr lbr; u64 host_perf_cap =3D 0; =20 if (!enable_pmu) @@ -7857,8 +7858,8 @@ static u64 vmx_get_perf_capabilities(void) rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); =20 if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR)) { - x86_perf_get_lbr(&lbr); - if (lbr.nr) + x86_perf_get_lbr(&vmx_lbr_caps); + if (vmx_lbr_caps.nr) perf_cap |=3D host_perf_cap & PMU_CAP_LBR_FMT; } =20 diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 65786dbe7d60..cc10df53966e 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -109,6 +109,8 @@ struct lbr_desc { bool msr_passthrough; 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charset="utf-8" Add a "has_callstack" field to the x86_pmu_lbr structure used to pass information to KVM, and set it accordingly in x86_perf_get_lbr(). KVM will use has_callstack to avoid trying to create perf LBR events with PERF_SAMPLE_BRANCH_CALL_STACK on CPUs that don't support callstacks. Signed-off-by: Sean Christopherson Reviewed-by: Mingwei Zhang --- arch/x86/events/intel/lbr.c | 1 + arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 78cd5084104e..4367aa77cb8d 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1693,6 +1693,7 @@ void x86_perf_get_lbr(struct x86_pmu_lbr *lbr) lbr->from =3D x86_pmu.lbr_from; lbr->to =3D x86_pmu.lbr_to; lbr->info =3D x86_pmu.lbr_info; + lbr->has_callstack =3D x86_pmu_has_lbr_callstack(); } EXPORT_SYMBOL_GPL(x86_perf_get_lbr); =20 diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 3736b8a46c04..7f1e17250546 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -555,6 +555,7 @@ struct x86_pmu_lbr { unsigned int from; unsigned int to; unsigned int info; + bool has_callstack; }; =20 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); 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AJvYcCVkb8KNHB7GPvbl1v5L85UXVZ6/bEx9oOECqRGHA1RSzmkMCOWpH+xudhCRgVpGvRHc6k6P6/qEVfPPmQ+iW2Xv3gOTxM9CeycmtKDe X-Gm-Message-State: AOJu0YwBJ8G/pTZXXGL8OULlonNVDE4R0ADo5y7rAxwZatpnJiqk++Tq eKvqhN4gtci3YXw9qxuIb5CQRn7s4iyQK4I5YDM/fOKpOJbn/4dsJHrlILcKPQeNNj1sZRR5Mfb 2cQ== X-Google-Smtp-Source: AGHT+IGeL/DjPRgCNBVl+V/SB3gCWNCNZ4LpSUf0yDvzT/PpyTaaBz/Gs5dkdOT3yZ6PloXBBo6wJVf66G8= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:aaa3:0:b0:dc6:db9b:7a6d with SMTP id t32-20020a25aaa3000000b00dc6db9b7a6dmr665270ybi.13.1709774032394; Wed, 06 Mar 2024 17:13:52 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 6 Mar 2024 17:13:44 -0800 In-Reply-To: <20240307011344.835640-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240307011344.835640-1-seanjc@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Message-ID: <20240307011344.835640-4-seanjc@google.com> Subject: [PATCH 3/3] KVM: VMX: Disable LBR virtualization if the CPU doesn't support LBR callstacks From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Mingwei Zhang , Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Disable LBR virtualization if the CPU doesn't support callstacks, which were introduced in HSW (see commit e9d7f7cd97c4 ("perf/x86/intel: Add basic Haswell LBR call stack support"), as KVM unconditionally configures the perf LBR event with PERF_SAMPLE_BRANCH_CALL_STACK, i.e. LBR virtualization always fails on pre-HSW CPUs. Simply disable LBR support on such CPUs, as it has never worked, i.e. there is no risk of breaking an existing setup, and figuring out a way to performantly context switch LBRs on old CPUs is not worth the effort. Fixes: be635e34c284 ("KVM: vmx/pmu: Expose LBR_FMT in the MSR_IA32_PERF_CAP= ABILITIES") Cc: Mingwei Zhang Cc: Jim Mattson Signed-off-by: Sean Christopherson Tested-by: Mingwei Zhang --- arch/x86/kvm/vmx/vmx.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 2a7cd66988a5..25a7652bee7c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7859,7 +7859,15 @@ static __init u64 vmx_get_perf_capabilities(void) =20 if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR)) { x86_perf_get_lbr(&vmx_lbr_caps); - if (vmx_lbr_caps.nr) + + /* + * KVM requires LBR callstack support, as the overhead due to + * context switching LBRs without said support is too high. + * See intel_pmu_create_guest_lbr_event() for more info. + */ + if (!vmx_lbr_caps.has_callstack) + memset(&vmx_lbr_caps, 0, sizeof(vmx_lbr_caps)); + else if (vmx_lbr_caps.nr) perf_cap |=3D host_perf_cap & PMU_CAP_LBR_FMT; } =20 --=20 2.44.0.278.ge034bb2e1d-goog