From nobody Mon Feb 9 10:52:41 2026 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 092431419BA for ; Wed, 6 Mar 2024 20:04:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755473; cv=none; b=XqVGdmQLdrEYdOsU+voPmG0vyMZnZDFVkyFvhJXHcsSIdAsWm2RBeDqkwu5LxCec95JRQDF4OY0A+C+NeVhmd8dhDVZSDwD44HlV1lZJ7ErBU/Z+o81FhQxeypMcNXOxGqNn1c8+TAjT/6ftXylWHNEYVSlYvr1Dc4veDpoWShE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755473; c=relaxed/simple; bh=FzR0GpkIwoZRYWxFyEryVlUwRX7agq76vtFdOU7VZ+M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qC5ftjw+i1jnPs3ttj0Oxgq5A+K11Uk09fPfOsLtSaF/FDLSYyND00FSu8RTcPa5snh2/L5CUHss09/UfPqIvWDajbEPgavQH2sKiOIHbuXa1sUOYiRREOG+HwDWZ7v1LOpJ37BqL6QvGJW0qJ2TvPNKDGr6r4vzdX/kiqOG/ZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=V9wFoDoi; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="V9wFoDoi" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1dc09556599so1125815ad.1 for ; Wed, 06 Mar 2024 12:04:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1709755470; x=1710360270; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3EVtHtZkQ3gl1JI+EwyEBrvg+iHnnWLYEsQB5N3MR4A=; b=V9wFoDoiP/cf9Uzw/mSWEm4mfj0nlN1hIM7ax8t38JCs7eQ/12Ghw7wV0xuHtU8FcA ysEgzVYbEkZmgCdvqICp5AC7ipTttao8e3xo95n0GayFwzp6sxaKFsX6fh09rKPvp7u0 NiSKNhiWGZoq5+vlMfj94hJlsU+8S/gaA4F1xNXbX9BRZLUexnri/yJI9tUzVh2nmoVH 18ydarOF85hmsBPrypesM20P6DfWbWiWj2ngtMOo8v2yu2hADuKNKyn58gqidkO0XmiI CuJTU5WsW46mb9QiF7qFPSM4HfPbahbgiPcDcT4OqsR8krEeKDAoMVP7vNWDfGG9Lrki FxuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709755470; x=1710360270; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3EVtHtZkQ3gl1JI+EwyEBrvg+iHnnWLYEsQB5N3MR4A=; b=eJthXVETFN1UGM1MIfzTR7WqfLpT0fhPgCIJJV8jPnwGLr15G0rBjp1+qjIrv+vNyz x+z5d/DC0fVu9/F844mmpZ7dYv8Mr9PIH+r01hhSfaJ1LlqwjgFLqzgYUQL1rsDZ9bth NLJUExh+85D7TwlQOifkVX49BG/DwnwOT3v4cpyuaOuqMEai4zgCibGZz/QrGI+bm6o7 GUMOTHi8xb0ClywVuLNg1uVcC+mdS8pnCxE61MEPdG/xlaCbPPCIYAUfpCC+HliQE5Al 70cHSjhjZfw7oX07JQvSiOQcHPzxKtIjrpVOQRWxHxYO3yKsnUptCqD4P1MlCZppEAdX QgZg== X-Forwarded-Encrypted: i=1; AJvYcCW7AjgzrML+KBMjHdtONT8grlrCkGlx4LZxnfchuNCaE3qpkghxpp9qkXku5At/K0f2qb/gOP1b0JqtaTTRnbDNFlspncsGyW/QlyNP X-Gm-Message-State: AOJu0Yxj7+Y38REc5fsJEPOj1DU/qKEmq1ypg2G8vHZ3X6Pj+AB2jfFD r0C82L6VToJBPMis+c3A5E+kfALl74/XjmZ4UlLneJu5oHzmIIs78S8M5kMvhOY= X-Google-Smtp-Source: AGHT+IH7qCYemZ9Fv29kGH+ngcAW1wIPaHrs6Rzhtk+olBLCSYpKDmZzT/TWRu2OtakOAUqT9RbrtQ== X-Received: by 2002:a17:902:e892:b0:1dc:744f:5317 with SMTP id w18-20020a170902e89200b001dc744f5317mr7603710plg.50.1709755470277; Wed, 06 Mar 2024 12:04:30 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m10-20020a170902db0a00b001dd42bbb08asm874913plx.253.2024.03.06.12.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Mar 2024 12:04:29 -0800 (PST) From: Charlie Jenkins Date: Wed, 06 Mar 2024 12:00:01 -0800 Subject: [PATCH v7 1/4] riscv: lib: Introduce has_fast_unaligned_access function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240306-disable_misaligned_probe_config-v7-1-6c90419e7a96@rivosinc.com> References: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> In-Reply-To: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Eric Biggers , Elliot Berman , Charles Lohr , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709755467; l=3372; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=FzR0GpkIwoZRYWxFyEryVlUwRX7agq76vtFdOU7VZ+M=; b=j5FrAhWN5NKWo/uoDCnKRVwC+pEcmVZD3Ik3AEgIdvZs2qy2QlaslIBnPi0QfAYB7of1L9SiA U1GUl1BflS1CjE+0hvYkkMgQbTVzvSCa3r0QvML215SYBVyiy3Wja5q X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Create has_fast_unaligned_access to avoid needing to explicitly check the fast_misaligned_access_speed_key static key. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green Reviewed-by: Conor Dooley --- arch/riscv/include/asm/cpufeature.h | 11 ++++++++--- arch/riscv/kernel/cpufeature.c | 6 +++--- arch/riscv/lib/csum.c | 7 ++----- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 5a626ed2c47a..466e1f591919 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright 2022-2023 Rivos, Inc + * Copyright 2022-2024 Rivos, Inc */ =20 #ifndef _ASM_CPUFEATURE_H @@ -53,6 +53,13 @@ static inline bool check_unaligned_access_emulated(int c= pu) static inline void unaligned_emulation_finish(void) {} #endif =20 +DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); + +static __always_inline bool has_fast_unaligned_accesses(void) +{ + return static_branch_likely(&fast_unaligned_access_speed_key); +} + unsigned long riscv_get_elf_hwcap(void); =20 struct riscv_isa_ext_data { @@ -135,6 +142,4 @@ static __always_inline bool riscv_cpu_has_extension_unl= ikely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } =20 -DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); - #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..7878cddccc0d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -810,14 +810,14 @@ static void check_unaligned_access_nonboot_cpu(void *= param) check_unaligned_access(pages[cpu]); } =20 -DEFINE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); +DEFINE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); =20 static void modify_unaligned_access_branches(cpumask_t *mask, int weight) { if (cpumask_weight(mask) =3D=3D weight) - static_branch_enable_cpuslocked(&fast_misaligned_access_speed_key); + static_branch_enable_cpuslocked(&fast_unaligned_access_speed_key); else - static_branch_disable_cpuslocked(&fast_misaligned_access_speed_key); + static_branch_disable_cpuslocked(&fast_unaligned_access_speed_key); } =20 static void set_unaligned_access_static_branches_except_cpu(int cpu) diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index af3df5274ccb..7178e0acfa22 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -3,7 +3,7 @@ * Checksum library * * Influenced by arch/arm64/lib/csum.c - * Copyright (C) 2023 Rivos Inc. + * Copyright (C) 2023-2024 Rivos Inc. */ #include #include @@ -318,10 +318,7 @@ unsigned int do_csum(const unsigned char *buff, int le= n) * branches. The largest chunk of overlap was delegated into the * do_csum_common function. */ - if (static_branch_likely(&fast_misaligned_access_speed_key)) - return do_csum_no_alignment(buff, len); - - if (((unsigned long)buff & OFFSET_MASK) =3D=3D 0) + if (has_fast_unaligned_accesses() || (((unsigned long)buff & OFFSET_MASK)= =3D=3D 0)) return do_csum_no_alignment(buff, len); =20 return do_csum_with_alignment(buff, len); --=20 2.43.2 From nobody Mon Feb 9 10:52:41 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C2691420BB for ; Wed, 6 Mar 2024 20:04:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755473; cv=none; b=o6azt+/l7E5YRWX84JmDBGrcgP/UAkljW0D4NuQH44PN2HG/gMSDixfqtWtTL2YJF5A6452RRAZolMt2igx9ViH4nYpEP3BRnCMQlagANaxe1yhlCmg8872jkhLWg0k8bGPitO0y7j5DUGPbPJAZFhSCKYGR6OTFI71CoPSo6KE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755473; c=relaxed/simple; bh=VSZiKx13zcdCVDYwqIRzCcJDp79icXmI6mc1wjrw+wY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qJ27799/mqxCFvAwYRDmlbS8CdmpwNsxQRLWewuRqDgSCAmPlSY01xCxmo/d1qUJnK4LbXXH56YTDpTU9o7WRGFNqS4LYq6o/ofpcxS/Z4hl7Qu/KElpugiS18ncm8xbowmGhYBPoCdy9mN8yit/7GEvgqV+nMwtKZsg+J5cuvE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=k9FoDYV8; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="k9FoDYV8" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-1dccb2edc6dso943525ad.3 for ; Wed, 06 Mar 2024 12:04:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1709755471; x=1710360271; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=h8i7Hn0NjGdBjABWwTPM97LUVWqQ4V1pWIxyh4e32z8=; b=k9FoDYV8UTfU/j2HryRYDpAot5v/B8w7q/q3FRc1sor8Db57yqOKnh4C01ruX5AMI5 2PsCLQ0W9R7LppcDiJ2Jd1zJL/TjxQf9GNPyXT8P2EqcG5ssunmis4Mr8FoDD9NRWANd /m5n/iFiO2yWhvgupyDnnXxINHON/NfxoNhI+Duv8UoHAmwHKetd3CbsGqcS7XvPfgHp bdaXEriOpU0+UOYYqlcyBQt9Loz213z9o5h1yj+ylTVN9cEXz3Tltdd67b9kwBcm/4sx sQQwj7HydXaFIe/726i85drYu1RCQi5p2HsL9MFarLPopz0a3QEWcjvK3F7AOB9Dx3Xm /hhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709755471; x=1710360271; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h8i7Hn0NjGdBjABWwTPM97LUVWqQ4V1pWIxyh4e32z8=; b=ZJ0qgnFcWo89fflbdyTX65vgt58sAvEXFYtO90jwqhxVzhnxSvKMMTbAeWL5ZKx9wB x6PjdQowsP7gb2FOpC9V4fOgz2ORmp0+8Pl5jeNSn6pLB6XDfgbMoU6v0coD9wJfIMaV G2TsA1bCdOPCi69TBscGqSUV102foiS9gvJL1WLkckvfv58TJiS36wzomQwYFwI122lQ KaggYbwJtnAWatXUapL5Ir5n8httKr059cedq4GSudHOtRxFN0TvuPMO+qp++zMbG0+A 3+m6N41XEpmBHGMNHUYvYhYyEw694HUj3Y5iL6ZJOwxCWHOFfxT5GFivRsC26CMl8Mrz Z/mg== X-Forwarded-Encrypted: i=1; AJvYcCXF/EJsAKSuq+i4He8yhCtSx7YpM6g6HA8SnvsiQaU7ljy/MShIjNpZ8KuVoPhBMS8QEj6sHmwUJKopEoxTm2D4iMQmk0T2xu90pscZ X-Gm-Message-State: AOJu0Yy425xyie4svMMLKiHNH8FhRKmIsuJLOxNrR3/D196FlvQ8PfHn 8sUbNpANG7UO0PPSYWFUa/bBxxE8x6WfXZX5IuJF//19Mwi7v472VeClEkGXrzE= X-Google-Smtp-Source: AGHT+IFiTweil7aQBRcwI+7H86suc3cGJBwmzJVih/YHjqX8u0RZZY9V0G85J7qj4Q4zuaOUvEoKZQ== X-Received: by 2002:a17:902:f787:b0:1d9:8832:f800 with SMTP id q7-20020a170902f78700b001d98832f800mr7051856pln.8.1709755471482; Wed, 06 Mar 2024 12:04:31 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m10-20020a170902db0a00b001dd42bbb08asm874913plx.253.2024.03.06.12.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Mar 2024 12:04:30 -0800 (PST) From: Charlie Jenkins Date: Wed, 06 Mar 2024 12:00:02 -0800 Subject: [PATCH v7 2/4] riscv: Only check online cpus for emulated accesses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240306-disable_misaligned_probe_config-v7-2-6c90419e7a96@rivosinc.com> References: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> In-Reply-To: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Eric Biggers , Elliot Berman , Charles Lohr , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709755467; l=985; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=VSZiKx13zcdCVDYwqIRzCcJDp79icXmI6mc1wjrw+wY=; b=J0jL6+8JqCrPcSklgw9NSjUi73EcQ1W43bQbtjsgXL78c2d9/VwkDRPZmyz/8+75OR9dmiASR BogsnEbR27ICPcusENpMNmdyy8SN/GRLOuSHLzCSpXseFkTsqmzXnz5 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= The unaligned access checker only sets valid values for online cpus. Check for these values on online cpus rather than on present cpus. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwprob= e") --- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 8ded225e8c5b..c2ed4e689bf9 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -632,7 +632,7 @@ void unaligned_emulation_finish(void) * accesses emulated since tasks requesting such control can run on any * CPU. */ - for_each_present_cpu(cpu) { + for_each_online_cpu(cpu) { if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_EMULATED) { return; --=20 2.43.2 From nobody Mon Feb 9 10:52:41 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DEE11428E1 for ; Wed, 6 Mar 2024 20:04:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755474; cv=none; b=PydJ0UDxIlCioV6TP1nxlH78cnr9+ZR9IpM/p5t3ndYY4AikSZa38i+TJK9k+U83xB+XeS6QEamMnkPL71TMG7EzjmJq3eAYD1oAOgWVgUPnpZ4XsYdN0pw/3wB2ngl2K/A2g8Nb2bG/OW9Fdop3zYUsqM/pFmKQpJjPjgfl1fk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755474; c=relaxed/simple; bh=DInkzEsYPrFJ+waSF/dYqKLd0uhEiOzVtX3I13D+1lQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r12qHuJcsh8BOhQDpYzylhNYSHtuGEvHXpkCKwhdVOn2mZKxHLe5FWLUib/JQkowJ0itE7/FUpPZoKo6V2TPonmjN1XO7juNixZb/qpyRRrjy19ZRYYgS14YLFE0/ASwj2EB1e7m7nK/S3O9AwP+v7UoxJGWewgLPbk6GXIJj/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Lvi/ZvPC; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Lvi/ZvPC" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-1dd3bdb6e9eso818535ad.3 for ; Wed, 06 Mar 2024 12:04:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1709755472; x=1710360272; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=T3h3l0Ycd0txaXwqtGKXZSurBo/SuGyYiZV4XuZZpag=; b=Lvi/ZvPCvAo71WaarlpMKCkkcK+EiKd7t/j7dLIKWJ2gGXsnrIjtyVC1IYwPnBm1RR fuQ9NRKQVreHum0NgOZIvsMZoo+ld/gQAEoR5E2iO+dAbgjvcvmjm5Kkh8NAyvLZLlkV hgKt4EyGvDLtOOYPeZx5PiesUKZiulK44QmcVjvnIaACdE0jR62LzwvV4Z75tJcci4L5 wilqGLf94/mzheUHo8BxaNnKVl+0XmneP/lNRWUVUwXojmE5RjSpZOmEV2R4e0H6l+O1 r/oYpbhpNtsIFPp+XslKUHhzXugwBTsufC5CQn2bSxtLJmNZyV2ZwuNVCr3MqellS0f8 6ULw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709755472; x=1710360272; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T3h3l0Ycd0txaXwqtGKXZSurBo/SuGyYiZV4XuZZpag=; b=em82XrpfxyXDU7erccaAXiUOtXnrcBEmDJQX0JnEJdP31PKEhnmkmfiMntzuiEbi4U M9ToblgaZ2Wzf1KzIt9S6QGyzea8XLOR6Z3njMc/ekJqowYxU6zN8o9WnwG/f6cKqc/n dqC0+EvlZ3N3COnMq/7DEviLiKaEkPniwenTjERZ32h6fcNL9TQZG5Hu+SAHD0SfLFu1 1btqvT4IZKkvC+j2402QxSUyrAslG2VJXWo4fS1Yv8KI03s/FMmgbBoucPGKhhptYlxd tAzakXkhVj/lxcu5jb72ZSkpbyha9OOfx3f0RU46E/ZiE8fF8TYzvP+fXeF9dUlS6VkK Wwmw== X-Forwarded-Encrypted: i=1; AJvYcCWo97YqXl/RyY6coVf22vbTfGk2P69PUUGViyX3Skj/Tz6prrbTqOM1+uJHL3qs/sEEtyUbamuAPHM5nQAphdIOwyMxhRL220l4LQ1W X-Gm-Message-State: AOJu0YxlLfzDyXtyIed9+mCJZxV7sW5+eEAhycTK9vmhkcjk+C8kEYBt rg7mlWR8WCgPSGudvNhdRyQuMdpF+Av20Wry56XvOG68G/BnySHdBK5GJzaxWZg= X-Google-Smtp-Source: AGHT+IHwpkx1HSST01gu7iFAZHNQnervC8qd68WqCPj80KESLMWRMKOAlsGOCO401jQFYD/w7wCfRw== X-Received: by 2002:a17:903:24d:b0:1dc:7845:537c with SMTP id j13-20020a170903024d00b001dc7845537cmr5928989plh.1.1709755472694; Wed, 06 Mar 2024 12:04:32 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m10-20020a170902db0a00b001dd42bbb08asm874913plx.253.2024.03.06.12.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Mar 2024 12:04:32 -0800 (PST) From: Charlie Jenkins Date: Wed, 06 Mar 2024 12:00:03 -0800 Subject: [PATCH v7 3/4] riscv: Decouple emulated unaligned accesses from access speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240306-disable_misaligned_probe_config-v7-3-6c90419e7a96@rivosinc.com> References: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> In-Reply-To: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Eric Biggers , Elliot Berman , Charles Lohr , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709755467; l=4180; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=DInkzEsYPrFJ+waSF/dYqKLd0uhEiOzVtX3I13D+1lQ=; b=jrlrelGypAUGPhL6WOlc+U5QG80c/2NUPxE//1G2xYp5fWrZqTju7D+5BYoGVZA8TyX+Yol9r f30a8KDNUw1DJosvrzrZ5/YaWsWWUht2zEvTFVWwrFNokvMxtasqojP X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Detecting if a system traps into the kernel on an unaligned access can be performed separately from checking the speed of unaligned accesses. This decoupling will make it possible to selectively enable or disable each of these checks as is done in the following patch. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/include/asm/cpufeature.h | 2 +- arch/riscv/kernel/cpufeature.c | 25 +++++++++++++++++++++---- arch/riscv/kernel/traps_misaligned.c | 15 +++++++-------- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 466e1f591919..6fec91845aa0 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -37,7 +37,7 @@ void riscv_user_isa_enable(void); =20 #ifdef CONFIG_RISCV_MISALIGNED bool unaligned_ctl_available(void); -bool check_unaligned_access_emulated(int cpu); +bool check_unaligned_access_emulated_all_cpus(void); void unaligned_emulation_finish(void); #else static inline bool unaligned_ctl_available(void) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7878cddccc0d..abb3a2f53106 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -719,7 +719,8 @@ static int check_unaligned_access(void *param) void *src; long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW; =20 - if (check_unaligned_access_emulated(cpu)) + if (IS_ENABLED(CONFIG_RISCV_MISALIGNED) && + per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_U= NKNOWN) return 0; =20 /* Make an unaligned destination buffer. */ @@ -896,8 +897,8 @@ static int riscv_offline_cpu(unsigned int cpu) return 0; } =20 -/* Measure unaligned access on all CPUs present at boot in parallel. */ -static int check_unaligned_access_all_cpus(void) +/* Measure unaligned access speed on all CPUs present at boot in parallel.= */ +static int check_unaligned_access_speed_all_cpus(void) { unsigned int cpu; unsigned int cpu_count =3D num_possible_cpus(); @@ -935,7 +936,6 @@ static int check_unaligned_access_all_cpus(void) riscv_online_cpu, riscv_offline_cpu); =20 out: - unaligned_emulation_finish(); for_each_cpu(cpu, cpu_online_mask) { if (bufs[cpu]) __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); @@ -945,6 +945,23 @@ static int check_unaligned_access_all_cpus(void) return 0; } =20 +#ifdef CONFIG_RISCV_MISALIGNED +static int check_unaligned_access_all_cpus(void) +{ + bool all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); + + if (!all_cpus_emulated) + return check_unaligned_access_speed_all_cpus(); + + return 0; +} +#else +static int check_unaligned_access_all_cpus(void) +{ + return check_unaligned_access_speed_all_cpus(); +} +#endif + arch_initcall(check_unaligned_access_all_cpus); =20 void riscv_user_isa_enable(void) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index c2ed4e689bf9..e55718179f42 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -596,7 +596,7 @@ int handle_misaligned_store(struct pt_regs *regs) return 0; } =20 -bool check_unaligned_access_emulated(int cpu) +static bool check_unaligned_access_emulated(int cpu) { long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); unsigned long tmp_var, tmp_val; @@ -623,7 +623,7 @@ bool check_unaligned_access_emulated(int cpu) return misaligned_emu_detected; } =20 -void unaligned_emulation_finish(void) +bool check_unaligned_access_emulated_all_cpus(void) { int cpu; =20 @@ -632,13 +632,12 @@ void unaligned_emulation_finish(void) * accesses emulated since tasks requesting such control can run on any * CPU. */ - for_each_online_cpu(cpu) { - if (per_cpu(misaligned_access_speed, cpu) !=3D - RISCV_HWPROBE_MISALIGNED_EMULATED) { - return; - } - } + for_each_online_cpu(cpu) + if (!check_unaligned_access_emulated(cpu)) + return false; + unaligned_ctl =3D true; + return true; } =20 bool unaligned_ctl_available(void) --=20 2.43.2 From nobody Mon Feb 9 10:52:41 2026 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6B23145678 for ; Wed, 6 Mar 2024 20:04:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755477; cv=none; b=nPQHCtE5hPs4n664X10NzLghN5pGwhLIpRTDhN3Arwe5QYOPcbJdMbJ5245cwNjm2kRWkq9qrzIf9DQYS/xaT+EINBpUB0KSsrCE1RYWqwQZqxlWOBlol93Hse34Vy0d/cm93ffNAWjtBkFOmx3yZG0ZEXshCLwrniGJD1i7Qdo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709755477; c=relaxed/simple; bh=YQSzRQEY36aNSAu1ZT8yBcupfMyq9ip+srjsa/Ok5+4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HwcDheKcrsLiMpcppzpKL34jAeiFVo970n69twRiz82A4Y+rRs8h6NzGToOT69FNjtXV6y0iv5lJwg6S9diCctRRhVM6xpPoqQcHiss5hLtQzc0zVCtTrUVO3LfDQaKP9QKgpXpvnj7YY4EikYZ4Xamw2FkJ0YzBFCM1XWV8uCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=ZF7mhkIr; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="ZF7mhkIr" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1dc418fa351so9375155ad.1 for ; Wed, 06 Mar 2024 12:04:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1709755474; x=1710360274; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mB31cS97znIw0QZJWpfrr6s8PT1410LCLJ+gV8AEE0k=; b=ZF7mhkIrhcEPu1pulInTtWQBF9qLB31+51IwnGyWCgEW7yJQjgUY1acTbwuColoiXe INeouiOs/uruiwcg1YpWztda+KBF1qHUU3j9DRH2VoTeMAf5rKwvrGiOxZlWKezkbAyh T81YapVFUe0dyiOZLboWVwxdfFIew9p3hwv3jc3HdiEtDcZjoWltVKIwPSL/QaKUi4OD /WfS3TXo/v5locf3GlGVOFu4rSZdy9/Gz/b8tXPd/nI5zZgoYf9E/SW6jy3O8ymsP72r 1F+nzl3v46urvfU486nM1LzSHfutleGxd3KTMI5yjO+gmwG8FmQItu25Uxvc1FnoLf4A Fx7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709755474; x=1710360274; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mB31cS97znIw0QZJWpfrr6s8PT1410LCLJ+gV8AEE0k=; b=ktz6C5/lu//foEJAjExZWouBzbF+0wJoii+ALPWzxBoaRfsB/0i5KRaTmJmeaOxNxu LFjUx8/P8atUyyvZ+EwTLbs1HbJNxNpaHPVoII9xuhXoYkaSXXjhHEWv5e6jAcyMNlts gmcQQCmkSGRcfFMUz+N2JqT/qfzwg6qW3/m7F2IwFxcAydBgwSS1SWKEnWvQB11Uf34U ZiCIbJap9feYpV6xPauADtH8I5uI7ukXFzMJ54ohhaBRpmX0Q91Sbda170nt2N/HlORF mQOJMIZEGQeWTN52XEw1KtBa4Q8Pk0sRJ/HC2fSNTBiApER1EVcK8aIdGXhOqYCmPaJN PIxA== X-Forwarded-Encrypted: i=1; AJvYcCW6Y3+b802Q6WVWnK72hgvaSTFPouV7BRk9VwGePPCM/aCXU78kpF05pp+UGoFJtB4fOv60el1GeFmoVofo+cxVpnNbivx2laUWq3Dd X-Gm-Message-State: AOJu0YxCAiOCugj05MhQT47DsX1TXn8CDg/TpW4ThbNED8YZIKyjNvyl 0QwdzbAJLhsixiiMeTeLEums0ovSvtMebjUhb3nYm4iMuBWnhGseFYlkaH/cM+0= X-Google-Smtp-Source: AGHT+IHwlsuOQplz61h1t1hZ5HPya8GHuOaOkDwHEf6ogJCl9YDe7m0CNEzSZimLAdg7gwTi260wtw== X-Received: by 2002:a17:902:d2d2:b0:1dd:7c4:b497 with SMTP id n18-20020a170902d2d200b001dd07c4b497mr1520085plc.28.1709755474046; Wed, 06 Mar 2024 12:04:34 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m10-20020a170902db0a00b001dd42bbb08asm874913plx.253.2024.03.06.12.04.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Mar 2024 12:04:33 -0800 (PST) From: Charlie Jenkins Date: Wed, 06 Mar 2024 12:00:04 -0800 Subject: [PATCH v7 4/4] riscv: Set unaligned access speed at compile time Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240306-disable_misaligned_probe_config-v7-4-6c90419e7a96@rivosinc.com> References: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> In-Reply-To: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Eric Biggers , Elliot Berman , Charles Lohr , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709755467; l=25894; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=YQSzRQEY36aNSAu1ZT8yBcupfMyq9ip+srjsa/Ok5+4=; b=oSHbVYujOB0gr7IY8NXZbAS+mncjSeO8qEQA9D0fHzG1yJcwLiedFWMPHaCsAuGrLWPoLUUUO jMRrl4HYBbqAPHa5E8CArAosUB735pmhFdIpNZsG4tj9o58GC/55uAs X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Introduce Kconfig options to set the kernel unaligned access support. These options provide a non-portable alternative to the runtime unaligned access probe. To support this, the unaligned access probing code is moved into it's own file and gated behind a new RISCV_PROBE_UNALIGNED_ACCESS_SUPPORT option. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig | 60 ++++-- arch/riscv/include/asm/cpufeature.h | 24 +-- arch/riscv/kernel/Makefile | 4 +- arch/riscv/kernel/cpufeature.c | 272 -------------------------= --- arch/riscv/kernel/sys_hwprobe.c | 15 ++ arch/riscv/kernel/traps_misaligned.c | 2 + arch/riscv/kernel/unaligned_access_speed.c | 282 +++++++++++++++++++++++++= ++++ 7 files changed, 363 insertions(+), 296 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index bffbd869a068..28c1e75ea88a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -688,27 +688,63 @@ config THREAD_SIZE_ORDER affects irq stack size, which is equal to thread stack size. =20 config RISCV_MISALIGNED - bool "Support misaligned load/store traps for kernel and userspace" + bool select SYSCTL_ARCH_UNALIGN_ALLOW - default y help - Say Y here if you want the kernel to embed support for misaligned - load/store for both kernel and userspace. When disable, misaligned - accesses will generate SIGBUS in userspace and panic in kernel. + Embed support for misaligned load/store for both kernel and userspace. + When disabled, misaligned accesses will generate SIGBUS in userspace + and panic in the kernel. + +choice + prompt "Unaligned Accesses Support" + default RISCV_PROBE_UNALIGNED_ACCESS + help + This determines the level of support for unaligned accesses. This + information is used by the kernel to perform optimizations. It is also + exposed to user space via the hwprobe syscall. The hardware will be + probed at boot by default. + +config RISCV_PROBE_UNALIGNED_ACCESS + bool "Probe for hardware unaligned access support" + select RISCV_MISALIGNED + help + During boot, the kernel will run a series of tests to determine the + speed of unaligned accesses. This probing will dynamically determine + the speed of unaligned accesses on the underlying system. If unaligned + memory accesses trap into the kernel as they are not supported by the + system, the kernel will emulate the unaligned accesses to preserve the + UABI. + +config RISCV_EMULATED_UNALIGNED_ACCESS + bool "Emulate unaligned access where system support is missing" + select RISCV_MISALIGNED + help + If unaligned memory accesses trap into the kernel as they are not + supported by the system, the kernel will emulate the unaligned + accesses to preserve the UABI. When the underlying system does support + unaligned accesses, the unaligned accesses are assumed to be slow. + +config RISCV_SLOW_UNALIGNED_ACCESS + bool "Assume the system supports slow unaligned memory accesses" + depends on NONPORTABLE + help + Assume that the system supports slow unaligned memory accesses. The + kernel and userspace programs may not be able to run at all on systems + that do not support unaligned memory accesses. =20 config RISCV_EFFICIENT_UNALIGNED_ACCESS - bool "Assume the CPU supports fast unaligned memory accesses" + bool "Assume the system supports fast unaligned memory accesses" depends on NONPORTABLE select DCACHE_WORD_ACCESS if MMU select HAVE_EFFICIENT_UNALIGNED_ACCESS help - Say Y here if you want the kernel to assume that the CPU supports - efficient unaligned memory accesses. When enabled, this option - improves the performance of the kernel on such CPUs. However, the - kernel will run much more slowly, or will not be able to run at all, - on CPUs that do not support efficient unaligned memory accesses. + Assume that the system supports fast unaligned memory accesses. When + enabled, this option improves the performance of the kernel on such + systems. However, the kernel and userspace programs will run much more + slowly, or will not be able to run at all, on systems that do not + support efficient unaligned memory accesses. =20 - If unsure what to do here, say N. +endchoice =20 endmenu # "Platform type" =20 diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 6fec91845aa0..46061f5e9764 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -28,37 +28,39 @@ struct riscv_isainfo { =20 DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 -DECLARE_PER_CPU(long, misaligned_access_speed); - /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 void riscv_user_isa_enable(void); =20 -#ifdef CONFIG_RISCV_MISALIGNED -bool unaligned_ctl_available(void); +#if defined(CONFIG_RISCV_MISALIGNED) bool check_unaligned_access_emulated_all_cpus(void); void unaligned_emulation_finish(void); +bool unaligned_ctl_available(void); +DECLARE_PER_CPU(long, misaligned_access_speed); #else static inline bool unaligned_ctl_available(void) { return false; } - -static inline bool check_unaligned_access_emulated(int cpu) -{ - return false; -} - -static inline void unaligned_emulation_finish(void) {} #endif =20 +#if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS) DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); =20 static __always_inline bool has_fast_unaligned_accesses(void) { return static_branch_likely(&fast_unaligned_access_speed_key); } +#else +static __always_inline bool has_fast_unaligned_accesses(void) +{ + if (IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)) + return true; + else + return false; +} +#endif =20 unsigned long riscv_get_elf_hwcap(void); =20 diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f71910718053..c8085126a6f9 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -38,7 +38,6 @@ extra-y +=3D vmlinux.lds obj-y +=3D head.o obj-y +=3D soc.o obj-$(CONFIG_RISCV_ALTERNATIVE) +=3D alternative.o -obj-y +=3D copy-unaligned.o obj-y +=3D cpu.o obj-y +=3D cpufeature.o obj-y +=3D entry.o @@ -62,6 +61,9 @@ obj-y +=3D tests/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 obj-$(CONFIG_RISCV_MISALIGNED) +=3D traps_misaligned.o +obj-$(CONFIG_RISCV_MISALIGNED) +=3D unaligned_access_speed.o +obj-$(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS) +=3D copy-unaligned.o + obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_RISCV_ISA_V) +=3D vector.o obj-$(CONFIG_RISCV_ISA_V) +=3D kernel_mode_vector.o diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index abb3a2f53106..319670af5704 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -21,20 +20,12 @@ #include #include #include -#include #include #include #include =20 -#include "copy-unaligned.h" - #define NUM_ALPHA_EXTS ('z' - 'a' + 1) =20 -#define MISALIGNED_ACCESS_JIFFIES_LG2 1 -#define MISALIGNED_BUFFER_SIZE 0x4000 -#define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE) -#define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80) - unsigned long elf_hwcap __read_mostly; =20 /* Host ISA bitmap */ @@ -43,11 +34,6 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __re= ad_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 -/* Performance information */ -DEFINE_PER_CPU(long, misaligned_access_speed); - -static cpumask_t fast_misaligned_access; - /** * riscv_isa_extension_base() - Get base extension word * @@ -706,264 +692,6 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } =20 -static int check_unaligned_access(void *param) -{ - int cpu =3D smp_processor_id(); - u64 start_cycles, end_cycles; - u64 word_cycles; - u64 byte_cycles; - int ratio; - unsigned long start_jiffies, now; - struct page *page =3D param; - void *dst; - void *src; - long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW; - - if (IS_ENABLED(CONFIG_RISCV_MISALIGNED) && - per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_U= NKNOWN) - return 0; - - /* Make an unaligned destination buffer. */ - dst =3D (void *)((unsigned long)page_address(page) | 0x1); - /* Unalign src as well, but differently (off by 1 + 2 =3D 3). */ - src =3D dst + (MISALIGNED_BUFFER_SIZE / 2); - src +=3D 2; - word_cycles =3D -1ULL; - /* Do a warmup. */ - __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE); - preempt_disable(); - start_jiffies =3D jiffies; - while ((now =3D jiffies) =3D=3D start_jiffies) - cpu_relax(); - - /* - * For a fixed amount of time, repeatedly try the function, and take - * the best time in cycles as the measurement. - */ - while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) { - start_cycles =3D get_cycles64(); - /* Ensure the CSR read can't reorder WRT to the copy. */ - mb(); - __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE); - /* Ensure the copy ends before the end time is snapped. */ - mb(); - end_cycles =3D get_cycles64(); - if ((end_cycles - start_cycles) < word_cycles) - word_cycles =3D end_cycles - start_cycles; - } - - byte_cycles =3D -1ULL; - __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE); - start_jiffies =3D jiffies; - while ((now =3D jiffies) =3D=3D start_jiffies) - cpu_relax(); - - while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) { - start_cycles =3D get_cycles64(); - mb(); - __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE); - mb(); - end_cycles =3D get_cycles64(); - if ((end_cycles - start_cycles) < byte_cycles) - byte_cycles =3D end_cycles - start_cycles; - } - - preempt_enable(); - - /* Don't divide by zero. */ - if (!word_cycles || !byte_cycles) { - pr_warn("cpu%d: rdtime lacks granularity needed to measure unaligned acc= ess speed\n", - cpu); - - return 0; - } - - if (word_cycles < byte_cycles) - speed =3D RISCV_HWPROBE_MISALIGNED_FAST; - - ratio =3D div_u64((byte_cycles * 100), word_cycles); - pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.= %02d, unaligned accesses are %s\n", - cpu, - ratio / 100, - ratio % 100, - (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow"); - - per_cpu(misaligned_access_speed, cpu) =3D speed; - - /* - * Set the value of fast_misaligned_access of a CPU. These operations - * are atomic to avoid race conditions. - */ - if (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) - cpumask_set_cpu(cpu, &fast_misaligned_access); - else - cpumask_clear_cpu(cpu, &fast_misaligned_access); - - return 0; -} - -static void check_unaligned_access_nonboot_cpu(void *param) -{ - unsigned int cpu =3D smp_processor_id(); - struct page **pages =3D param; - - if (smp_processor_id() !=3D 0) - check_unaligned_access(pages[cpu]); -} - -DEFINE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); - -static void modify_unaligned_access_branches(cpumask_t *mask, int weight) -{ - if (cpumask_weight(mask) =3D=3D weight) - static_branch_enable_cpuslocked(&fast_unaligned_access_speed_key); - else - static_branch_disable_cpuslocked(&fast_unaligned_access_speed_key); -} - -static void set_unaligned_access_static_branches_except_cpu(int cpu) -{ - /* - * Same as set_unaligned_access_static_branches, except excludes the - * given CPU from the result. When a CPU is hotplugged into an offline - * state, this function is called before the CPU is set to offline in - * the cpumask, and thus the CPU needs to be explicitly excluded. - */ - - cpumask_t fast_except_me; - - cpumask_and(&fast_except_me, &fast_misaligned_access, cpu_online_mask); - cpumask_clear_cpu(cpu, &fast_except_me); - - modify_unaligned_access_branches(&fast_except_me, num_online_cpus() - 1); -} - -static void set_unaligned_access_static_branches(void) -{ - /* - * This will be called after check_unaligned_access_all_cpus so the - * result of unaligned access speed for all CPUs will be available. - * - * To avoid the number of online cpus changing between reading - * cpu_online_mask and calling num_online_cpus, cpus_read_lock must be - * held before calling this function. - */ - - cpumask_t fast_and_online; - - cpumask_and(&fast_and_online, &fast_misaligned_access, cpu_online_mask); - - modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); -} - -static int lock_and_set_unaligned_access_static_branch(void) -{ - cpus_read_lock(); - set_unaligned_access_static_branches(); - cpus_read_unlock(); - - return 0; -} - -arch_initcall_sync(lock_and_set_unaligned_access_static_branch); - -static int riscv_online_cpu(unsigned int cpu) -{ - static struct page *buf; - - /* We are already set since the last check */ - if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_U= NKNOWN) - goto exit; - - buf =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); - if (!buf) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - return -ENOMEM; - } - - check_unaligned_access(buf); - __free_pages(buf, MISALIGNED_BUFFER_ORDER); - -exit: - set_unaligned_access_static_branches(); - - return 0; -} - -static int riscv_offline_cpu(unsigned int cpu) -{ - set_unaligned_access_static_branches_except_cpu(cpu); - - return 0; -} - -/* Measure unaligned access speed on all CPUs present at boot in parallel.= */ -static int check_unaligned_access_speed_all_cpus(void) -{ - unsigned int cpu; - unsigned int cpu_count =3D num_possible_cpus(); - struct page **bufs =3D kzalloc(cpu_count * sizeof(struct page *), - GFP_KERNEL); - - if (!bufs) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - return 0; - } - - /* - * Allocate separate buffers for each CPU so there's no fighting over - * cache lines. - */ - for_each_cpu(cpu, cpu_online_mask) { - bufs[cpu] =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); - if (!bufs[cpu]) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - goto out; - } - } - - /* Check everybody except 0, who stays behind to tend jiffies. */ - on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1); - - /* Check core 0. */ - smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); - - /* - * Setup hotplug callbacks for any new CPUs that come online or go - * offline. - */ - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu, riscv_offline_cpu); - -out: - for_each_cpu(cpu, cpu_online_mask) { - if (bufs[cpu]) - __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); - } - - kfree(bufs); - return 0; -} - -#ifdef CONFIG_RISCV_MISALIGNED -static int check_unaligned_access_all_cpus(void) -{ - bool all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); - - if (!all_cpus_emulated) - return check_unaligned_access_speed_all_cpus(); - - return 0; -} -#else -static int check_unaligned_access_all_cpus(void) -{ - return check_unaligned_access_speed_all_cpus(); -} -#endif - -arch_initcall(check_unaligned_access_all_cpus); - void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZI= CBOZ)) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index a7c56b41efd2..51003f08b746 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -147,6 +147,7 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus= , unsigned long ext) return (pair.value & ext); } =20 +#if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS) static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -169,6 +170,20 @@ static u64 hwprobe_misaligned(const struct cpumask *cp= us) =20 return perf; } +#else +static u64 hwprobe_misaligned(const struct cpumask *cpus) +{ + if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS)) + if (unaligned_ctl_available()) + return RISCV_HWPROBE_MISALIGNED_EMULATED; + else + return RISCV_HWPROBE_MISALIGNED_SLOW; + else if (IS_ENABLED(CONFIG_RISCV_SLOW_UNALIGNED_ACCESS)) + return RISCV_HWPROBE_MISALIGNED_SLOW; + else if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS)) + return RISCV_HWPROBE_MISALIGNED_FAST; +} +#endif =20 static void hwprobe_one_pair(struct riscv_hwprobe *pair, const struct cpumask *cpus) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index e55718179f42..2adb7c3e4dd5 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -413,7 +413,9 @@ int handle_misaligned_load(struct pt_regs *regs) =20 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_EMUL= ATED; +#endif =20 if (!unaligned_enabled) return -1; diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c new file mode 100644 index 000000000000..52264ea4f0bd --- /dev/null +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2024 Rivos Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "copy-unaligned.h" + +#define MISALIGNED_ACCESS_JIFFIES_LG2 1 +#define MISALIGNED_BUFFER_SIZE 0x4000 +#define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE) +#define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80) + +DEFINE_PER_CPU(long, misaligned_access_speed); + +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS +static cpumask_t fast_misaligned_access; +static int check_unaligned_access(void *param) +{ + int cpu =3D smp_processor_id(); + u64 start_cycles, end_cycles; + u64 word_cycles; + u64 byte_cycles; + int ratio; + unsigned long start_jiffies, now; + struct page *page =3D param; + void *dst; + void *src; + long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW; + + if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_U= NKNOWN) + return 0; + + /* Make an unaligned destination buffer. */ + dst =3D (void *)((unsigned long)page_address(page) | 0x1); + /* Unalign src as well, but differently (off by 1 + 2 =3D 3). */ + src =3D dst + (MISALIGNED_BUFFER_SIZE / 2); + src +=3D 2; + word_cycles =3D -1ULL; + /* Do a warmup. */ + __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE); + preempt_disable(); + start_jiffies =3D jiffies; + while ((now =3D jiffies) =3D=3D start_jiffies) + cpu_relax(); + + /* + * For a fixed amount of time, repeatedly try the function, and take + * the best time in cycles as the measurement. + */ + while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) { + start_cycles =3D get_cycles64(); + /* Ensure the CSR read can't reorder WRT to the copy. */ + mb(); + __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE); + /* Ensure the copy ends before the end time is snapped. */ + mb(); + end_cycles =3D get_cycles64(); + if ((end_cycles - start_cycles) < word_cycles) + word_cycles =3D end_cycles - start_cycles; + } + + byte_cycles =3D -1ULL; + __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE); + start_jiffies =3D jiffies; + while ((now =3D jiffies) =3D=3D start_jiffies) + cpu_relax(); + + while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) { + start_cycles =3D get_cycles64(); + mb(); + __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE); + mb(); + end_cycles =3D get_cycles64(); + if ((end_cycles - start_cycles) < byte_cycles) + byte_cycles =3D end_cycles - start_cycles; + } + + preempt_enable(); + + /* Don't divide by zero. */ + if (!word_cycles || !byte_cycles) { + pr_warn("cpu%d: rdtime lacks granularity needed to measure unaligned acc= ess speed\n", + cpu); + + return 0; + } + + if (word_cycles < byte_cycles) + speed =3D RISCV_HWPROBE_MISALIGNED_FAST; + + ratio =3D div_u64((byte_cycles * 100), word_cycles); + pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.= %02d, unaligned accesses are %s\n", + cpu, + ratio / 100, + ratio % 100, + (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow"); + + per_cpu(misaligned_access_speed, cpu) =3D speed; + + /* + * Set the value of fast_misaligned_access of a CPU. These operations + * are atomic to avoid race conditions. + */ + if (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) + cpumask_set_cpu(cpu, &fast_misaligned_access); + else + cpumask_clear_cpu(cpu, &fast_misaligned_access); + + return 0; +} + +static void check_unaligned_access_nonboot_cpu(void *param) +{ + unsigned int cpu =3D smp_processor_id(); + struct page **pages =3D param; + + if (smp_processor_id() !=3D 0) + check_unaligned_access(pages[cpu]); +} + +DEFINE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); + +static void modify_unaligned_access_branches(cpumask_t *mask, int weight) +{ + if (cpumask_weight(mask) =3D=3D weight) + static_branch_enable_cpuslocked(&fast_unaligned_access_speed_key); + else + static_branch_disable_cpuslocked(&fast_unaligned_access_speed_key); +} + +static void set_unaligned_access_static_branches_except_cpu(int cpu) +{ + /* + * Same as set_unaligned_access_static_branches, except excludes the + * given CPU from the result. When a CPU is hotplugged into an offline + * state, this function is called before the CPU is set to offline in + * the cpumask, and thus the CPU needs to be explicitly excluded. + */ + + cpumask_t fast_except_me; + + cpumask_and(&fast_except_me, &fast_misaligned_access, cpu_online_mask); + cpumask_clear_cpu(cpu, &fast_except_me); + + modify_unaligned_access_branches(&fast_except_me, num_online_cpus() - 1); +} + +static void set_unaligned_access_static_branches(void) +{ + /* + * This will be called after check_unaligned_access_all_cpus so the + * result of unaligned access speed for all CPUs will be available. + * + * To avoid the number of online cpus changing between reading + * cpu_online_mask and calling num_online_cpus, cpus_read_lock must be + * held before calling this function. + */ + + cpumask_t fast_and_online; + + cpumask_and(&fast_and_online, &fast_misaligned_access, cpu_online_mask); + + modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); +} + +static int lock_and_set_unaligned_access_static_branch(void) +{ + cpus_read_lock(); + set_unaligned_access_static_branches(); + cpus_read_unlock(); + + return 0; +} + +arch_initcall_sync(lock_and_set_unaligned_access_static_branch); + +static int riscv_online_cpu(unsigned int cpu) +{ + static struct page *buf; + + /* We are already set since the last check */ + if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_U= NKNOWN) + goto exit; + + buf =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); + if (!buf) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + return -ENOMEM; + } + + check_unaligned_access(buf); + __free_pages(buf, MISALIGNED_BUFFER_ORDER); + +exit: + set_unaligned_access_static_branches(); + + return 0; +} + +static int riscv_offline_cpu(unsigned int cpu) +{ + set_unaligned_access_static_branches_except_cpu(cpu); + + return 0; +} + +/* Measure unaligned access speed on all CPUs present at boot in parallel.= */ +static int check_unaligned_access_speed_all_cpus(void) +{ + unsigned int cpu; + unsigned int cpu_count =3D num_possible_cpus(); + struct page **bufs =3D kzalloc(cpu_count * sizeof(struct page *), + GFP_KERNEL); + + if (!bufs) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + return 0; + } + + /* + * Allocate separate buffers for each CPU so there's no fighting over + * cache lines. + */ + for_each_cpu(cpu, cpu_online_mask) { + bufs[cpu] =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); + if (!bufs[cpu]) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + goto out; + } + } + + /* Check everybody except 0, who stays behind to tend jiffies. */ + on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1); + + /* Check core 0. */ + smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); + + /* + * Setup hotplug callbacks for any new CPUs that come online or go + * offline. + */ + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu, riscv_offline_cpu); + +out: + for_each_cpu(cpu, cpu_online_mask) { + if (bufs[cpu]) + __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); + } + + kfree(bufs); + return 0; +} + +static int check_unaligned_access_all_cpus(void) +{ + bool all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); + + if (!all_cpus_emulated) + return check_unaligned_access_speed_all_cpus(); + + return 0; +} +#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ +static int check_unaligned_access_all_cpus(void) +{ + check_unaligned_access_emulated_all_cpus(); + + return 0; +} +#endif + +arch_initcall(check_unaligned_access_all_cpus); --=20 2.43.2