From nobody Wed Dec 17 11:31:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 957EB45034; Wed, 6 Mar 2024 23:15:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709766952; cv=none; b=PO1ySFblyA3kaxRUoASFkNDtEh3N1+KXwvnPz2KmJKTo3d9oMQOcnjQoEhGPW4boaTZNssXnyGNCiFhl12+g4wK8xB184JOik83+POmB7NIZ1yvD3TbUIErXZCQFePJ6oMrvXPcmjyhx8KdGF9w/PO5zXg/yQqqXRwS3P8Pf+dA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709766952; c=relaxed/simple; bh=fY7XsyGWBCyMThKR5lWJhW/9PqmzwSI9SznLLw/I8/I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D335scQ/BMPOeB6q7SM28Fjvz1CDwg5HaPDBFIRL1A7D2kov/TOY+7HbaLzhv3U8d+hHtmXS/V+VR1RQwH18GVqrO6Ydfh8MCGmyqLodFCB5XnYKEAg5UBtpUqDP47ndNZPI2spqlx0stg0fagZmp5hcZ8sWpXaIVM27eyqcbZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DXcD86v+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DXcD86v+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64BF2C43330; Wed, 6 Mar 2024 23:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709766952; bh=fY7XsyGWBCyMThKR5lWJhW/9PqmzwSI9SznLLw/I8/I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DXcD86v+iNqFhP587JqwA1ZOpeibZUf4ZSZyEDDE/v+M3p6qoP7Azkj9cM02HOAYH eo5ZHVpYP7UEKCvHgoWjg9M1K+zJX2MCiNF2eNdcDzfdM2SIPhFjRApTJlamwEKwQx DvbYNylj5wB9X4JqLjukN8qYemj4l4CTFEZk9rFEh1AXZxUpEbZoP6VxyF2n43sP0y 66+rnZnHlYfyLaD8QQ2f0fLb9HXPd4LjpL2/Eyd8AYepwlb43XHhMRO5vnEm2n7TTR DSLkZ2Xsnp3BVZ7NO0LIceCZaqDqBgfNGwsJmybL6u/bg7DspfXKrLrWGllv/2pWFC 4MxtO5NbqRBNw== From: Mark Brown Date: Wed, 06 Mar 2024 23:14:54 +0000 Subject: [PATCH v5 9/9] kselftest/arm64: Add 2023 DPISA hwcap test coverage Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240306-arm64-2023-dpisa-v5-9-c568edc8ed7f@kernel.org> References: <20240306-arm64-2023-dpisa-v5-0-c568edc8ed7f@kernel.org> In-Reply-To: <20240306-arm64-2023-dpisa-v5-0-c568edc8ed7f@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-a684c X-Developer-Signature: v=1; a=openpgp-sha256; l=6393; i=broonie@kernel.org; h=from:subject:message-id; bh=fY7XsyGWBCyMThKR5lWJhW/9PqmzwSI9SznLLw/I8/I=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBl6PkIPf4xKM6Yu7Jj12VtcoLudg3aXyTrU4sxT1La WsGAUa2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZej5CAAKCRAk1otyXVSH0H6+B/ 4jaJHK3agkptHz+sTNdoXR2K45V1FnjbIQBTW5YXRbAYn4XTwxGccZjPSQzrSEnJNlHCB/jnKHcPik y1lcowHa9+pxdcrbB/Mxjxv/83xnCLRoENKzqm+qn5zuwvKdmU2Xu/v3TWBfee26zET9kEiprbngzm sA8ZZ9KYl4RmSeQY2BKpcW1P7GPX8UWsfTJoXqaxisYTaiCWnHjD8+xBsdeUS+qsNXqmFrFfQ1/VHW /Dwj68WDajxm3J/6//anbAMOUaOE5yKZ0xKvIViPh87Rg4iMCsRfoI7EK+uwf0D4fqEBtS/gW7xua0 5Iih4evvLo6OgzHFtvVBGhv5JcYj0F X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add the hwcaps added for the 2023 DPISA extensions to the hwcaps test program. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 217 ++++++++++++++++++++++++++= ++++ 1 file changed, 217 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/self= tests/arm64/abi/hwcap.c index 1189e77c8152..d8909b2b535a 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -58,11 +58,46 @@ static void cssc_sigill(void) asm volatile(".inst 0xdac01c00" : : : "x0"); } =20 +static void f8cvt_sigill(void) +{ + /* FSCALE V0.4H, V0.4H, V0.4H */ + asm volatile(".inst 0x2ec03c00"); +} + +static void f8dp2_sigill(void) +{ + /* FDOT V0.4H, V0.4H, V0.5H */ + asm volatile(".inst 0xe40fc00"); +} + +static void f8dp4_sigill(void) +{ + /* FDOT V0.2S, V0.2S, V0.2S */ + asm volatile(".inst 0xe00fc00"); +} + +static void f8fma_sigill(void) +{ + /* FMLALB V0.8H, V0.16B, V0.16B */ + asm volatile(".inst 0xec0fc00"); +} + +static void faminmax_sigill(void) +{ + /* FAMIN V0.4H, V0.4H, V0.4H */ + asm volatile(".inst 0x2ec01c00"); +} + static void fp_sigill(void) { asm volatile("fmov s0, #1"); } =20 +static void fpmr_sigill(void) +{ + asm volatile("mrs x0, S3_3_C4_C4_2" : : : "x0"); +} + static void ilrcpc_sigill(void) { /* LDAPUR W0, [SP, #8] */ @@ -95,6 +130,12 @@ static void lse128_sigill(void) : "cc", "memory"); } =20 +static void lut_sigill(void) +{ + /* LUTI2 V0.16B, { V0.16B }, V[0] */ + asm volatile(".inst 0x4e801000"); +} + static void mops_sigill(void) { char dst[1], src[1]; @@ -216,6 +257,78 @@ static void smef16f16_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } =20 +static void smef8f16_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT ZA.H[W0, 0], Z0.B-Z1.B, Z0.B-Z1.B */ + asm volatile(".inst 0xc1a01020" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smef8f32_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT ZA.S[W0, 0], { Z0.B-Z1.B }, Z0.B[0] */ + asm volatile(".inst 0xc1500038" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smelutv2_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* LUTI4 { Z0.B-Z3.B }, ZT0, { Z0-Z1 } */ + asm volatile(".inst 0xc08b0000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8dp2_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT Z0.H, Z0.B, Z0.B[0] */ + asm volatile(".inst 0x64204400" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8dp4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT Z0.S, Z0.B, Z0.B[0] */ + asm volatile(".inst 0xc1a41C00" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8fma_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMLALB V0.8H, V0.16B, V0.16B */ + asm volatile(".inst 0xec0fc00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void sve_sigill(void) { /* RDVL x0, #0 */ @@ -353,6 +466,53 @@ static const struct hwcap_data { .cpuinfo =3D "cssc", .sigill_fn =3D cssc_sigill, }, + { + .name =3D "F8CVT", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_F8CVT, + .cpuinfo =3D "f8cvt", + .sigill_fn =3D f8cvt_sigill, + }, + { + .name =3D "F8DP4", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_F8DP4, + .cpuinfo =3D "f8dp4", + .sigill_fn =3D f8dp4_sigill, + }, + { + .name =3D "F8DP2", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_F8DP2, + .cpuinfo =3D "f8dp4", + .sigill_fn =3D f8dp2_sigill, + }, + { + .name =3D "F8E5M2", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_F8E5M2, + .cpuinfo =3D "f8e5m2", + }, + { + .name =3D "F8E4M3", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_F8E4M3, + .cpuinfo =3D "f8e4m3", + }, + { + .name =3D "F8FMA", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_F8FMA, + .cpuinfo =3D "f8fma", + .sigill_fn =3D f8fma_sigill, + }, + { + .name =3D "FAMINMAX", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_FAMINMAX, + .cpuinfo =3D "faminmax", + .sigill_fn =3D faminmax_sigill, + }, { .name =3D "FP", .at_hwcap =3D AT_HWCAP, @@ -360,6 +520,14 @@ static const struct hwcap_data { .cpuinfo =3D "fp", .sigill_fn =3D fp_sigill, }, + { + .name =3D "FPMR", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_FPMR, + .cpuinfo =3D "fpmr", + .sigill_fn =3D fpmr_sigill, + .sigill_reliable =3D true, + }, { .name =3D "JSCVT", .at_hwcap =3D AT_HWCAP, @@ -411,6 +579,13 @@ static const struct hwcap_data { .cpuinfo =3D "lse128", .sigill_fn =3D lse128_sigill, }, + { + .name =3D "LUT", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_LUT, + .cpuinfo =3D "lut", + .sigill_fn =3D lut_sigill, + }, { .name =3D "MOPS", .at_hwcap =3D AT_HWCAP2, @@ -511,6 +686,48 @@ static const struct hwcap_data { .cpuinfo =3D "smef16f16", .sigill_fn =3D smef16f16_sigill, }, + { + .name =3D "SME F8F16", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_SME_F8F16, + .cpuinfo =3D "smef8f16", + .sigill_fn =3D smef8f16_sigill, + }, + { + .name =3D "SME F8F32", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_SME_F8F32, + .cpuinfo =3D "smef8f32", + .sigill_fn =3D smef8f32_sigill, + }, + { + .name =3D "SME LUTV2", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_SME_LUTV2, + .cpuinfo =3D "smelutv2", + .sigill_fn =3D smelutv2_sigill, + }, + { + .name =3D "SME SF8FMA", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_SME_SF8FMA, + .cpuinfo =3D "smesf8fma", + .sigill_fn =3D smesf8fma_sigill, + }, + { + .name =3D "SME SF8DP2", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_SME_SF8DP2, + .cpuinfo =3D "smesf8dp2", + .sigill_fn =3D smesf8dp2_sigill, + }, + { + .name =3D "SME SF8DP4", + .at_hwcap =3D AT_HWCAP2, + .hwcap_bit =3D HWCAP2_SME_SF8DP4, + .cpuinfo =3D "smesf8dp4", + .sigill_fn =3D smesf8dp4_sigill, + }, { .name =3D "SVE", .at_hwcap =3D AT_HWCAP, --=20 2.30.2