From nobody Sat Feb 7 08:47:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A00817C74 for ; Tue, 5 Mar 2024 01:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602760; cv=none; b=iRFhj5DRHEMalTnH7K8Qtgw4ZK6SLyP427SO5MyXhFNyrgJKIQ/YOI0PcCsLZv/7P9g9a8o9OAcbWH9Q5zMULKyHKCHBcL7uZAGa4UBgDAp1LyWxJZlnlNpZW8lsMRNBnHPEDlUEP0Y+FScqSv7BwCIa+grXddkdYbyN58fijOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602760; c=relaxed/simple; bh=jSRINu5rWaem2uvB6vunlGLVk7IHvJV3l54DVIsljm8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=muD8BHwEPJ7HiHOfRVVzMPDzaymSnJVaFPC9jrRhMEoAx2/97Qhy7Jpn/xMcJLk7oDC8MbuYArw9xo9V+O0LWo/K9OeiTqbZOOUiLOTSyp4O52HleReAEcb5DnlUsoDGXhhwkm9epJBkr7/ChRpYTHnxZf1HHHnJviJ+TK7CATQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jvMpyosq; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jvMpyosq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709602760; x=1741138760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jSRINu5rWaem2uvB6vunlGLVk7IHvJV3l54DVIsljm8=; b=jvMpyosqLPwXOzsZaoNVU4WqDFXS682e+d3r9I5Wxavy+/+xbHDFYXoH ys9HItYXBg5DMt7N5DGwqy8Nsdo/1eSLWLTIkbGQh+7OWi5lAv573/hlN 365A6X04kv6wkCJ+B78iOh2uVaAxkr3sexH8mod1RnrN+khoduOvFIT0d gt3Eyj9bul41edO/thpzDmjpEIqm0NyjUtBeRseq9DuX/U5lVWIm5jFZN aXyssajhmuhoxBtjp81ClT7nPSG7D8fuKd9ZOgiCsxRjAGz2wsd9o3EEn vNzrWspCjxxJlg027uxjs+KjNy5pZAYuvoPcZJ+46ejnHgBAmEIsT494n g==; X-IronPort-AV: E=McAfee;i="6600,9927,11003"; a="4286689" X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="4286689" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 17:39:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="13865441" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa004.jf.intel.com with ESMTP; 04 Mar 2024 17:39:16 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Eric Badger Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu , Jason Gunthorpe Subject: [PATCH v3 1/5] iommu: Add static iommu_ops->release_domain Date: Tue, 5 Mar 2024 09:33:01 +0800 Message-Id: <20240305013305.204605-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240305013305.204605-1-baolu.lu@linux.intel.com> References: <20240305013305.204605-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current device_release callback for individual iommu drivers does the following: 1) Silent IOMMU DMA translation: It detaches any existing domain from the device and puts it into a blocking state (some drivers might use the identity state). 2) Resource release: It releases resources allocated during the device_probe callback and restores the device to its pre-probe state. Step 1 is challenging for individual iommu drivers because each must check if a domain is already attached to the device. Additionally, if a deferred attach never occurred, the device_release should avoid modifying hardware configuration regardless of the reason for its call. To simplify this process, introduce a static release_domain within the iommu_ops structure. It can be either a blocking or identity domain depending on the iommu hardware. The iommu core will decide whether to attach this domain before the device_release callback, eliminating the need for repetitive code in various drivers. Consequently, the device_release callback can focus solely on the opposite operations of device_probe, including releasing all resources allocated during that callback. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- include/linux/iommu.h | 1 + drivers/iommu/iommu.c | 19 +++++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index af6c367ed673..2e925b5eba53 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -585,6 +585,7 @@ struct iommu_ops { struct module *owner; struct iommu_domain *identity_domain; struct iommu_domain *blocked_domain; + struct iommu_domain *release_domain; struct iommu_domain *default_domain; }; =20 diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index eb50543bf956..098869007c69 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -462,13 +462,24 @@ static void iommu_deinit_device(struct device *dev) =20 /* * release_device() must stop using any attached domain on the device. - * If there are still other devices in the group they are not effected + * If there are still other devices in the group, they are not affected * by this callback. * - * The IOMMU driver must set the device to either an identity or - * blocking translation and stop using any domain pointer, as it is - * going to be freed. + * If the iommu driver provides release_domain, the core code ensures + * that domain is attached prior to calling release_device. Drivers can + * use this to enforce a translation on the idle iommu. Typically, the + * global static blocked_domain is a good choice. + * + * Otherwise, the iommu driver must set the device to either an identity + * or a blocking translation in release_device() and stop using any + * domain pointer, as it is going to be freed. + * + * Regardless, if a delayed attach never occurred, then the release + * should still avoid touching any hardware configuration either. */ + if (!dev->iommu->attach_deferred && ops->release_domain) + ops->release_domain->ops->attach_dev(ops->release_domain, dev); + if (ops->release_device) ops->release_device(dev); =20 --=20 2.34.1 From nobody Sat Feb 7 08:47:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29726182AE for ; Tue, 5 Mar 2024 01:39:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602765; cv=none; b=CewnJNvGo5XydY9kpqn23aJzijml01Oct28yi10RTdd/xAzcbWiuT63XStsrtHgUl/dLSSyFt9dvoazReFwUUPRxfHO+UNOEsutbdxLll8JfWOW7Zlh83WmnJWTR/DTq+CknCAmoPadkkgiMF2b0JxtYSxemOya1nRs82TOekew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602765; c=relaxed/simple; bh=hCpSe1wQQmn4a4MF4QIzbrjshK2ebiCRBYaAnxsrxc4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZMkViB0n2spG65U0SMgZ+9MMcAJVkDxI/mX0dnqQvN6yxYwOX/ujhtgtRDgVJqNE3nxJNFFLIfhqmt656qoQLjbI64LQpfTzOz6bNHo7ZQ3q8LTKe5FS7hnPzvZ6Ttf0ALEjGMEZMUVK2GhNVEKbx7wG3X3urmzLhZT2rkX/bQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Gvg0v7IS; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Gvg0v7IS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709602762; x=1741138762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hCpSe1wQQmn4a4MF4QIzbrjshK2ebiCRBYaAnxsrxc4=; b=Gvg0v7ISX6bauHNGYknfOtwnnkGz65VvcQ34IKhZI5KgNrrYcnvK0drT FRUCh+Rt7g2vp+4DjQCBuSHpfNrNzdN1hdyL9W+n0pnvX4v1afo6C8Mp7 oa97HcpWrLpZDBrOr2w6dbd0nBixgSeXEuQe+xraW6iV916T0/5RQNZgH 4E+lwzVMePwJgwsM29ihUUcg3A3jXheRC7fP6c5NLgZM7VShFBmTc7MyO FDaeH/eeJYUjKZhx2x5NIkIAeZVleAnlRnuMEMIirxEfRHV02mz5/sYuT GwiWpA+FRP4gZUFRXrQKxTrIHbEZzsF8t1TEESTbtA5UbpI9POuZnwnW3 A==; X-IronPort-AV: E=McAfee;i="6600,9927,11003"; a="4286704" X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="4286704" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 17:39:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="13865453" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa004.jf.intel.com with ESMTP; 04 Mar 2024 17:39:19 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Eric Badger Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 2/5] iommu/vt-d: Fix NULL domain on device release Date: Tue, 5 Mar 2024 09:33:02 +0800 Message-Id: <20240305013305.204605-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240305013305.204605-1-baolu.lu@linux.intel.com> References: <20240305013305.204605-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the kdump kernel, the IOMMU operates in deferred_attach mode. In this mode, info->domain may not yet be assigned by the time the release_device function is called. It leads to the following crash in the crash kernel: BUG: kernel NULL pointer dereference, address: 000000000000003c ... RIP: 0010:do_raw_spin_lock+0xa/0xa0 ... _raw_spin_lock_irqsave+0x1b/0x30 intel_iommu_release_device+0x96/0x170 iommu_deinit_device+0x39/0xf0 __iommu_group_remove_device+0xa0/0xd0 iommu_bus_notifier+0x55/0xb0 notifier_call_chain+0x5a/0xd0 blocking_notifier_call_chain+0x41/0x60 bus_notify+0x34/0x50 device_del+0x269/0x3d0 pci_remove_bus_device+0x77/0x100 p2sb_bar+0xae/0x1d0 ... i801_probe+0x423/0x740 Use the release_domain mechanism to fix it. The scalable mode context entry which is not part of release_domain should be cleared in release_device(). Fixes: 586081d3f6b1 ("iommu/vt-d: Remove DEFER_DEVICE_DOMAIN_INFO") Reported-by: Eric Badger Closes: https://lore.kernel.org/r/20240113181713.1817855-1-ebadger@purestor= age.com Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/pasid.h | 1 + drivers/iommu/intel/iommu.c | 31 ++++-------------- drivers/iommu/intel/pasid.c | 64 +++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index 487ede039bdd..42fda97fd851 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -318,4 +318,5 @@ void intel_pasid_tear_down_entry(struct intel_iommu *io= mmu, bool fault_ignore); void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu, struct device *dev, u32 pasid); +void intel_pasid_teardown_sm_context(struct device *dev); #endif /* __INTEL_PASID_H */ diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index cc3994efd362..f74d42d3258f 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3869,30 +3869,6 @@ static void domain_context_clear(struct device_domai= n_info *info) &domain_context_clear_one_cb, info); } =20 -static void dmar_remove_one_dev_info(struct device *dev) -{ - struct device_domain_info *info =3D dev_iommu_priv_get(dev); - struct dmar_domain *domain =3D info->domain; - struct intel_iommu *iommu =3D info->iommu; - unsigned long flags; - - if (!dev_is_real_dma_subdevice(info->dev)) { - if (dev_is_pci(info->dev) && sm_supported(iommu)) - intel_pasid_tear_down_entry(iommu, info->dev, - IOMMU_NO_PASID, false); - - iommu_disable_pci_caps(info); - domain_context_clear(info); - } - - spin_lock_irqsave(&domain->lock, flags); - list_del(&info->link); - spin_unlock_irqrestore(&domain->lock, flags); - - domain_detach_iommu(domain, iommu); - info->domain =3D NULL; -} - /* * Clear the page table pointer in context or pasid table entries so that * all DMA requests without PASID from the device are blocked. If the page @@ -4431,7 +4407,11 @@ static void intel_iommu_release_device(struct device= *dev) mutex_lock(&iommu->iopf_lock); device_rbtree_remove(info); mutex_unlock(&iommu->iopf_lock); - dmar_remove_one_dev_info(dev); + + if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev) && + !context_copied(iommu, info->bus, info->devfn)) + intel_pasid_teardown_sm_context(dev); + intel_pasid_free_table(dev); intel_iommu_debugfs_remove_dev(info); kfree(info); @@ -4922,6 +4902,7 @@ static const struct iommu_dirty_ops intel_dirty_ops = =3D { =20 const struct iommu_ops intel_iommu_ops =3D { .blocked_domain =3D &blocking_domain, + .release_domain =3D &blocking_domain, .capable =3D intel_iommu_capable, .hw_info =3D intel_iommu_hw_info, .domain_alloc =3D intel_iommu_domain_alloc, diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 108158e2b907..9261ea986dbf 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -667,3 +667,67 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu= , struct device *dev, =20 return 0; } + +/* + * Interfaces to setup or teardown a pasid table to the scalable-mode + * context table entry: + */ + +static void device_pasid_table_teardown(struct device *dev, u8 bus, u8 dev= fn) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + struct context_entry *context; + + spin_lock(&iommu->lock); + context =3D iommu_context_addr(iommu, bus, devfn, false); + if (!context) { + spin_unlock(&iommu->lock); + return; + } + + context_clear_entry(context); + __iommu_flush_cache(iommu, context, sizeof(*context)); + spin_unlock(&iommu->lock); + + /* + * Cache invalidation for changes to a scalable-mode context table + * entry. + * + * Section 6.5.3.3 of the VT-d spec: + * - Device-selective context-cache invalidation; + * - Domain-selective PASID-cache invalidation to affected domains + * (can be skipped if all PASID entries were not-present); + * - Domain-selective IOTLB invalidation to affected domains; + * - Global Device-TLB invalidation to affected functions. + * + * The iommu has been parked in the blocking state. All domains have + * been detached from the device or PASID. The PASID and IOTLB caches + * have been invalidated during the domain detach path. + */ + iommu->flush.flush_context(iommu, 0, PCI_DEVID(bus, devfn), + DMA_CCMD_MASK_NOBIT, DMA_CCMD_DEVICE_INVL); + devtlb_invalidation_with_pasid(iommu, dev, IOMMU_NO_PASID); +} + +static int pci_pasid_table_teardown(struct pci_dev *pdev, u16 alias, void = *data) +{ + struct device *dev =3D data; + + if (dev =3D=3D &pdev->dev) + device_pasid_table_teardown(dev, PCI_BUS_NUM(alias), alias & 0xff); + + return 0; +} + +void intel_pasid_teardown_sm_context(struct device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + + if (!dev_is_pci(dev)) { + device_pasid_table_teardown(dev, info->bus, info->devfn); + return; + } + + pci_for_each_dma_alias(to_pci_dev(dev), pci_pasid_table_teardown, dev); +} --=20 2.34.1 From nobody Sat Feb 7 08:47:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB1F217C76 for ; Tue, 5 Mar 2024 01:39:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602766; cv=none; b=oebEsRu1I/zCGWA7hQiINZl4a8fHHFnjG66OVnLuY7L5M1dZzlRl7DTZ5V405X2imvsCU+Npkmm/d0VvYA9pUBYGMCI9F0EQHg4lsQpMz0ONVeMj1iBeDKUWFN6NJPOnHUVumWBmYhmPs23LXf97FuUgKjFqoHDUvkwYK/YEr9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602766; c=relaxed/simple; bh=Cx77HMO5pvAQ5Q1Jc4OgrkWnlf1+yIUlXAhkLvzu/uQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LQMZUIrCLiBFg0L2wrZl81tbeAwSR/Ww1TqFVJ5ggL7GWy5GStQJEk+V7LkcaYXREdJURsc3KX3y8ty+ye4x5HM2Adb/W9QfJzY+X5GeeNk6z7LczXgsSlBlfe9w4HRUIpNNIjkwluDYFcaHzhGbMvLEVd6W9ClRBc825/BVvPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JOyf54qp; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JOyf54qp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709602765; x=1741138765; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Cx77HMO5pvAQ5Q1Jc4OgrkWnlf1+yIUlXAhkLvzu/uQ=; b=JOyf54qpMEmjut8Xf+9MPL41D8ibkg6WCVXFP1QMfbg9jFbap3ZLb5sA OYNn63LbNpWjfKBc3S6RI41SIdDCp/8whmCnYvqBSfXSY4ig5f7A1BVUf 1r872pcys6hcgQLGNwHRWaB7Wzb7ge3Uwe5KX1IZngqbusCXDsTCn0vFS Dj+/mNftzO91A5Xs63LsgidkqSNgKEfTR7QevSJygoLxiH1DgjcVdckZU 3l1j8MhtNT5brQwaZx4z6nCt+ojDfJvzsgYc9SFLy074DfwOLR+RoURb/ Kx6YW5nWy8XnP+XmgZWB4/bxrugWdh/cl7mFGbuZskHT+BaQY02Xlb5JJ g==; X-IronPort-AV: E=McAfee;i="6600,9927,11003"; a="4286717" X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="4286717" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 17:39:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="13865470" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa004.jf.intel.com with ESMTP; 04 Mar 2024 17:39:22 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Eric Badger Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 3/5] iommu/vt-d: Setup scalable mode context entry in probe path Date: Tue, 5 Mar 2024 09:33:03 +0800 Message-Id: <20240305013305.204605-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240305013305.204605-1-baolu.lu@linux.intel.com> References: <20240305013305.204605-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In contrast to legacy mode, the DMA translation table is configured in the PASID table entry instead of the context entry for scalable mode. For this reason, it is more appropriate to set up the scalable mode context entry in the device_probe callback and direct it to the appropriate PASID table. The iommu domain attach/detach operations only affect the PASID table entry. Therefore, there is no need to modify the context entry when configuring the translation type and page table. The only exception is the kdump case, where context entry setup is postponed until the device driver invokes the first DMA interface. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/pasid.h | 1 + drivers/iommu/intel/iommu.c | 12 ++++ drivers/iommu/intel/pasid.c | 138 ++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index 42fda97fd851..da9978fef7ac 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -318,5 +318,6 @@ void intel_pasid_tear_down_entry(struct intel_iommu *io= mmu, bool fault_ignore); void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu, struct device *dev, u32 pasid); +int intel_pasid_setup_sm_context(struct device *dev); void intel_pasid_teardown_sm_context(struct device *dev); #endif /* __INTEL_PASID_H */ diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index f74d42d3258f..9b96d36b9d2a 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4073,6 +4073,10 @@ int prepare_domain_attach_device(struct iommu_domain= *domain, dmar_domain->agaw--; } =20 + if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev) && + context_copied(iommu, info->bus, info->devfn)) + return intel_pasid_setup_sm_context(dev); + return 0; } =20 @@ -4386,11 +4390,19 @@ static struct iommu_device *intel_iommu_probe_devic= e(struct device *dev) dev_err(dev, "PASID table allocation failed\n"); goto clear_rbtree; } + + if (!context_copied(iommu, info->bus, info->devfn)) { + ret =3D intel_pasid_setup_sm_context(dev); + if (ret) + goto free_table; + } } =20 intel_iommu_debugfs_create_dev(info); =20 return &iommu->iommu; +free_table: + intel_pasid_free_table(dev); clear_rbtree: device_rbtree_remove(info); free: diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 9261ea986dbf..625d5cff49c3 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -731,3 +731,141 @@ void intel_pasid_teardown_sm_context(struct device *d= ev) =20 pci_for_each_dma_alias(to_pci_dev(dev), pci_pasid_table_teardown, dev); } + +/* + * Get the PASID directory size for scalable mode context entry. + * Value of X in the PDTS field of a scalable mode context entry + * indicates PASID directory with 2^(X + 7) entries. + */ +static unsigned long context_get_sm_pds(struct pasid_table *table) +{ + unsigned long pds, max_pde; + + max_pde =3D table->max_pasid >> PASID_PDE_SHIFT; + pds =3D find_first_bit(&max_pde, MAX_NR_PASID_BITS); + if (pds < 7) + return 0; + + return pds - 7; +} + +static int context_entry_set_pasid_table(struct context_entry *context, + struct device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct pasid_table *table =3D info->pasid_table; + struct intel_iommu *iommu =3D info->iommu; + unsigned long pds; + + context_clear_entry(context); + + pds =3D context_get_sm_pds(table); + context->lo =3D (u64)virt_to_phys(table->table) | context_pdts(pds); + context_set_sm_rid2pasid(context, IOMMU_NO_PASID); + + if (info->ats_supported) + context_set_sm_dte(context); + if (info->pri_supported) + context_set_sm_pre(context); + if (info->pasid_supported) + context_set_pasid(context); + + context_set_fault_enable(context); + context_set_present(context); + __iommu_flush_cache(iommu, context, sizeof(*context)); + + return 0; +} + +static int device_pasid_table_setup(struct device *dev, u8 bus, u8 devfn) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + struct context_entry *context; + + spin_lock(&iommu->lock); + context =3D iommu_context_addr(iommu, bus, devfn, true); + if (!context) { + spin_unlock(&iommu->lock); + return -ENOMEM; + } + + if (context_present(context) && !context_copied(iommu, bus, devfn)) { + spin_unlock(&iommu->lock); + return 0; + } + + if (context_copied(iommu, bus, devfn)) { + context_clear_entry(context); + __iommu_flush_cache(iommu, context, sizeof(*context)); + + /* + * For kdump cases, old valid entries may be cached due to + * the in-flight DMA and copied pgtable, but there is no + * unmapping behaviour for them, thus we need explicit cache + * flushes for all affected domain IDs and PASIDs used in + * the copied PASID table. Given that we have no idea about + * which domain IDs and PASIDs were used in the copied tables, + * upgrade them to global PASID and IOTLB cache invalidation. + */ + iommu->flush.flush_context(iommu, 0, + PCI_DEVID(bus, devfn), + DMA_CCMD_MASK_NOBIT, + DMA_CCMD_DEVICE_INVL); + qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0); + iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); + devtlb_invalidation_with_pasid(iommu, dev, IOMMU_NO_PASID); + + /* + * At this point, the device is supposed to finish reset at + * its driver probe stage, so no in-flight DMA will exist, + * and we don't need to worry anymore hereafter. + */ + clear_context_copied(iommu, bus, devfn); + } + + context_entry_set_pasid_table(context, dev); + spin_unlock(&iommu->lock); + + /* + * It's a non-present to present mapping. If hardware doesn't cache + * non-present entry we don't need to flush the caches. If it does + * cache non-present entries, then it does so in the special + * domain #0, which we have to flush: + */ + if (cap_caching_mode(iommu->cap)) { + iommu->flush.flush_context(iommu, 0, + PCI_DEVID(bus, devfn), + DMA_CCMD_MASK_NOBIT, + DMA_CCMD_DEVICE_INVL); + iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH); + } + + return 0; +} + +static int pci_pasid_table_setup(struct pci_dev *pdev, u16 alias, void *da= ta) +{ + struct device *dev =3D data; + + if (dev !=3D &pdev->dev) + return 0; + + return device_pasid_table_setup(dev, PCI_BUS_NUM(alias), alias & 0xff); +} + +/* + * Set the device's PASID table to its context table entry. + * + * The PASID table is set to the context entries of both device itself + * and its alias requester ID for DMA. + */ +int intel_pasid_setup_sm_context(struct device *dev) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + + if (!dev_is_pci(dev)) + return device_pasid_table_setup(dev, info->bus, info->devfn); + + return pci_for_each_dma_alias(to_pci_dev(dev), pci_pasid_table_setup, dev= ); +} --=20 2.34.1 From nobody Sat Feb 7 08:47:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCAA818EA2 for ; Tue, 5 Mar 2024 01:39:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602769; cv=none; b=HXUIW4q8eZPfr33Yat7HUP19K/PP3VcTts5cEJyBLXanC7jEs7ry/QSDIyiJ5LqQwv7PTxCKQbkhP/9prv5tbFHhWOkeBx9oMMXMwf+3cFVSZ/SdYxPoeev+1ax6JqEBU/QyvFGKUtSnCfx1VOHDDJWkNDdHZzr/M1IcYbhksEg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709602769; c=relaxed/simple; bh=qeCD6/ETW06FwabC2wz//U7xIkJ48O/wljaDDpL2SfQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aldKSf2sK+2sOVgoMQrugiTxy0FUAC9UhfXVhcF44Qtt7E5Ijn87lt3/42ekXDn01LqM7SE7zHZryGsnqamaLntUT1We2hGVkmeUY0NS0s7izccQgH9lZVHs5vY/7zGUTV9+Sf5XLiRVAmOyVbfB9CI9ZOu0CMfP5maFCDWMULo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iiSSegQ3; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iiSSegQ3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709602768; x=1741138768; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qeCD6/ETW06FwabC2wz//U7xIkJ48O/wljaDDpL2SfQ=; b=iiSSegQ38XaDAGpKxDKyBaBRdKyC3/hoD/74pzDIkcNXizPWNYUtxLFq 8AjCtvrmUXQYvGNY3mlqMkBlUQFHWJ8XZkPQofeO6mp/OIBZsT4fXK9gi j0xKccP0VmNtWtwyCWPTIOz0h94u148BgJyyCNtmjDtw9khIHRrfA05Cu vP0SBClr4cw0GUIiGbRbU7IZ4tYVlhfZaryj+qJki49F7yg8O1pCdOl4q RvocPsfj1zmB9FvICgKdsrgkNQkN5QWuX8epu7tt83EC5SP+G49YCiBAD 81kfPDKAvwOVrpKxD1VpuWBqQUF/FUGVJkjCK+sOEnF+TflRWoOXibr3A A==; X-IronPort-AV: E=McAfee;i="6600,9927,11003"; a="4286725" X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="4286725" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 17:39:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="13865494" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa004.jf.intel.com with ESMTP; 04 Mar 2024 17:39:25 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Eric Badger Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 4/5] iommu/vt-d: Remove scalable mode context entry setup from attach_dev Date: Tue, 5 Mar 2024 09:33:04 +0800 Message-Id: <20240305013305.204605-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240305013305.204605-1-baolu.lu@linux.intel.com> References: <20240305013305.204605-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The scalable mode context entry is now setup in the probe_device path, eliminating the need to configure it in the attach_dev path. Removes the redundant code from the attach_dev path to avoid dead code. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 156 ++++++++++-------------------------- 1 file changed, 44 insertions(+), 112 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 9b96d36b9d2a..d682eb6ad4d2 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1850,34 +1850,17 @@ static void domain_exit(struct dmar_domain *domain) kfree(domain); } =20 -/* - * Get the PASID directory size for scalable mode context entry. - * Value of X in the PDTS field of a scalable mode context entry - * indicates PASID directory with 2^(X + 7) entries. - */ -static unsigned long context_get_sm_pds(struct pasid_table *table) -{ - unsigned long pds, max_pde; - - max_pde =3D table->max_pasid >> PASID_PDE_SHIFT; - pds =3D find_first_bit(&max_pde, MAX_NR_PASID_BITS); - if (pds < 7) - return 0; - - return pds - 7; -} - static int domain_context_mapping_one(struct dmar_domain *domain, struct intel_iommu *iommu, - struct pasid_table *table, u8 bus, u8 devfn) { struct device_domain_info *info =3D domain_lookup_dev_info(domain, iommu, bus, devfn); u16 did =3D domain_id_iommu(domain, iommu); int translation =3D CONTEXT_TT_MULTI_LEVEL; + struct dma_pte *pgd =3D domain->pgd; struct context_entry *context; - int ret; + int agaw, ret; =20 if (hw_pass_through && domain_type_is_si(domain)) translation =3D CONTEXT_TT_PASS_THROUGH; @@ -1920,65 +1903,37 @@ static int domain_context_mapping_one(struct dmar_d= omain *domain, } =20 context_clear_entry(context); + context_set_domain_id(context, did); =20 - if (sm_supported(iommu)) { - unsigned long pds; - - /* Setup the PASID DIR pointer: */ - pds =3D context_get_sm_pds(table); - context->lo =3D (u64)virt_to_phys(table->table) | - context_pdts(pds); - - /* Setup the RID_PASID field: */ - context_set_sm_rid2pasid(context, IOMMU_NO_PASID); - + if (translation !=3D CONTEXT_TT_PASS_THROUGH) { /* - * Setup the Device-TLB enable bit and Page request - * Enable bit: + * Skip top levels of page tables for iommu which has + * less agaw than default. Unnecessary for PT mode. */ + for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { + ret =3D -ENOMEM; + pgd =3D phys_to_virt(dma_pte_addr(pgd)); + if (!dma_pte_present(pgd)) + goto out_unlock; + } + if (info && info->ats_supported) - context_set_sm_dte(context); - if (info && info->pri_supported) - context_set_sm_pre(context); - if (info && info->pasid_supported) - context_set_pasid(context); + translation =3D CONTEXT_TT_DEV_IOTLB; + else + translation =3D CONTEXT_TT_MULTI_LEVEL; + + context_set_address_root(context, virt_to_phys(pgd)); + context_set_address_width(context, agaw); } else { - struct dma_pte *pgd =3D domain->pgd; - int agaw; - - context_set_domain_id(context, did); - - if (translation !=3D CONTEXT_TT_PASS_THROUGH) { - /* - * Skip top levels of page tables for iommu which has - * less agaw than default. Unnecessary for PT mode. - */ - for (agaw =3D domain->agaw; agaw > iommu->agaw; agaw--) { - ret =3D -ENOMEM; - pgd =3D phys_to_virt(dma_pte_addr(pgd)); - if (!dma_pte_present(pgd)) - goto out_unlock; - } - - if (info && info->ats_supported) - translation =3D CONTEXT_TT_DEV_IOTLB; - else - translation =3D CONTEXT_TT_MULTI_LEVEL; - - context_set_address_root(context, virt_to_phys(pgd)); - context_set_address_width(context, agaw); - } else { - /* - * In pass through mode, AW must be programmed to - * indicate the largest AGAW value supported by - * hardware. And ASR is ignored by hardware. - */ - context_set_address_width(context, iommu->msagaw); - } - - context_set_translation_type(context, translation); + /* + * In pass through mode, AW must be programmed to + * indicate the largest AGAW value supported by + * hardware. And ASR is ignored by hardware. + */ + context_set_address_width(context, iommu->msagaw); } =20 + context_set_translation_type(context, translation); context_set_fault_enable(context); context_set_present(context); if (!ecap_coherent(iommu->ecap)) @@ -2008,43 +1963,29 @@ static int domain_context_mapping_one(struct dmar_d= omain *domain, return ret; } =20 -struct domain_context_mapping_data { - struct dmar_domain *domain; - struct intel_iommu *iommu; - struct pasid_table *table; -}; - static int domain_context_mapping_cb(struct pci_dev *pdev, u16 alias, void *opaque) { - struct domain_context_mapping_data *data =3D opaque; + struct device_domain_info *info =3D dev_iommu_priv_get(&pdev->dev); + struct intel_iommu *iommu =3D info->iommu; + struct dmar_domain *domain =3D opaque; =20 - return domain_context_mapping_one(data->domain, data->iommu, - data->table, PCI_BUS_NUM(alias), - alias & 0xff); + return domain_context_mapping_one(domain, iommu, + PCI_BUS_NUM(alias), alias & 0xff); } =20 static int domain_context_mapping(struct dmar_domain *domain, struct device *dev) { struct device_domain_info *info =3D dev_iommu_priv_get(dev); - struct domain_context_mapping_data data; struct intel_iommu *iommu =3D info->iommu; u8 bus =3D info->bus, devfn =3D info->devfn; - struct pasid_table *table; - - table =3D intel_pasid_get_table(dev); =20 if (!dev_is_pci(dev)) - return domain_context_mapping_one(domain, iommu, table, - bus, devfn); - - data.domain =3D domain; - data.iommu =3D iommu; - data.table =3D table; + return domain_context_mapping_one(domain, iommu, bus, devfn); =20 return pci_for_each_dma_alias(to_pci_dev(dev), - &domain_context_mapping_cb, &data); + domain_context_mapping_cb, domain); } =20 /* Returns a number of VTD pages, but aligned to MM page size */ @@ -2404,28 +2345,19 @@ static int dmar_domain_attach_device(struct dmar_do= main *domain, list_add(&info->link, &domain->devices); spin_unlock_irqrestore(&domain->lock, flags); =20 - /* PASID table is mandatory for a PCI device in scalable mode. */ - if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) { - /* Setup the PASID entry for requests without PASID: */ - if (hw_pass_through && domain_type_is_si(domain)) - ret =3D intel_pasid_setup_pass_through(iommu, - dev, IOMMU_NO_PASID); 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X-IronPort-AV: E=McAfee;i="6600,9927,11003"; a="4286734" X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="4286734" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 17:39:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="13865517" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa004.jf.intel.com with ESMTP; 04 Mar 2024 17:39:28 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Eric Badger Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v3 5/5] iommu/vt-d: Remove scalabe mode in domain_context_clear_one() Date: Tue, 5 Mar 2024 09:33:05 +0800 Message-Id: <20240305013305.204605-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240305013305.204605-1-baolu.lu@linux.intel.com> References: <20240305013305.204605-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" domain_context_clear_one() only handles the context entry teardown in legacy mode. Remove the scalable mode check in it to avoid dead code. Remove an unnecessary check in the code as well. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian --- drivers/iommu/intel/iommu.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index d682eb6ad4d2..50eb9aed47cc 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2175,9 +2175,6 @@ static void domain_context_clear_one(struct device_do= main_info *info, u8 bus, u8 struct context_entry *context; u16 did_old; =20 - if (!iommu) - return; - spin_lock(&iommu->lock); context =3D iommu_context_addr(iommu, bus, devfn, 0); if (!context) { @@ -2185,14 +2182,7 @@ static void domain_context_clear_one(struct device_d= omain_info *info, u8 bus, u8 return; } =20 - if (sm_supported(iommu)) { - if (hw_pass_through && domain_type_is_si(info->domain)) - did_old =3D FLPT_DEFAULT_DID; - else - did_old =3D domain_id_iommu(info->domain, iommu); - } else { - did_old =3D context_domain_id(context); - } + did_old =3D context_domain_id(context); =20 context_clear_entry(context); __iommu_flush_cache(iommu, context, sizeof(*context)); @@ -2203,9 +2193,6 @@ static void domain_context_clear_one(struct device_do= main_info *info, u8 bus, u8 DMA_CCMD_MASK_NOBIT, DMA_CCMD_DEVICE_INVL); =20 - if (sm_supported(iommu)) - qi_flush_pasid_cache(iommu, did_old, QI_PC_ALL_PASIDS, 0); - iommu->flush.flush_iotlb(iommu, did_old, 0, --=20 2.34.1