From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77FB422EE9; Mon, 4 Mar 2024 10:12:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547142; cv=none; b=RVM93YiZM6nrLCpKvR5rrNGyziYXXLgphI8fr/rsn46Si2dGLUvd1bef4WRjttKxQIudBfgoW8Ez9qjgo3nGbMO302rBqRB7NonIgWbizARjsdo9Tjr3SnPn8YVG0KK6qyP1x51vxZ5RSnKaarezav0id/JKGZJW71HaUTOpOh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547142; c=relaxed/simple; bh=OxIB2NND+GwRKTASD5QCovsMnnYYsMqrQtarqse8fjU=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=bb7O70rEBqO8qfX1ZDFjjD9Kl+dP3bpVI4SbaWW2Tc5Jn8jQnV0m05d1dvOlHq/ixvjPcDymyWyLcu/RxjFX9M0aAAa5lnXexDBP1VUETaYlLL4aHkZds4NnjrmU8TnNmKr5xMltKN1Vg3tRueokvo7w+5w27FyKT0RiZ79ZoGI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=18molGr0; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=I6Cd0G1o; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="18molGr0"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="I6Cd0G1o" Message-ID: <20240304005104.394845326@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547138; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=A3vlMqUJEQqqd54jjPrJxoXmY2AzGd+lvLwJqkXi5u0=; b=18molGr0u2BdjPyrVtj4EuzPZ8saG92VRtLosWyHKUqN7RTwSdyYxCOOHA3hBR65Z+9cua UGyGPSikf5PBTaggGn+HQgBChxqSxdFHlUNxcRK/PLssQ6TQG00Ljw66g7ZGAOo+kBz+jL +1GQOPDYzzl9QZVcqQ0SeLH/BefvdPSnYGmhuA5/EENb52l5WowQjMujAnzDenn58GaSAb /YT5yR2CDCRhy/dXWWA86DApqPso8offxSEcXNsAYJldO3H6XJ8BtDCBiMT8o3ZrsO/eny Z+0ZnFS8BlwRFjn0PDFfqfqMurvNEDu2li3R1/oIrEVuM22K+j5Lhn3Rdmr6gA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547138; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=A3vlMqUJEQqqd54jjPrJxoXmY2AzGd+lvLwJqkXi5u0=; b=I6Cd0G1o/AZmLzVbcS4rLiO8uXc1CRKi91dtqC2ynHYdFBQ9uWYdR0ijlQBFFCXge/9w3S r5PNP10WdNkansAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 1/9] perf/x86/amd/uncore: Fix __percpu annotation References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:18 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The __percpu annotation in struct amd_uncore is confusing sparse: uncore.c:649:10: sparse: warning: incorrect type in initializer (different = address spaces) uncore.c:649:10: sparse: expected void const [noderef] __percpu *__vpp_v= erify uncore.c:649:10: sparse: got union amd_uncore_info * The reason is that the __percpu annotation sits between the '*' dereferencing operator and the member name. Move it before the dereferencing operator to cure this. Signed-off-by: Thomas Gleixner --- arch/x86/events/amd/uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -71,7 +71,7 @@ union amd_uncore_info { }; =20 struct amd_uncore { - union amd_uncore_info * __percpu info; + union amd_uncore_info __percpu *info; struct amd_uncore_pmu *pmus; unsigned int num_pmus; bool init_done; From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78F8A22EEF; Mon, 4 Mar 2024 10:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547143; cv=none; b=oayFqG/4p0hitIE2V/lHnV2oE9jk1QUjqK+fGmJUd6MdeUkL8y+gMJUs0q5zGrWMB9qFBf/oadNo89gpBEF91CSGOCCeGISnmML49Hw4Fah5frlDquJSmcZ3MLQmzMDXCZ3zPHIq+9vBOgzbLctp4kCUftIuifN4VtqopmZzz3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547143; c=relaxed/simple; bh=oe6F4lKWB++RV3X/5FOu3DsK+9122S04xUjZlqb7KBk=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=tE53gvllkDKZUkJrFSvmpLQUPsflMSM8qHgDhaOaEq+XrkyMaHDCEdMo2rG4jEWKhIeIrDNoTf9ccSb6FkoCcUXP1VkNW5fy7YkyUzPeAe2Gb7YW9BdTwUHBXrEow3e4l4Y/ALJgmEcv9dNCs8SKCP96iyGt2LlqD+9WvUoGlx0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=T/53tueK; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/WAp4UrI; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="T/53tueK"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/WAp4UrI" Message-ID: <20240304005104.454678686@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547139; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JjiiERu9azu6SWbDWr4pKpCYy2SlURHt/nrJBAl1h1Y=; b=T/53tueKe10l1d+k71sAf8TP1Hj98kgPukmmg7e9npKY0SbnwTXurPJEINjp3sop4ispQH zRXHcPzn5+l8Q6vSmRvB5AUr8lymIZZ1EwmHaHyZpK8Iky5opS49s7GjFQnh/e5QoXkZGr +8Bf8hirsVGHAo3f9B05aQ/mFhm4jIiSQrySYEkYhMWjFFCQxYMIt3qpHOGjqkl0cuO2jj pvrg62BavUrUEY9h/DaMjk5dDmyQ2dL2dAFA0AO2weYA4kLtRic6c5IC8j6ndW0Hde2qvP oc00Gvk860ZFz9HWijHppw3Gw01z7LoZfKTIoGYyRGHa3KQQ4jwW7wP3ZpH1+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547139; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JjiiERu9azu6SWbDWr4pKpCYy2SlURHt/nrJBAl1h1Y=; b=/WAp4UrICNOMuK6YuFiovxtgIq4qvrMbHE2iTwY9A85zUpHj8F9CFJpKKWXB1n29tO4ORy ovTj+gEjKENOOCCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 2/9] x86/msr: Prepare for including percpu.h References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:19 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To cleanup the per CPU insanity of UP which causes sparse to be rightfully unhappy and prevents the usage of the generic per cpu accessors on cpu_info it is necessary to include linux/percpu.h into asm/msr.h. Including percpu.h into msr.h is impossible because it ends up in header dependency hell. The problem is that processor.h includes msr.h. The inclusion of percpu.h results in a compile fail where the compiler cannot longer handle an include in cpufeature.h which references boot_cpu_data which is defined in processor.h The only reason why msr.h is included in processor.h are the set/get_debugctlmsr() inlines. They are defined there because processor.h is such a nice dump ground for everything. In fact they belong obviously into debugreg.h. Move them to debugreg.h and fixup the resulting damage which is just exposing the reliance on random include chains. Signed-off-by: Thomas Gleixner --- arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 1 + arch/x86/include/asm/debugreg.h | 24 ++++++++++++++++++++++++ arch/x86/include/asm/fsgsbase.h | 2 +- arch/x86/include/asm/processor.h | 22 ---------------------- arch/x86/include/asm/special_insns.h | 4 ++-- arch/x86/kernel/cpu/intel_pconfig.c | 2 ++ arch/x86/kernel/cpu/rdrand.c | 1 + arch/x86/kernel/fpu/bugs.c | 2 ++ arch/x86/kernel/step.c | 2 ++ 10 files changed, 36 insertions(+), 25 deletions(-) --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include #include --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -5,6 +5,7 @@ #include =20 #include +#include #include #include #include --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -5,7 +5,9 @@ #include #include #include + #include +#include =20 DECLARE_PER_CPU(unsigned long, cpu_dr7); =20 @@ -159,4 +161,26 @@ static inline unsigned long amd_get_dr_a } #endif =20 +static inline unsigned long get_debugctlmsr(void) +{ + unsigned long debugctlmsr =3D 0; + +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return 0; +#endif + rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); + + return debugctlmsr; +} + +static inline void update_debugctlmsr(unsigned long debugctlmsr) +{ +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return; +#endif + wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); +} + #endif /* _ASM_X86_DEBUGREG_H */ --- a/arch/x86/include/asm/fsgsbase.h +++ b/arch/x86/include/asm/fsgsbase.h @@ -6,7 +6,7 @@ =20 #ifdef CONFIG_X86_64 =20 -#include +#include =20 /* * Read/write a task's FSBASE or GSBASE. This returns the value that --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -578,28 +578,6 @@ extern void cpu_init(void); extern void cpu_init_exception_handling(void); extern void cr4_init(void); =20 -static inline unsigned long get_debugctlmsr(void) -{ - unsigned long debugctlmsr =3D 0; - -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return 0; -#endif - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); - - return debugctlmsr; -} - -static inline void update_debugctlmsr(unsigned long debugctlmsr) -{ -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return; -#endif - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); -} - extern void set_task_blockstep(struct task_struct *task, bool on); =20 /* Boot loader type from the setup header: */ --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -2,11 +2,11 @@ #ifndef _ASM_X86_SPECIAL_INSNS_H #define _ASM_X86_SPECIAL_INSNS_H =20 - #ifdef __KERNEL__ - #include #include + +#include #include #include =20 --- a/arch/x86/kernel/cpu/intel_pconfig.c +++ b/arch/x86/kernel/cpu/intel_pconfig.c @@ -7,6 +7,8 @@ * Author: * Kirill A. Shutemov */ +#include +#include =20 #include #include --- a/arch/x86/kernel/cpu/rdrand.c +++ b/arch/x86/kernel/cpu/rdrand.c @@ -6,6 +6,7 @@ * Authors: Fenghua Yu , * H. Peter Anvin */ +#include =20 #include #include --- a/arch/x86/kernel/fpu/bugs.c +++ b/arch/x86/kernel/fpu/bugs.c @@ -2,6 +2,8 @@ /* * x86 FPU bug checks: */ +#include + #include #include =20 --- a/arch/x86/kernel/step.c +++ b/arch/x86/kernel/step.c @@ -6,7 +6,9 @@ #include #include #include + #include +#include #include =20 unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_re= gs *regs) From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7A6B3984B; Mon, 4 Mar 2024 10:12:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547144; cv=none; b=YTPi9jpS7JUzoHYjkFMUv22q823RwmrQxa7YuKXPeDGtAs+Jtzl0xfZ3NE8w3oyTKpGoFN8Rqhrv9w7EOkmlCMGsa4AMBAbA0EiAYuHOoXubjr22VCHnQ489D7w98K1W+VGwDnvPkl9zJC/iS2wUBLAPGqRW14fp29d6kgJ+0Vc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547144; c=relaxed/simple; bh=Xy2u0bRDImKld1wcyjYDGiVnq2irYEy02BmpMI3Gm/Q=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=l7bX761oN/iIVR4BIP9EImAE1rvwNkdUXmAZCQPX5orayWIe+tORDDHzPckmser8HBBy1D1isG/4fdjHoqxMg/w5a/cJ6uyFcIGqP/604+weIgD7fk23Mcl3oqN5LbBXdRHM+thnWKYgyN3sH0dEYZB1EuJqkuq0jPHW+6K58Ts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EerkCNw2; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=v992CpVd; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EerkCNw2"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="v992CpVd" Message-ID: <20240304005104.513181735@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547141; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RyGbWjTAxec6UVxBRQI4/who5kTeC4Qetv+7IpOA3/s=; b=EerkCNw2EwZUT050o6pD4jnPrRjHC0dtfkfhEJXshTi9754LlALEgL5ozins3+nZDYVXTE FVLnPMvBc7RjABDX20HQhDmSerXxDtyIGzj7vjIGuyQlJ04NgkAFV6MZp+e50vMFOuApx4 MLMqO4KQDoI24+J9RHw7P/0RRGGpvNG+ACxd6Bd0H4gwlcVKY2YqpjLkILIR3b4lbnGx3Q San6m7VeZOrFkPMLxfva4SuepYtthCTHL0X8fAGlI4F91oHsax7vsLp6KyKVmkSaGseYwG bSrsavRUUdm59sW8xTYGQLtAioAquQ0TfrwRYJZ+3ajzCyYtWL5CktwjAdWmhQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547141; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RyGbWjTAxec6UVxBRQI4/who5kTeC4Qetv+7IpOA3/s=; b=v992CpVd3cXVfweVPzJzcgmEsgJL48gP4m7p7DFZ5TdrFRRueI+GubKaP/CBnKfBOC9AX5 bl5+WhvPg9fdW2Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 3/9] x86/msr: Add missing __percpu annotations References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:20 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sparse complains rightfully about using a plain pointer for per CPU accessors: msr-smp.c:15:23: sparse: warning: incorrect type in initializer (different = address spaces) msr-smp.c:15:23: sparse: expected void const [noderef] __percpu *__vpp_v= erify msr-smp.c:15:23: sparse: got struct msr * Add __percpu annotations to the related datastructure and function arguments to cure this. This also cures the related sparse warnings at the callsites in drivers/edac/amd64_edac.c. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/msr.h | 26 ++++++++++++++------------ arch/x86/include/asm/processor.h | 1 - arch/x86/include/asm/tsc.h | 3 ++- arch/x86/lib/msr-smp.c | 12 +++++------- arch/x86/lib/msr.c | 6 +++--- 5 files changed, 24 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -12,11 +12,13 @@ #include #include =20 +#include + struct msr_info { - u32 msr_no; - struct msr reg; - struct msr *msrs; - int err; + u32 msr_no; + struct msr reg; + struct msr __percpu *msrs; + int err; }; =20 struct msr_regs_info { @@ -323,8 +325,8 @@ static inline int wrmsrl_safe(u32 msr, u return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); } =20 -struct msr *msrs_alloc(void); -void msrs_free(struct msr *msrs); +struct msr __percpu *msrs_alloc(void); +void msrs_free(struct msr __percpu *msrs); int msr_set_bit(u32 msr, u8 bit); int msr_clear_bit(u32 msr, u8 bit); =20 @@ -333,8 +335,8 @@ int rdmsr_on_cpu(unsigned int cpu, u32 m int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); -void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msr= s); -void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msr= s); +void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); +void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); @@ -363,14 +365,14 @@ static inline int wrmsrl_on_cpu(unsigned return 0; } static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, - struct msr *msrs) + struct msr __percpu *msrs) { - rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); + rdmsr_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->l), raw_cpu_ptr(&msrs->h)); } static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, - struct msr *msrs) + struct msr __percpu *msrs) { - wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); + wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->l), raw_cpu_read(msrs->h)); } static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -20,7 +20,6 @@ struct vm86; #include #include #include -#include #include #include #include --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -5,8 +5,9 @@ #ifndef _ASM_X86_TSC_H #define _ASM_X86_TSC_H =20 -#include #include +#include +#include =20 /* * Standard way to access the cycle counter. --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -9,10 +9,9 @@ static void __rdmsr_on_cpu(void *info) { struct msr_info *rv =3D info; struct msr *reg; - int this_cpu =3D raw_smp_processor_id(); =20 if (rv->msrs) - reg =3D per_cpu_ptr(rv->msrs, this_cpu); + reg =3D this_cpu_ptr(rv->msrs); else reg =3D &rv->reg; =20 @@ -23,10 +22,9 @@ static void __wrmsr_on_cpu(void *info) { struct msr_info *rv =3D info; struct msr *reg; - int this_cpu =3D raw_smp_processor_id(); =20 if (rv->msrs) - reg =3D per_cpu_ptr(rv->msrs, this_cpu); + reg =3D this_cpu_ptr(rv->msrs); else reg =3D &rv->reg; =20 @@ -97,7 +95,7 @@ int wrmsrl_on_cpu(unsigned int cpu, u32 EXPORT_SYMBOL(wrmsrl_on_cpu); =20 static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no, - struct msr *msrs, + struct msr __percpu *msrs, void (*msr_func) (void *info)) { struct msr_info rv; @@ -124,7 +122,7 @@ static void __rwmsr_on_cpus(const struct * @msrs: array of MSR values * */ -void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msr= s) +void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs) { __rwmsr_on_cpus(mask, msr_no, msrs, __rdmsr_on_cpu); } @@ -138,7 +136,7 @@ EXPORT_SYMBOL(rdmsr_on_cpus); * @msrs: array of MSR values * */ -void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msr= s) +void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __pe= rcpu *msrs) { __rwmsr_on_cpus(mask, msr_no, msrs, __wrmsr_on_cpu); } --- a/arch/x86/lib/msr.c +++ b/arch/x86/lib/msr.c @@ -6,9 +6,9 @@ #define CREATE_TRACE_POINTS #include =20 -struct msr *msrs_alloc(void) +struct msr __percpu *msrs_alloc(void) { - struct msr *msrs =3D NULL; + struct msr __percpu *msrs =3D NULL; =20 msrs =3D alloc_percpu(struct msr); if (!msrs) { @@ -20,7 +20,7 @@ struct msr *msrs_alloc(void) } EXPORT_SYMBOL(msrs_alloc); =20 -void msrs_free(struct msr *msrs) +void msrs_free(struct msr __percpu *msrs) { free_percpu(msrs); } From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1605439AE1; Mon, 4 Mar 2024 10:12:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547145; cv=none; b=i4jOh2E2Cz8G9JxUHMqOU7rEFV8pJ4o2TlCwmRw9YRopIGqWdAAN5r2l19eFjAj9oPoOp2d0DM6o5aQpavl8A/CiS9rT04N4IsUIaxbCUQCYD/ElUpS1ngvwyr1syDh/SgjTA98jVJVC8xfk8mDk0EleCblxTLN0rbnem0VREOI= ARC-Message-Signature: i=1; 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bh=oaBlEsAnKVJlhuCSShod/Mz5x/UHGwu5Y/M9GU3TTqY=; b=gm6AaC648uSUhApkGjnoS+zQ5LiSzriiW9rugLnsQm+58Dgp/rElOwOUUrCPOY2ELxclZn JQrQJkdcZMOh+oCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 4/9] smp: Consolidate smp_prepare_boot_cpu() References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:22 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no point in having seven architectures implementing the same empty stub. Provide a weak function in the init code and remove the stubs. This also allows to utilize the function on UP which is required to sanitize the percpu handling on X86 UP. Signed-off-by: Thomas Gleixner --- arch/alpha/kernel/smp.c | 5 ----- arch/arc/kernel/smp.c | 5 ----- arch/csky/kernel/smp.c | 4 ---- arch/hexagon/kernel/smp.c | 4 ---- arch/openrisc/kernel/smp.c | 4 ---- arch/riscv/kernel/smpboot.c | 4 ---- arch/sparc/kernel/smp_64.c | 4 ---- arch/x86/include/asm/smp.h | 5 ----- arch/x86/kernel/smpboot.c | 5 +++++ include/linux/smp.h | 13 ++++++------- init/main.c | 4 ++++ 11 files changed, 15 insertions(+), 42 deletions(-) --- a/arch/alpha/kernel/smp.c +++ b/arch/alpha/kernel/smp.c @@ -467,11 +467,6 @@ smp_prepare_cpus(unsigned int max_cpus) smp_num_cpus =3D smp_num_probed; } =20 -void -smp_prepare_boot_cpu(void) -{ -} - int __cpu_up(unsigned int cpu, struct task_struct *tidle) { --- a/arch/arc/kernel/smp.c +++ b/arch/arc/kernel/smp.c @@ -39,11 +39,6 @@ struct plat_smp_ops __weak plat_smp_ops /* XXX: per cpu ? Only needed once in early secondary boot */ struct task_struct *secondary_idle_tsk; =20 -/* Called from start_kernel */ -void __init smp_prepare_boot_cpu(void) -{ -} - static int __init arc_get_cpu_map(const char *name, struct cpumask *cpumas= k) { unsigned long dt_root =3D of_get_flat_dt_root(); --- a/arch/csky/kernel/smp.c +++ b/arch/csky/kernel/smp.c @@ -152,10 +152,6 @@ void arch_irq_work_raise(void) } #endif =20 -void __init smp_prepare_boot_cpu(void) -{ -} - void __init smp_prepare_cpus(unsigned int max_cpus) { } --- a/arch/hexagon/kernel/smp.c +++ b/arch/hexagon/kernel/smp.c @@ -114,10 +114,6 @@ void send_ipi(const struct cpumask *cpum local_irq_restore(flags); } =20 -void __init smp_prepare_boot_cpu(void) -{ -} - /* * interrupts should already be disabled from the VM * SP should already be correct; need to set THREADINFO_REG --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -57,10 +57,6 @@ static void boot_secondary(unsigned int spin_unlock(&boot_lock); } =20 -void __init smp_prepare_boot_cpu(void) -{ -} - void __init smp_init_cpus(void) { struct device_node *cpu; --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -42,10 +42,6 @@ =20 static DECLARE_COMPLETION(cpu_running); =20 -void __init smp_prepare_boot_cpu(void) -{ -} - void __init smp_prepare_cpus(unsigned int max_cpus) { int cpuid; --- a/arch/sparc/kernel/smp_64.c +++ b/arch/sparc/kernel/smp_64.c @@ -1206,10 +1206,6 @@ void __init smp_prepare_cpus(unsigned in { } =20 -void smp_prepare_boot_cpu(void) -{ -} - void __init smp_setup_processor_id(void) { if (tlb_type =3D=3D spitfire) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -59,11 +59,6 @@ static inline void stop_other_cpus(void) smp_ops.stop_other_cpus(1); } =20 -static inline void smp_prepare_boot_cpu(void) -{ - smp_ops.smp_prepare_boot_cpu(); -} - static inline void smp_prepare_cpus(unsigned int max_cpus) { smp_ops.smp_prepare_cpus(max_cpus); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1187,6 +1187,11 @@ void __init smp_prepare_cpus_common(void set_cpu_sibling_map(0); } =20 +void __init smp_prepare_boot_cpu(void) +{ + smp_ops.smp_prepare_boot_cpu(); +} + #ifdef CONFIG_X86_64 /* Establish whether parallel bringup can be supported. */ bool __init arch_cpuhp_init_parallel_bringup(void) --- a/include/linux/smp.h +++ b/include/linux/smp.h @@ -105,6 +105,12 @@ static inline void on_each_cpu_cond(smp_ on_each_cpu_cond_mask(cond_func, func, info, wait, cpu_online_mask); } =20 +/* + * Architecture specific boot CPU setup. Defined as empty weak function in + * init/main.c. Architectures can override it. + */ +void smp_prepare_boot_cpu(void); + #ifdef CONFIG_SMP =20 #include @@ -171,12 +177,6 @@ void generic_smp_call_function_single_in #define generic_smp_call_function_interrupt \ generic_smp_call_function_single_interrupt =20 -/* - * Mark the boot cpu "online" so that it can call console drivers in - * printk() and can access its per-cpu storage. - */ -void smp_prepare_boot_cpu(void); - extern unsigned int setup_max_cpus; extern void __init setup_nr_cpu_ids(void); extern void __init smp_init(void); @@ -203,7 +203,6 @@ static inline void up_smp_call_function( (up_smp_call_function(func, info)) =20 static inline void smp_send_reschedule(int cpu) { } -#define smp_prepare_boot_cpu() do {} while (0) #define smp_call_function_many(mask, func, info, wait) \ (up_smp_call_function(func, info)) static inline void call_function_init(void) { } --- a/init/main.c +++ b/init/main.c @@ -776,6 +776,10 @@ void __init __weak smp_setup_processor_i { } =20 +void __init __weak smp_prepare_boot_cpu(void) +{ +} + # if THREAD_SIZE >=3D PAGE_SIZE void __init __weak thread_stack_cache_init(void) { From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA8053A1B5; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547144; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=waWca13nkXlTk1KdzjjO2eUHwkXJkPInhR1X09TJX+0=; b=DybwRAzaUVoj3GiTZNCzx4w9/5h1J6i6awKRx6ALpGlnYu7RBOoHK+EpiWo6GAfyzSUvKj 08Qabz6R7eWQ3kBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 5/9] x86: Cure per CPU madness on UP References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:23 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On UP builds sparse complains rightfully about accesses to cpu_info with per CPU accessors: cacheinfo.c:282:30: sparse: warning: incorrect type in initializer (differe= nt address spaces) cacheinfo.c:282:30: sparse: expected void const [noderef] __percpu *__vp= p_verify cacheinfo.c:282:30: sparse: got unsigned int * The reason is that on UP builds cpu_info which is a per CPU variable on SMP is mapped to boot_cpu_info which is a regular variable. There is a hideous accessor cpu_data() which tries to hide this, but it's not sufficient as some places require raw accessors and generates worse code than the regular per CPU accessors. Waste sizeof(struct x86_cpuinfo) memory on UP and provide the per CPU cpu_info unconditionally. This requires to update the CPU info on the boot CPU as SMP does. (Ab)use the weakly defined smp_prepare_boot_cpu() function and implement exactly that. This allows to use regular per CPU accessors uncoditionally and paves the way to remove the cpu_data() hackery. Signed-off-by: Thomas Gleixner Tested-by: Guenter Roeck --- arch/x86/include/asm/processor.h | 5 ----- arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kernel/setup.c | 10 ++++++++++ arch/x86/kernel/smpboot.c | 4 ---- 4 files changed, 13 insertions(+), 9 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -185,13 +185,8 @@ extern struct cpuinfo_x86 new_cpu_data; extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; =20 -#ifdef CONFIG_SMP DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); #define cpu_data(cpu) per_cpu(cpu_info, cpu) -#else -#define cpu_info boot_cpu_data -#define cpu_data(cpu) boot_cpu_data -#endif =20 extern const struct seq_operations cpuinfo_op; =20 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -70,6 +70,9 @@ =20 #include "cpu.h" =20 +DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); +EXPORT_PER_CPU_SYMBOL(cpu_info); + u32 elf_hwcap2 __read_mostly; =20 /* Number of siblings per CPU package */ --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1211,6 +1211,16 @@ void __init i386_reserve_resources(void) =20 #endif /* CONFIG_X86_32 */ =20 +#ifndef CONFIG_SMP +void __init smp_prepare_boot_cpu(void) +{ + struct cpuinfo_x86 *c =3D &cpu_data(0); + + *c =3D boot_cpu_data; + c->initialized =3D true; +} +#endif + static struct notifier_block kernel_offset_notifier =3D { .notifier_call =3D dump_kernel_offset }; --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -101,10 +101,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map); DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); EXPORT_PER_CPU_SYMBOL(cpu_die_map); =20 -/* Per CPU bogomips and other parameters */ -DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); -EXPORT_PER_CPU_SYMBOL(cpu_info); - /* CPUs which are the primary SMT threads */ struct cpumask __cpu_primary_thread_mask __read_mostly; From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A2F33B19E; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547145; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JtmrisRHZR6UF3WBSqph8+Mk5bBFqrMgy9HjBdcJVEk=; b=GXY72yH0oyMBAGlKJeAWMRCFXiwyVc/SK62N6NHJayvUlS1I76NnxOBgthWNkeAwjP7zd4 r4wIKfiIhaBciDDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 6/9] x86/uaccess: Add missing __force to casts in __access_ok() and valid_user_address() References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:25 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sparse complains about losing the __user address space due to the cast to long: uaccess_64.h:88:24: sparse: warning: cast removes address space '__user' of= expression Annotate it with __force to tell sparse that this is intentional. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/uaccess_64.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h @@ -54,7 +54,7 @@ static inline unsigned long __untagged_a * half and a user half. When cast to a signed type, user pointers * are positive and kernel pointers are negative. */ -#define valid_user_address(x) ((long)(x) >=3D 0) +#define valid_user_address(x) ((__force long)(x) >=3D 0) =20 /* * User pointers can have tag bits on x86-64. This scheme tolerates @@ -87,8 +87,9 @@ static inline bool __access_ok(const voi if (__builtin_constant_p(size <=3D PAGE_SIZE) && size <=3D PAGE_SIZE) { return valid_user_address(ptr); } else { - unsigned long sum =3D size + (unsigned long)ptr; - return valid_user_address(sum) && sum >=3D (unsigned long)ptr; + unsigned long sum =3D size + (__force unsigned long)ptr; + + return valid_user_address(sum) && sum >=3D (__force unsigned long)ptr; } } #define __access_ok __access_ok From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 847573BB2E; Mon, 4 Mar 2024 10:12:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547149; cv=none; b=WJu6yNKoEk2/WG2c0ZfAkLXqQ9JDmr6di5du361A29NwwPZ5E00TLAYxnvFDs5pcTcBza8TcQqlHECp+LuxaZo9vaQ/c0tbfgBaWbZ/etpFIQxmeG4zNzZlEdzu+jDP4fkbrY8tXa0f9BE3/EU2fVdSSn99FaOtuijhn195Qo7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547149; c=relaxed/simple; bh=OyN8YEdrBn8llpG2kEDC2mhfQ0B4aig3D3k4rEQFbBw=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=sq3v/Ht9BeTe92ecg0d6WFR/glyNdKvgVyJJagrhQbCuR4xrSX5FzIVFVFD4NqYNlHnouIGpcQUCFt+zvPdGfHAO5h8+bHGQl2A5xntTs3jCwVZK41ZtYNNL+SmkFytNgNTabW2iGRUy2JkvuCa9Pyc6ohmxDx/W26rktXhnrkU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oDT/Xu+F; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jzxjGBOY; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oDT/Xu+F"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jzxjGBOY" Message-ID: <20240304005104.732288812@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547147; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=P1puNPiaRZsJi3LvDbzvEOsTfk74hgQ7qSp99Hl7hDM=; b=oDT/Xu+FEWupD4WnJWzYsbwIgFGDT62w1IljV+6VhDRUEI0uFmkEdEZIwd/bz4ru5CAjxu EupYV6NbSQ1mGBHqZ+w30oZ8J+NOz9ZnEt1eLBaVFShhVvkO5NYeKnYaRunauESYbWvt43 QzIh4T3utgPwd1onET2WvD3uG/Frvyr/9hZ8QOKOcNe3x7EaTXLdhiKKKcQ+pOyd36cR0D jhxvobHod4bk4iU7x7YM2lJtM1hl0uXIlbZTvp8rvEtJaJjW44eMOLsBM36zq20QKFjhaa p2Kh9H1nsPAwDFtOPoD/cEj40U0uBHJRY+qoIYSlegmUgs0BKrZP+lnieV4MzA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547147; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=P1puNPiaRZsJi3LvDbzvEOsTfk74hgQ7qSp99Hl7hDM=; b=jzxjGBOYUFsGZ3hZFO+xR+Yl3T6Gy4lQJbVwQhe0DyXuo9xEy1rqaQWSf4Mktc1N5pUcAV fyQjBS9nqaBbzsDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 7/9] x86/cpu: Use EXPORT_PER_CPU_SYMBOL_GPL() for x86_spec_ctrl_current References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:26 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sparse rightfully complains: bugs.c:71:9: sparse: warning: incorrect type in initializer (different addr= ess spaces) bugs.c:71:9: sparse: expected void const [noderef] __percpu *__vpp_verify bugs.c:71:9: sparse: got unsigned long long * The reason is that x86_spec_ctrl_current which is a per CPU variable is exported with EXPORT_SYMBOL_GPL(). Use EXPORT_PER_CPU_SYMBOL_GPL() instead. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/bugs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -56,7 +56,7 @@ EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); =20 /* The current value of the SPEC_CTRL MSR with task-specific bits set */ DEFINE_PER_CPU(u64, x86_spec_ctrl_current); -EXPORT_SYMBOL_GPL(x86_spec_ctrl_current); +EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); =20 u64 x86_pred_cmd __ro_after_init =3D PRED_CMD_IBPB; EXPORT_SYMBOL_GPL(x86_pred_cmd); From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9CC53C087; Mon, 4 Mar 2024 10:12:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547151; cv=none; b=FFcSC3gQpa3js+0yrT9kSpacicZ8nvQ9sVe+waCzdl9PXGc0QL5wht0cjrN69NXsDX6y27zoX8khZxZZ2skuxFEFWman18ePOTxk7m+DJJx3IHYtruCvwYOvwMM0vzGax/fGF5pMX7sHYriDRO7HevHGKbhPpU1Xgs7z5QanjR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547151; c=relaxed/simple; bh=0nwFi0bkuZGiGtiI8Nsx6zeMClnjEJolxPelJmGOFdM=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=IaRpnAnzaTz4hMHTdrwgmYMf99MVy0xUZ9v+3pb37Ynu+LMIKmq6ZWOyCpffqhJL0HVmSBiiToKkZT3yXkBuAJZR2KbF+jv6GF448zZRyAKDXX4xaPxF7OpsT+UoED7un2adCz5J8pU9PnoFUbhBrblAGTp6Uosa43946PQ2gXM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NO8lSC7k; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=90m2Rl2o; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NO8lSC7k"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="90m2Rl2o" Message-ID: <20240304005104.787173239@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547148; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6Jgk9G7c0E4dzMxbvaTsjGPBA2bcPCPscX5bks01Uro=; b=NO8lSC7k+xuFTRyI7RDoRaIx57KuVWWkTdO69WoHfx1l4s6SvALgnsdiH23XFiV0Lku7FA dFs+/vfPDCaI0i1XKSKbxrncJHkGUG05L4tLpLOp6m+ZmZbTGgPCfhhZBBiF+bFA544pCJ Ife3C4CeGfrygHWbseJHDp0S/ETIf5JYa8SsWTqBXc7skRZPoSESnlEuD2kdgubT1R9EVT 6RYMVtbvOrj7448mWylKQrOXulwXNdxrP4LOE7RMFBBkhpZMVcm1Im0N0ll3765Z99m+h3 9z3xbVIDoOFuwpd4eNp0ZoYCgCoNyerplkqIAKvbbAcpY1A4F76T8u5cyx9Fvg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547148; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6Jgk9G7c0E4dzMxbvaTsjGPBA2bcPCPscX5bks01Uro=; b=90m2Rl2oJgJFtAWub/kQ/ti4ooEu+pBEJZ8iuepWmfQWR/jnE01Sl2VKRtNiOwEbOQEsbP MKVHn8eclKAYCPAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 8/9] x86/cpu: Provide a declaration for itlb_multihit_kvm_mitigation References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:28 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sparse complains rightfully about the missing declaration which has been placed sloppily into the usage site: bugs.c:2223:6: sparse: warning: symbol 'itlb_multihit_kvm_mitigation' was not declared. Should it be static? Add it to spec-ctrl.h where it belongs and remove the one in the kvm code. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/spec-ctrl.h | 2 ++ arch/x86/kvm/mmu/mmu.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h @@ -96,4 +96,6 @@ static inline void speculative_store_byp extern void speculation_ctrl_update(unsigned long tif); extern void speculation_ctrl_update_current(void); =20 +extern bool itlb_multihit_kvm_mitigation; + #endif --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -53,12 +53,11 @@ #include #include #include +#include #include =20 #include "trace.h" =20 -extern bool itlb_multihit_kvm_mitigation; - static bool nx_hugepage_mitigation_hard_disabled; =20 int __read_mostly nx_huge_pages =3D -1; From nobody Sun Feb 8 10:50:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2553C2556F; Mon, 4 Mar 2024 10:12:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547152; cv=none; b=riAruhF2j75jW8Bn9NrMr4DmZNFTWtkc6WDfmlnODHZBGIVnQXAmtW69ZoYPPMK1OsgyQBNoCVfzmD6yxe6jzh8u4ysc3ro/dw01Y5EC3gaUAahiAMg9oSzwGcIc9/QwClsQwAnv3LFBYOFelqKAIogNuF/i+ozgBRzhCd6PynA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709547152; c=relaxed/simple; bh=8Pg2EFDXUYjtz+tkcv/kg/YFmeskhKXf43DpJ0nXHlg=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=KZy83YTahKPQZbeY7QDs05v98+uCQpA0OeK/Hya2bN1F5OwLh9OprjDZ3YO1zQlP+K0c1Dujv9Wtt21wy4GwlXsFSS0Ib76zcPWvZR40OulxUubVM3kGPcJePKx2JuHLkmeYw8p4O8nbeWI+zrCFdoF/OfpLjgTBNvXsshMm6+Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oF47lkb4; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bC/zpfQn; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oF47lkb4"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bC/zpfQn" Message-ID: <20240304005104.841915535@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547149; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CNfpfUdf+bJ/WXlKRuxwbcf+mJAjRsom7OLtmfNUsUs=; b=oF47lkb4Rk/qvj8Db0DRNJP1DueeQS9kXvhHnhNzDRR8etK9qNQysmWn7gl1vnhJGoyRVU G3nly8CjbNeLALkuKp6qhtOlQd+IXybJsPeFN902wLcz/8bciN4T9Ts55RgXlE5yXECQ4P r0ndTbug4smvpyy4oBE5xvh0KjUTBclNR58/LW3vsJX66Po7iz+XKA54haE3NDtexiWtfE j/YvojK59blwLY6kn3bHJN7VVH/HW8RXyhm4kDQtDYTYj6yf8zCphUO2GgAQU5u39vfP7p BH3jv35bwdDorlupW8PDfesjvd9M9ky6L2OXWfJz+TUUtjJFZ1GURBq9K8kkRA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547149; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CNfpfUdf+bJ/WXlKRuxwbcf+mJAjRsom7OLtmfNUsUs=; b=bC/zpfQngeugmwtDkBFAMAJ1oOblN8I8e29J1a4Gq0IsYlUkp4Ep8z7A48ioHN+x2JjHE3 QcneLlx7+eISCTAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 9/9] x86/callthunks: Use EXPORT_PER_CPU_SYMBOL_GPL() for per CPU variables References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:29 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" sparse complains rightfully about the usage of EXPORT_SYMBOL_GPL() for per CPU variables: callthunks.c:346:20: sparse: warning: incorrect type in initializer (differ= ent address spaces) callthunks.c:346:20: sparse: expected void const [noderef] __percpu *__v= pp_verify callthunks.c:346:20: sparse: got unsigned long long * Use EXPORT_PER_CPU_SYMBOL_GPL instead. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/callthunks.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/callthunks.c +++ b/arch/x86/kernel/callthunks.c @@ -44,8 +44,8 @@ DEFINE_PER_CPU(u64, __x86_call_count); DEFINE_PER_CPU(u64, __x86_ret_count); DEFINE_PER_CPU(u64, __x86_stuffs_count); DEFINE_PER_CPU(u64, __x86_ctxsw_count); -EXPORT_SYMBOL_GPL(__x86_ctxsw_count); -EXPORT_SYMBOL_GPL(__x86_call_count); +EXPORT_PER_CPU_SYMBOL_GPL(__x86_ctxsw_count); +EXPORT_PER_CPU_SYMBOL_GPL(__x86_call_count); #endif =20 extern s32 __call_sites[], __call_sites_end[];