From nobody Fri Sep 20 01:30:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DC873A8D8 for ; Fri, 1 Mar 2024 14:44:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709304254; cv=none; b=DmnOw+NWtT/mCqV3ndS2oP+GNDYq1GkDynVpN85qj65UkyrytdylwPgWfPALt6HdeqnHwVIq43PpNLVs3Cr7D1Ms8QxwHUomNu2OZQFkkBiRIc7VysxOkhaia/vhPk6XFOEfhIGJNHiCqQLAQPwh7sVBXL+GlJ0DSME9UHEHN8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709304254; c=relaxed/simple; bh=u/qdQKxxHWxdR7mQ6yXNAv14RbtVmZcngF2KU/ZM66Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dXzwfkt/Yfj6UMdRXGbBI625nG4aqWAwd7jBIWuV35JgBCMzXeMmvldpDs0WW6bFzMV5ZI1HKoHdYE6oVr6fpYdnxpFNbSePzYFhyWroeMIZUEX3SCdXynAk1lIlOm9Fy1jH8Om1/mEi3oNGPsiPyRl4erJTczCsLLmGGF6JuiA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=soIjvjJ6; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="soIjvjJ6" X-UUID: 27947ccad7da11ee935d6952f98a51a9-20240301 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=iVlDUuKVmuA7JnvVmCn0d4WsSJI5tUjOae/sjyXi08c=; b=soIjvjJ66bjrsLIo9EriHpWPsAoonwwvPafWH09/xpPWB0Dy6r6sXmG7vTGsbVtZgogrQtBVwqT7gNZGmBrMkjrj4e96TyWJTCkIWkKUd6B811NrSgWEsd5S7IyVqv5+vm/fQ9zjN2BP14uKKqMiXCswf83NVfshhkgBsGnTaRY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:015bffb2-fdce-449a-ba64-d7da00ee4c05,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6f543d0,CLOUDID:352c66ff-c16b-4159-a099-3b9d0558e447,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 27947ccad7da11ee935d6952f98a51a9-20240301 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 194215741; Fri, 01 Mar 2024 22:44:06 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Mar 2024 22:44:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Mar 2024 22:44:04 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [RESEND, PATCH 1/5] soc: mediatek: mtk-cmdq: Add specific purpose register definitions for GCE Date: Fri, 1 Mar 2024 22:43:59 +0800 Message-ID: <20240301144403.2977-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240301144403.2977-1-jason-jh.lin@mediatek.com> References: <20240301144403.2977-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add specific purpose register definitions for GCE, so CMDQ users can use them as a buffer to store data. Signed-off-by: Jason-JH.Lin --- include/linux/soc/mediatek/mtk-cmdq.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index 649955d2cf5c..1dae80185f9f 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -14,6 +14,15 @@ #define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) #define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1)) =20 +/* + * Every cmdq thread has its own SPRs (Specific Purpose Registers), + * so there are 4 * N (threads) SPRs in GCE that shares the same indexes b= elow. + */ +#define CMDQ_THR_SPR_IDX0 (0) +#define CMDQ_THR_SPR_IDX1 (1) +#define CMDQ_THR_SPR_IDX2 (2) +#define CMDQ_THR_SPR_IDX3 (3) + struct cmdq_pkt; =20 struct cmdq_client_reg { --=20 2.18.0 From nobody Fri Sep 20 01:30:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FA9D3985A for ; Fri, 1 Mar 2024 14:44:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709304254; cv=none; b=O8OhKsZbN6WGk2EKPD7ImvmcQdaZ6z2SI/O8WCaPvFrKg/nZh9fs8M087nBeq0jKXeKxxomSealxQs+zSmRCLuK5ugaZWSiGr1JgcKmzZcTEL0d70Xpc7suMfPJIf42g+uFzwNLv3ZH6HRanCXNG3oxIlXwQ7cVQistrj1OWVtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709304254; c=relaxed/simple; bh=Akl9Bh+YJIiyMPc9g7WpxKAyGeUsUlx4vxBArfJWXXY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t6Q14+0Jlp/oAs+v8psHvj3tH5zItNDMSTsGVD/e2u5Aimz3wdE7w0dONtAHyumxH5g/hGb9den/vz40LzlnzkOCsf1Hp7L+PULXdGDRPoQ6B/hnGMdm34Y8CkGLncIBrnwNA591ntn8/NVEnKQovXW6NoiRtyfE2FRSLWnn1rA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=rfp3hl9i; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="rfp3hl9i" X-UUID: 27aecbc0d7da11eeb8927bc1f75efef4-20240301 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=b2jtfBQ99XTwNQWIlhNqeShiovjYiw2SHuwp+NS8xzo=; b=rfp3hl9iawLTDiftCT5bJCtp/CPmY6z9TDO+Sk0/Zgih5bvYS2Iacijqfvg/vGFJVr5QdmSf877IZGCxJPlQzcWPFKM2Z0VwJlXybb3C3/BTL++eFZsghgJcNh1eGsic7uQT67kfQxXazTFGeA2G8Nvnwl+lyLAvZ5JROcPCesg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:434e1981-6f7f-4a6c-bee0-8e548015b2d3,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6f543d0,CLOUDID:66370181-4f93-4875-95e7-8c66ea833d57,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 27aecbc0d7da11eeb8927bc1f75efef4-20240301 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 410278015; Fri, 01 Mar 2024 22:44:06 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Mar 2024 22:44:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Mar 2024 22:44:04 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [RESEND, PATCH 2/5] soc: mediatek: mtk-cmdq: Add cmdq_pkt_mem_move() function Date: Fri, 1 Mar 2024 22:44:00 +0800 Message-ID: <20240301144403.2977-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240301144403.2977-1-jason-jh.lin@mediatek.com> References: <20240301144403.2977-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cmdq_pkt_mem_move() function to support CMDQ user making an instruction for moving a value from a source address to a destination address. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 26 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 10 ++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index b0cd071c4719..3a1e47ad8a41 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -299,6 +299,32 @@ int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, = u8 high_addr_reg_idx, } EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value); =20 +s32 cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_= t dst_addr) +{ + s32 err; + const u16 tmp_reg_idx =3D CMDQ_THR_SPR_IDX0; + const u16 swap_reg_idx =3D CMDQ_THR_SPR_IDX1; + + /* read the value of src_addr into swap_reg_idx */ + err =3D cmdq_pkt_assign(pkt, tmp_reg_idx, CMDQ_ADDR_HIGH(src_addr)); + if (err < 0) + return err; + err =3D cmdq_pkt_read_s(pkt, tmp_reg_idx, CMDQ_ADDR_LOW(src_addr), swap_r= eg_idx); + if (err < 0) + return err; + + /* write the value of swap_reg_idx into dst_addr */ + err =3D cmdq_pkt_assign(pkt, tmp_reg_idx, CMDQ_ADDR_HIGH(dst_addr)); + if (err < 0) + return err; + err =3D cmdq_pkt_write_s(pkt, tmp_reg_idx, CMDQ_ADDR_LOW(dst_addr), swap_= reg_idx); + if (err < 0) + return err; + + return err; +} +EXPORT_SYMBOL(cmdq_pkt_mem_move); + int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear) { struct cmdq_instruction inst =3D { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index 1dae80185f9f..b6dbe2d8f16a 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -182,6 +182,16 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 hi= gh_addr_reg_idx, int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u16 addr_low, u32 value, u32 mask); =20 +/** + * cmdq_pkt_mem_move() - append memory move command to the CMDQ packet + * @pkt: the CMDQ packet + * @src_addr: source address + * @dma_addr_t: destination address + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_= t dst_addr); + /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet * @pkt: the CMDQ packet --=20 2.18.0 From nobody Fri Sep 20 01:30:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E95FA6CDCD for ; Fri, 1 Mar 2024 14:44:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709304256; cv=none; b=DMMcsNs3MbKMc9R+XHQpeqV3kjWx/lrI7w6HuRyqdshbMcTz4jdjVYMplJ+RyVrTGx8VvsNy4kv7gIQ5RGKFompx30bvItuwm83LmQ5upBQe1bdVM3REoy0bxLm1sotPPlrH2PP5QRmFD94zbRp1S4GcqJAmMsRSiZGTV7HbsBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709304256; c=relaxed/simple; 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Fri, 01 Mar 2024 22:44:06 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Mar 2024 22:44:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Mar 2024 22:44:05 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [RESEND, PATCH 3/5] soc: mediatek: mtk-cmdq: Add cmdq_pkt_poll_addr() function Date: Fri, 1 Mar 2024 22:44:01 +0800 Message-ID: <20240301144403.2977-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240301144403.2977-1-jason-jh.lin@mediatek.com> References: <20240301144403.2977-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cmdq_pkt_poll_addr function to support CMDQ user making an instruction for polling a specific address of hardware rigster to check the value with or without mask. POLL is an old operation in GCE, so it does not support SPR and CMDQ_CODE_LOGIC. CMDQ users need to use GPR and CMDQ_CODE_MASK to move polling register address to GPR to make an instruction. This will be done in cmdq_pkt_poll_addr(). Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 38 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 16 +++++++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index 3a1e47ad8a41..2e9fc9bb1183 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -12,6 +12,7 @@ =20 #define CMDQ_WRITE_ENABLE_MASK BIT(0) #define CMDQ_POLL_ENABLE_MASK BIT(0) +#define CMDQ_POLL_HIGH_ADDR_GPR (14) #define CMDQ_EOC_IRQ_EN BIT(0) #define CMDQ_REG_TYPE 1 #define CMDQ_JUMP_RELATIVE 1 @@ -406,6 +407,43 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, } EXPORT_SYMBOL(cmdq_pkt_poll_mask); =20 +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u= 32 mask) +{ + struct cmdq_instruction inst =3D { {0} }; + int err; + u8 use_mask =3D 0; + + if (mask !=3D U32_MAX) { + inst.op =3D CMDQ_CODE_MASK; + inst.mask =3D ~mask; + err =3D cmdq_pkt_append_command(pkt, inst); + if (err !=3D 0) + return err; + use_mask =3D CMDQ_POLL_ENABLE_MASK; + } + + /* + * POLL is an old operation in GCE and it does not support SPR and CMDQ_C= ODE_LOGIC, + * so it can not use cmdq_pkt_assign to keep polling register address to = SPR. + * It needs to use GPR and CMDQ_CODE_MASK to move polling register addres= s to GPR. + */ + inst.op =3D CMDQ_CODE_MASK; + inst.dst_t =3D CMDQ_REG_TYPE; + inst.sop =3D CMDQ_POLL_HIGH_ADDR_GPR; + inst.mask =3D addr; + err =3D cmdq_pkt_append_command(pkt, inst); + if (err < 0) + return err; + + inst.op =3D CMDQ_CODE_POLL; + inst.dst_t =3D CMDQ_REG_TYPE; + inst.sop =3D CMDQ_POLL_HIGH_ADDR_GPR; + inst.offset =3D use_mask; + inst.value =3D value; + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_poll_addr); + int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) { struct cmdq_instruction inst =3D {}; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index b6dbe2d8f16a..2fe9be240fbc 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -253,6 +253,22 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value, u32 mask); =20 +/** + * cmdq_pkt_poll_addr() - Append polling command to the CMDQ packet, ask G= CE to + * execute an instruction that wait for a specified + * address of hardware register to check for the value + * w/ or w/o mask. + * All GCE hardware threads will be blocked by this + * instruction. + * @pkt: the CMDQ packet + * @addr: the hardware register address + * @value: the specified target register value + * @mask: the specified target register mask + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u= 32 mask); + /** * cmdq_pkt_assign() - Append logic assign command to the CMDQ packet, ask= GCE * to execute an instruction that set a constant value into --=20 2.18.0 From nobody Fri Sep 20 01:30:26 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD1763AC0C for ; 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Fri, 01 Mar 2024 22:44:06 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Mar 2024 22:44:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Mar 2024 22:44:05 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [RESEND, PATCH 4/5] soc: mediatek: mtk-cmdq: Add cmdq_pkt_acquire_event() function Date: Fri, 1 Mar 2024 22:44:02 +0800 Message-ID: <20240301144403.2977-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240301144403.2977-1-jason-jh.lin@mediatek.com> References: <20240301144403.2977-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cmdq_pkt_acquire_event() function to support CMDQ user making an instruction for acquiring event. CMDQ users can use cmdq_pkt_acquire_event() and cmdq_pkt_clear_event() to acquire GCE event and release GCE event and achieve the MUTEX_LOCK protection between GCE threads. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 9 +++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index 2e9fc9bb1183..0183b40a0eff 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -342,6 +342,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool= clear) } EXPORT_SYMBOL(cmdq_pkt_wfe); =20 +int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event) +{ + struct cmdq_instruction inst =3D {}; + + if (event >=3D CMDQ_MAX_EVENT) + return -EINVAL; + + inst.op =3D CMDQ_CODE_WFE; + inst.value =3D CMDQ_WFE_UPDATE | CMDQ_WFE_UPDATE_VALUE | CMDQ_WFE_WAIT; + inst.event =3D event; + + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_acquire_event); + int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) { struct cmdq_instruction inst =3D { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index 2fe9be240fbc..de93c0a8e8a9 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -202,6 +202,15 @@ int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t= src_addr, dma_addr_t dst_ */ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear); =20 +/** + * cmdq_pkt_acquire_event() - append acquire event command to the CMDQ pac= ket + * @pkt: the CMDQ packet + * @event: the desired event to be acquired + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event); + /** * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet * @pkt: the CMDQ packet --=20 2.18.0 From nobody Fri Sep 20 01:30:26 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C0CC23DE for ; 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Fri, 01 Mar 2024 22:44:06 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Mar 2024 22:44:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Mar 2024 22:44:05 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , Matthias Brugger CC: AngeloGioacchino Del Regno , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , , , Subject: [RESEND, PATCH 5/5] mailbox: mtk-cmdq: Add support runtime get and set GCE event Date: Fri, 1 Mar 2024 22:44:03 +0800 Message-ID: <20240301144403.2977-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240301144403.2977-1-jason-jh.lin@mediatek.com> References: <20240301144403.2977-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ISP drivers need to get and set GCE event in their runtime contorl flow. So add these functions to support get and set GCE by CPU. Signed-off-by: Jason-JH.Lin --- drivers/mailbox/mtk-cmdq-mailbox.c | 37 ++++++++++++++++++++++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++ 2 files changed, 39 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index ead2200f39ba..d7c08249c898 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -25,7 +25,11 @@ #define CMDQ_GCE_NUM_MAX (2) =20 #define CMDQ_CURR_IRQ_STATUS 0x10 +#define CMDQ_SYNC_TOKEN_ID 0x60 +#define CMDQ_SYNC_TOKEN_VALUE 0x64 +#define CMDQ_TOKEN_ID_MASK GENMASK(9, 0) #define CMDQ_SYNC_TOKEN_UPDATE 0x68 +#define CMDQ_TOKEN_UPDATE_VALUE BIT(16) #define CMDQ_THR_SLOT_CYCLES 0x30 #define CMDQ_THR_BASE 0x100 #define CMDQ_THR_SIZE 0x80 @@ -83,6 +87,7 @@ struct cmdq { struct cmdq_thread *thread; struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX]; bool suspended; + spinlock_t event_lock; /* lock for gce event */ }; =20 struct gce_plat { @@ -113,6 +118,38 @@ u8 cmdq_get_shift_pa(struct mbox_chan *chan) } EXPORT_SYMBOL(cmdq_get_shift_pa); =20 +void cmdq_set_event(void *chan, u16 event_id) +{ + struct cmdq *cmdq =3D container_of(((struct mbox_chan *)chan)->mbox, + typeof(*cmdq), mbox); + unsigned long flags; + + spin_lock_irqsave(&cmdq->event_lock, flags); + + writel(CMDQ_TOKEN_UPDATE_VALUE | event_id, cmdq->base + CMDQ_SYNC_TOKEN_U= PDATE); + + spin_unlock_irqrestore(&cmdq->event_lock, flags); +} +EXPORT_SYMBOL(cmdq_set_event); + +u32 cmdq_get_event(void *chan, u16 event_id) +{ + struct cmdq *cmdq =3D container_of(((struct mbox_chan *)chan)->mbox, + typeof(*cmdq), mbox); + unsigned long flags; + u32 value =3D 0; + + spin_lock_irqsave(&cmdq->event_lock, flags); + + writel(CMDQ_TOKEN_ID_MASK & event_id, cmdq->base + CMDQ_SYNC_TOKEN_ID); + value =3D readl(cmdq->base + CMDQ_SYNC_TOKEN_VALUE); + + spin_unlock_irqrestore(&cmdq->event_lock, flags); + + return value; +} +EXPORT_SYMBOL(cmdq_get_event); + static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thre= ad) { u32 status; diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailb= ox/mtk-cmdq-mailbox.h index a8f0070c7aa9..f05cabd230da 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -79,5 +79,7 @@ struct cmdq_pkt { }; =20 u8 cmdq_get_shift_pa(struct mbox_chan *chan); +void cmdq_set_event(void *chan, u16 event_id); +u32 cmdq_get_event(void *chan, u16 event_id); =20 #endif /* __MTK_CMDQ_MAILBOX_H__ */ --=20 2.18.0