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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id st11-20020a170907c08b00b00a3f5c39bf2asm1618457ejc.0.2024.03.01.03.35.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 03:35:15 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Subject: [PATCH 1/4] arm64: dts: mediatek: mt7622: fix clock controllers Date: Fri, 1 Mar 2024 12:35:03 +0100 Message-Id: <20240301113506.22944-2-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240301113506.22944-1-zajec5@gmail.com> References: <20240301113506.22944-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Rafa=C5=82 Mi=C5=82ecki 1. Drop unneeded "syscon"s (bindings were updated recently) 2. Use "clock-controller" in nodenames 3. Add missing "#clock-cells" Signed-off-by: Rafa=C5=82 Mi=C5=82ecki --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 27 +++++++++++------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts= /mediatek/mt7622.dtsi index 3ee9266fa8e9..283fdf7d2d8b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -283,16 +283,14 @@ thermal_calibration: calib@198 { }; }; =20 - apmixedsys: apmixedsys@10209000 { - compatible =3D "mediatek,mt7622-apmixedsys", - "syscon"; + apmixedsys: clock-controller@10209000 { + compatible =3D "mediatek,mt7622-apmixedsys"; reg =3D <0 0x10209000 0 0x1000>; #clock-cells =3D <1>; }; =20 - topckgen: topckgen@10210000 { - compatible =3D "mediatek,mt7622-topckgen", - "syscon"; + topckgen: clock-controller@10210000 { + compatible =3D "mediatek,mt7622-topckgen"; reg =3D <0 0x10210000 0 0x1000>; #clock-cells =3D <1>; }; @@ -734,9 +732,8 @@ wmac: wmac@18000000 { power-domains =3D <&scpsys MT7622_POWER_DOMAIN_WB>; }; =20 - ssusbsys: ssusbsys@1a000000 { - compatible =3D "mediatek,mt7622-ssusbsys", - "syscon"; + ssusbsys: clock-controller@1a000000 { + compatible =3D "mediatek,mt7622-ssusbsys"; reg =3D <0 0x1a000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; @@ -793,9 +790,8 @@ u2port1: usb-phy@1a0c5000 { }; }; =20 - pciesys: pciesys@1a100800 { - compatible =3D "mediatek,mt7622-pciesys", - "syscon"; + pciesys: clock-controller@1a100800 { + compatible =3D "mediatek,mt7622-pciesys"; reg =3D <0 0x1a100800 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; @@ -921,12 +917,13 @@ sata_port: sata-phy@1a243000 { }; }; =20 - hifsys: syscon@1af00000 { - compatible =3D "mediatek,mt7622-hifsys", "syscon"; + hifsys: clock-controller@1af00000 { + compatible =3D "mediatek,mt7622-hifsys"; reg =3D <0 0x1af00000 0 0x70>; + #clock-cells =3D <1>; }; =20 - ethsys: syscon@1b000000 { + ethsys: clock-controller@1b000000 { compatible =3D "mediatek,mt7622-ethsys", "syscon"; reg =3D <0 0x1b000000 0 0x1000>; --=20 2.35.3