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Lin" , Singo Chang , "Nancy Lin" , Shawn Sung , , , , Subject: [PATCH 3/5] soc: mediatek: mtk-cmdq: Add cmdq_pkt_poll_addr() function Date: Fri, 1 Mar 2024 19:11:24 +0800 Message-ID: <20240301111126.22035-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240301111126.22035-1-jason-jh.lin@mediatek.com> References: <20240301111126.22035-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.772500-8.000000 X-TMASE-MatchedRID: 8X2PBhRYyqJYXTxImR5ZvFVN8laWo90MYu7s3QSSN+Tfc2Xd6VJ+ysxF Qxp3PhHyz4sGsPGzdli46TLvlH7amuHxFb2pjr4bhK8o4aoss8pKPIx+MJF9o99RlPzeVuQQXVC mjmk3KwwDvKUzYsUZK1fsuOSPFWFcKYkG37rHS8Xzh2yKdnl7WPSEh8AqyHUv/rvU1dGgVf76au 5bveuHjHhYmQFcXfkdgDLqnrRlXrZ8nn9tnqel2K6NVEWSRWybLIRvJZxdOT8ccxlO3vDdFnpRb 6jaaE2WB4xikmzQuji9mcsT4mLfgePF7+QNf5yPgesk0PKcIwDLcleArf7N1eS8xlf5yikEjofs MjQaxVwyYjbiqIQ3CsykhtyXcigD6rVdgBjDT2r1nXJavJVNag== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.772500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: F66502118867CD93F42C699C31E1482D3047D14864830B5BC5BAD1E4B63B00072000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cmdq_pkt_poll_addr function to support CMDQ user making an instruction for polling a specific address of hardware rigster to check the value with or without mask. POLL is an old operation in GCE, so it does not support SPR and CMDQ_CODE_LOGIC. CMDQ users need to use GPR and CMDQ_CODE_MASK to move polling register address to GPR to make an instruction. This will be done in cmdq_pkt_poll_addr(). Signed-off-by: Jason-JH.Lin Change-Id: I91ff98e06570dc4501187eb29de64aaa65b1cf13 --- drivers/soc/mediatek/mtk-cmdq-helper.c | 38 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 16 +++++++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/= mtk-cmdq-helper.c index 3a1e47ad8a41..2e9fc9bb1183 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -12,6 +12,7 @@ =20 #define CMDQ_WRITE_ENABLE_MASK BIT(0) #define CMDQ_POLL_ENABLE_MASK BIT(0) +#define CMDQ_POLL_HIGH_ADDR_GPR (14) #define CMDQ_EOC_IRQ_EN BIT(0) #define CMDQ_REG_TYPE 1 #define CMDQ_JUMP_RELATIVE 1 @@ -406,6 +407,43 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, } EXPORT_SYMBOL(cmdq_pkt_poll_mask); =20 +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u= 32 mask) +{ + struct cmdq_instruction inst =3D { {0} }; + int err; + u8 use_mask =3D 0; + + if (mask !=3D U32_MAX) { + inst.op =3D CMDQ_CODE_MASK; + inst.mask =3D ~mask; + err =3D cmdq_pkt_append_command(pkt, inst); + if (err !=3D 0) + return err; + use_mask =3D CMDQ_POLL_ENABLE_MASK; + } + + /* + * POLL is an old operation in GCE and it does not support SPR and CMDQ_C= ODE_LOGIC, + * so it can not use cmdq_pkt_assign to keep polling register address to = SPR. + * It needs to use GPR and CMDQ_CODE_MASK to move polling register addres= s to GPR. + */ + inst.op =3D CMDQ_CODE_MASK; + inst.dst_t =3D CMDQ_REG_TYPE; + inst.sop =3D CMDQ_POLL_HIGH_ADDR_GPR; + inst.mask =3D addr; + err =3D cmdq_pkt_append_command(pkt, inst); + if (err < 0) + return err; + + inst.op =3D CMDQ_CODE_POLL; + inst.dst_t =3D CMDQ_REG_TYPE; + inst.sop =3D CMDQ_POLL_HIGH_ADDR_GPR; + inst.offset =3D use_mask; + inst.value =3D value; + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_poll_addr); + int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) { struct cmdq_instruction inst =3D {}; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/medi= atek/mtk-cmdq.h index b6dbe2d8f16a..2fe9be240fbc 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -253,6 +253,22 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value, u32 mask); =20 +/** + * cmdq_pkt_poll_addr() - Append polling command to the CMDQ packet, ask G= CE to + * execute an instruction that wait for a specified + * address of hardware register to check for the value + * w/ or w/o mask. + * All GCE hardware threads will be blocked by this + * instruction. + * @pkt: the CMDQ packet + * @addr: the hardware register address + * @value: the specified target register value + * @mask: the specified target register mask + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u= 32 mask); + /** * cmdq_pkt_assign() - Append logic assign command to the CMDQ packet, ask= GCE * to execute an instruction that set a constant value into --=20 2.18.0