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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240301-x1e80100-pci-v4-1-7ab7e281d647@linaro.org> References: <20240301-x1e80100-pci-v4-0-7ab7e281d647@linaro.org> In-Reply-To: <20240301-x1e80100-pci-v4-0-7ab7e281d647@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6174; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=1cnXF/UECj2KO4q4f1/R4DEYEj/qecZ9dKHdF1neor8=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBl4gldFvPw8/3HvDbwo2gcLZTLYOuKhwbPBWhSH NbVHeNrmcWJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZeIJXQAKCRAbX0TJAJUV VsVnEACNU/RtdKUeko4mzeIUo5Fo7Iv4oGzY27wMNTnvQ+GuUH0GCxjX5CTZnaaLDdBJGZwhM+8 Hdirn9naV3jJGUbWrrYqUqUi64jzT9CKCnU/oHZUjsK2uEOdvMe/iWjQTpybbOm+D7MXwXuxcw7 UbTcw9zfTYgJYk9H46N9PbGqtMp8ufFI9zMFEit9r8sT3Ml5lzQgzAsY2wevXqsRyEFz4PBiw80 JFM9UyxalLK68lO24CMb7VK7nHn5aaGAn0rnAIxgyqFWTyGDMxTsqB7Lc55NZDrAbWqGrC+6h40 mpjCz8b8TEKh35h/Z/8pPuxcSBF6qWd8hj8T2xBpEed8EH1kstCDn5M0bQrsGd54bTL2Hx9Kznk x7ob66lCPQsuZh3DKkZXZFS5pjQCgMg1ljCV8TDB/fLGuzegGIBpxtSOUedL8XLBpjx9VaxuduE iuxVtZJ9xGyhSXC5jRU0BKxVJ5i88aEucJHp01IqlD6TeQy/14VqGZsIyX+25ynMpg0Whewajsw p6Iai4cPH3nDznMrpPQha5tAxmiQZA/sJm/8VJss80ABowgkxVmXl3x7Wi0Nd6lzGh2+5xmIbqa c6FXgi3ju/tLrVOwmpeiYBsEATCz5/EFKCkYTLpQNQfg4mLGGy6i1SL5zAOOxMvCwTd8YJfKk73 BaSvbVdaTA9OyeA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add dedicated schema for the PCIe controllers found on X1E80100. Signed-off-by: Abel Vesa Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/qcom,pcie-x1e80100.yaml | 165 +++++++++++++++++= ++++ 1 file changed, 165 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml = b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml new file mode 100644 index 000000000000..1074310a8e7a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is b= ased on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-x1e80100 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 7 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c08000 { + compatible =3D "qcom,pcie-x1e80100"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x7c000000 0 0xf1d>, + <0 0x7c000f40 0 0xa8>, + <0 0x7c001000 0 0x1000>, + <0 0x7c100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100= 000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH= >, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,= /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,= /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;= /* int_d */ + + interconnects =3D <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EB= I1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE= _PCIE_4 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys =3D <&pcie4_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc GCC_PCIE_4_GDSC>; + + resets =3D <&gcc GCC_PCIE_4_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add the compatible and the driver data for X1E80100 PCIe controller. There are 5 controller instances found on this platform, out of which 2 are Gen3 with speeds of up to 8.0GT/s, while the other 3 are Gen4 with speeds of up to 16GT/s. The version of the controller is 1.38.0 for all instances, but they are compatible with 1.9.0 config. The max link width is x8 for one controller, x4 for two of others and x2 for the two left. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Abel Vesa --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 2ce2a3bd932b..b7467f9dfea9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-sm8450-pcie0", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8450-pcie1", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8550", .data =3D &cfg_1_9_0 }, + { .compatible =3D "qcom,pcie-x1e80100", .data =3D &cfg_1_9_0 }, { } }; =20 --=20 2.34.1