From nobody Mon Feb 9 08:55:49 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BF18482DF; Fri, 1 Mar 2024 03:36:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709264161; cv=none; b=rOPAgbiswhx32EhSL3mki2uvp7E6yZu/qErYpQjo3N8wVcWjner0ioC/H7zWnu0B5qIdPY9EQk9u6NhXgRrpX4vSI10TQi5l8vSAoTnt3V6dujIPBoGRovIvJV84mWs+yjeYI6wzNRN6J+G/oKZC8MKnXC/JGJGMkA2mMdFSr0M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709264161; c=relaxed/simple; bh=MJif9gM+OTN6uv2+Y+Woloo1HMrmxN37Tj7Nmiagu0M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i4gp3+jC1GXRoY/U2slujJ6H5KqAEPPaTuBRUQQ2a2z2paoS4rUdKSRx/8Ebf0AWya5yIiKMIgzbmehYmkcHlSMVpJBveDJQnGwVzMjZZiXq7QO4RAhHoGX9WGV5+mEmmbcbgLQ3QQ7An6tdSojhxz0BbfCZBmgTsTP+qOaxHWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A/71gSQg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A/71gSQg" Received: by smtp.kernel.org (Postfix) with ESMTPS id BFB2BC4167E; Fri, 1 Mar 2024 03:36:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709264160; bh=MJif9gM+OTN6uv2+Y+Woloo1HMrmxN37Tj7Nmiagu0M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=A/71gSQgdYyypHUVueIB5Zh1di74yQJTxNhEXTw3+dRWq47WKgteS0FG+HginPxDc mFSvqpQLzCI3MWnoKiQngGDtlq4S1Lgh4lpYHsdMHnTrH2powCiD5zIerc7WLwjDa5 6jZEgUka/euI9Iq20yujE4vF+2TTdeKKme/GMD34TvIdsmIerTnCpAQSsO2N7ZTvre qeegHbYLSXuzZUQ4PFtxVi0FvFXzM/yFntD66w2YlXhWWoUmT6zM1kCWAefXCQp7Lf H3+sIwi9R34GVdVuGrr1+nilmnb4QMQextrwrsp5zRO2ERPheMeAT6SC/HMowP57Jf gRGlXAKzKKg/g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFC26C54E55; Fri, 1 Mar 2024 03:36:00 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Fri, 01 Mar 2024 11:36:01 +0800 Subject: [PATCH net-next v7 8/9] net: hisi_femac: add support for hisi_femac core on Hi3798MV200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240301-net-v7-8-45823597d4d4@outlook.com> References: <20240301-net-v7-0-45823597d4d4@outlook.com> In-Reply-To: <20240301-net-v7-0-45823597d4d4@outlook.com> To: Yisen Zhuang , Salil Mehta , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709264157; l=6571; i=forbidden405@outlook.com; s=20240228; h=from:subject:message-id; bh=7r/SzKt7Slny2pCaFA5xgpTMqsYzRWcfAXD5cVU5KYE=; b=x+kH33EaxeKC6RXPGCDyy1GD45wsDTqQD8yq3dI5YwiE6pvk1/JOEcCb2Tz3CS+kNteRK/nPN zukNigeq0U4AHSWRxzPqIHH7epDONIO1crLMFr9kSQSg2zOQuVxJKAK X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=KAWv6ZzFsT54MGllOczJgFiWB+DuayEmyn24iiVVThU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20240228 with auth_id=136 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen Register the sub MDIO bus if it is found. Also implement the internal PHY reset procedure as needed. Note it's unable to put the MDIO bus node outside of MAC controller (i.e. at the same level in the parent bus node). Because we need to control all clocks and resets in FEMAC driver due to the phy reset procedure. So the clocks can't be assigned to MDIO bus device, which is an essential resource for the MDIO bus to work. Signed-off-by: Yang Xiwen --- drivers/net/ethernet/hisilicon/hisi_femac.c | 73 +++++++++++++++++++++++--= ---- 1 file changed, 59 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hisi_femac.c b/drivers/net/ethe= rnet/hisilicon/hisi_femac.c index 5a088cba7d4e..22a4697e0dde 100644 --- a/drivers/net/ethernet/hisilicon/hisi_femac.c +++ b/drivers/net/ethernet/hisilicon/hisi_femac.c @@ -10,8 +10,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -97,6 +99,13 @@ enum phy_reset_delays { DELAYS_NUM, }; =20 +enum clk_type { + CLK_MAC, + CLK_MACIF, + CLK_PHY, + CLK_NUM, +}; + struct hisi_femac_queue { struct sk_buff **skb; dma_addr_t *dma_phys; @@ -108,7 +117,7 @@ struct hisi_femac_queue { struct hisi_femac_priv { void __iomem *port_base; void __iomem *glb_base; - struct clk *clk; + struct clk_bulk_data *clks; struct reset_control *mac_rst; struct reset_control *phy_rst; u32 phy_reset_delays[DELAYS_NUM]; @@ -116,6 +125,7 @@ struct hisi_femac_priv { =20 struct device *dev; struct net_device *ndev; + struct platform_device *mdio_pdev; =20 struct hisi_femac_queue txq; struct hisi_femac_queue rxq; @@ -693,6 +703,7 @@ static const struct net_device_ops hisi_femac_netdev_op= s =3D { static void hisi_femac_core_reset(struct hisi_femac_priv *priv) { reset_control_assert(priv->mac_rst); + usleep_range(200, 300); reset_control_deassert(priv->mac_rst); } =20 @@ -712,6 +723,10 @@ static void hisi_femac_sleep_us(u32 time_us) =20 static void hisi_femac_phy_reset(struct hisi_femac_priv *priv) { + /* MAC clock must be disabled before PHY reset + */ + clk_disable(priv->clks[CLK_MAC].clk); + clk_disable(priv->clks[CLK_MACIF].clk); /* To make sure PHY hardware reset success, * we must keep PHY in deassert state first and * then complete the hardware reset operation @@ -727,6 +742,9 @@ static void hisi_femac_phy_reset(struct hisi_femac_priv= *priv) reset_control_deassert(priv->phy_rst); /* delay some time to ensure later MDIO access */ hisi_femac_sleep_us(priv->phy_reset_delays[POST_DELAY]); + + clk_enable(priv->clks[CLK_MAC].clk); + clk_enable(priv->clks[CLK_MACIF].clk); } =20 static void hisi_femac_port_init(struct hisi_femac_priv *priv) @@ -768,11 +786,12 @@ static void hisi_femac_port_init(struct hisi_femac_pr= iv *priv) static int hisi_femac_drv_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->of_node; + struct device_node *node =3D dev->of_node, *mdio_np; struct net_device *ndev; struct hisi_femac_priv *priv; struct phy_device *phy; int ret; + bool mdio_registered =3D false; =20 ndev =3D alloc_etherdev(sizeof(*priv)); if (!ndev) @@ -797,17 +816,16 @@ static int hisi_femac_drv_probe(struct platform_devic= e *pdev) goto out_free_netdev; } =20 - priv->clk =3D devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(priv->clk)) { - dev_err(dev, "failed to get clk\n"); - ret =3D -ENODEV; + ret =3D devm_clk_bulk_get_all(&pdev->dev, &priv->clks); + if (ret < 0 || ret !=3D CLK_NUM) { + dev_err(dev, "failed to get clk bulk: %d\n", ret); goto out_free_netdev; } =20 - ret =3D clk_prepare_enable(priv->clk); + ret =3D clk_bulk_prepare_enable(CLK_NUM, priv->clks); if (ret) { - dev_err(dev, "failed to enable clk %d\n", ret); - goto out_free_netdev; + dev_err(dev, "failed to enable clk bulk: %d\n", ret); + goto out_disable_clk; } =20 priv->mac_rst =3D devm_reset_control_get(dev, "mac"); @@ -830,11 +848,29 @@ static int hisi_femac_drv_probe(struct platform_devic= e *pdev) hisi_femac_phy_reset(priv); } =20 + // Register the optional MDIO bus + for_each_available_child_of_node(node, mdio_np) { + if (of_node_name_prefix(mdio_np, "mdio")) { + priv->mdio_pdev =3D of_platform_device_create(mdio_np, NULL, dev); + of_node_put(mdio_np); + if (!priv->mdio_pdev) { + dev_err(dev, "failed to register MDIO bus device\n"); + ret =3D -ENODEV; + goto out_disable_clk; + } + mdio_registered =3D true; + break; + } + } + + if (!mdio_registered) + dev_warn(dev, "MDIO subnode not found. This is usually a bug.\n"); + phy =3D of_phy_get_and_connect(ndev, node, hisi_femac_adjust_link); if (!phy) { dev_err(dev, "connect to PHY failed!\n"); ret =3D -ENODEV; - goto out_disable_clk; + goto out_unregister_mdio_bus; } =20 phy_attached_print(phy, "phy_id=3D0x%.8lx, phy_mode=3D%s\n", @@ -885,8 +921,10 @@ static int hisi_femac_drv_probe(struct platform_device= *pdev) out_disconnect_phy: netif_napi_del(&priv->napi); phy_disconnect(phy); +out_unregister_mdio_bus: + platform_device_unregister(priv->mdio_pdev); out_disable_clk: - clk_disable_unprepare(priv->clk); + clk_bulk_disable_unprepare(CLK_NUM, priv->clks); out_free_netdev: free_netdev(ndev); =20 @@ -902,7 +940,8 @@ static void hisi_femac_drv_remove(struct platform_devic= e *pdev) unregister_netdev(ndev); =20 phy_disconnect(ndev->phydev); - clk_disable_unprepare(priv->clk); + platform_device_unregister(priv->mdio_pdev); + clk_bulk_disable_unprepare(CLK_NUM, priv->clks); free_netdev(ndev); } =20 @@ -919,7 +958,7 @@ static int hisi_femac_drv_suspend(struct platform_devic= e *pdev, netif_device_detach(ndev); } =20 - clk_disable_unprepare(priv->clk); + clk_bulk_disable_unprepare(CLK_NUM, priv->clks); =20 return 0; } @@ -928,8 +967,14 @@ static int hisi_femac_drv_resume(struct platform_devic= e *pdev) { struct net_device *ndev =3D platform_get_drvdata(pdev); struct hisi_femac_priv *priv =3D netdev_priv(ndev); + int ret; + + ret =3D clk_bulk_prepare_enable(CLK_NUM, priv->clks); + if (ret) { + dev_err(&pdev->dev, "failed to enable clk bulk: %d\n", ret); + return ret; + } =20 - clk_prepare_enable(priv->clk); if (priv->phy_rst) hisi_femac_phy_reset(priv); =20 --=20 2.43.0