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Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/csr.h | 2 +- arch/riscv/include/asm/errata_list.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..603e5a3c61f9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f =20 -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 =20 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index ea33288f8a25..cd49eb025ddf 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -114,7 +114,7 @@ asm volatile(ALTERNATIVE( \ =20 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU) \ --=20 2.34.1 From nobody Sun Feb 8 10:03:18 2026 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9D224438A for ; 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charset="utf-8" SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/sbi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6e68f8dff76b..ef8311dafb91 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_START, SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, }; =20 union sbi_pmu_ctr_info { --=20 2.34.1 From nobody Sun Feb 8 10:03:18 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A204F44C7B for ; Thu, 29 Feb 2024 01:01:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; 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charset="utf-8" SBI v2.0 introduced a explicit function to read the upper 32 bits for any firmwar counter width that is longer than 32bits. This is only applicable for RV32 where firmware counter can be 64 bit. Acked-by: Palmer Dabbelt Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- drivers/perf/riscv_pmu_sbi.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16acd4dcdb96..ea0fdb589f0d 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -35,6 +35,8 @@ PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:63"); =20 +static bool sbi_v2_available; + static struct attribute *riscv_arch_formats_attr[] =3D { &format_attr_event.attr, &format_attr_firmware.attr, @@ -488,16 +490,23 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; struct sbiret ret; - union sbi_pmu_ctr_info info; u64 val =3D 0; + union sbi_pmu_ctr_info info =3D pmu_ctr_list[idx]; =20 if (pmu_sbi_is_fw_event(event)) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); 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charset="utf-8" SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Anup Patel Acked-by: Palmer Dabbelt Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..dfa830f7d54b 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, }; =20 union sbi_pmu_ctr_info { @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info { }; }; =20 +/* Data structure to contain the pmu snapshot data */ +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 =20 @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type { =20 /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT BIT(1) =20 /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) =20 enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE =3D 0, @@ -285,6 +295,7 @@ struct sbi_sta_struct { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 =20 extern unsigned long sbi_spec_version; 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Wed, 28 Feb 2024 17:01:50 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:01:50 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Palmer Dabbelt , Anup Patel , Conor Dooley , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 05/15] drivers/perf: riscv: Implement SBI PMU snapshot function Date: Wed, 28 Feb 2024 17:01:20 -0800 Message-Id: <20240229010130.1380926-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SBI v2.0 SBI introduced PMU snapshot feature which adds the following features. 1. Read counter values directly from the shared memory instead of csr read. 2. Start multiple counters with initial values with one SBI call. These functionalities optimizes the number of traps to the higher privilege mode. If the kernel is in VS mode while the hypervisor deploy trap & emulate method, this would minimize all the hpmcounter CSR read traps. If the kernel is running in S-mode, the benefits reduced to CSR latency vs DRAM/cache latency as there is no trap involved while accessing the hpmcounter CSRs. In both modes, it does saves the number of ecalls while starting multiple counter together with an initial values. This is a likely scenario if multiple counters overflow at the same time. Acked-by: Palmer Dabbelt Reviewed-by: Anup Patel Reviewed-by: Conor Dooley Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu.c | 1 + drivers/perf/riscv_pmu_sbi.c | 209 +++++++++++++++++++++++++++++++-- include/linux/perf/riscv_pmu.h | 6 + 3 files changed, 204 insertions(+), 12 deletions(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index 0dda70e1ef90..5b57acb770d3 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -412,6 +412,7 @@ struct riscv_pmu *riscv_pmu_alloc(void) cpuc->n_events =3D 0; for (i =3D 0; i < RISCV_MAX_COUNTERS; i++) cpuc->events[i] =3D NULL; + cpuc->snapshot_addr =3D NULL; } pmu->pmu =3D (struct pmu) { .event_init =3D riscv_pmu_event_init, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index ea0fdb589f0d..8de5721e8019 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -36,6 +36,9 @@ PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:63"); =20 static bool sbi_v2_available; +static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); +#define sbi_pmu_snapshot_available() \ + static_branch_unlikely(&sbi_pmu_snapshot_available) =20 static struct attribute *riscv_arch_formats_attr[] =3D { &format_attr_event.attr, @@ -485,14 +488,100 @@ static int pmu_sbi_event_map(struct perf_event *even= t, u64 *econfig) return ret; } =20 +static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) +{ + int cpu; + + for_each_possible_cpu(cpu) { + struct cpu_hw_events *cpu_hw_evt =3D per_cpu_ptr(pmu->hw_events, cpu); + + if (!cpu_hw_evt->snapshot_addr) + continue; + + free_page((unsigned long)cpu_hw_evt->snapshot_addr); + cpu_hw_evt->snapshot_addr =3D NULL; + cpu_hw_evt->snapshot_addr_phys =3D 0; + } +} + +static int pmu_sbi_snapshot_alloc(struct riscv_pmu *pmu) +{ + int cpu; + struct page *snapshot_page; + + for_each_possible_cpu(cpu) { + struct cpu_hw_events *cpu_hw_evt =3D per_cpu_ptr(pmu->hw_events, cpu); + + if (cpu_hw_evt->snapshot_addr) + continue; + + snapshot_page =3D alloc_page(GFP_ATOMIC | __GFP_ZERO); + if (!snapshot_page) { + pmu_sbi_snapshot_free(pmu); + return -ENOMEM; + } + cpu_hw_evt->snapshot_addr =3D page_to_virt(snapshot_page); + cpu_hw_evt->snapshot_addr_phys =3D page_to_phys(snapshot_page); + } + + return 0; +} + +static void pmu_sbi_snapshot_disable(void) +{ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, -1, + -1, 0, 0, 0, 0); +} + +static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu) +{ + struct cpu_hw_events *cpu_hw_evt; + struct sbiret ret =3D {0}; + + cpu_hw_evt =3D per_cpu_ptr(pmu->hw_events, cpu); + if (!cpu_hw_evt->snapshot_addr_phys) + return -EINVAL; + + if (cpu_hw_evt->snapshot_set_done) + return 0; + + if (IS_ENABLED(CONFIG_32BIT)) + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + cpu_hw_evt->snapshot_addr_phys, + (u64)(cpu_hw_evt->snapshot_addr_phys) >> 32, 0, 0, 0, 0); + else + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + cpu_hw_evt->snapshot_addr_phys, 0, 0, 0, 0, 0); + + /* Free up the snapshot area memory and fall back to SBI PMU calls withou= t snapshot */ + if (ret.error) { + if (ret.error !=3D SBI_ERR_NOT_SUPPORTED) + pr_warn("pmu snapshot setup failed with error %ld\n", ret.error); + return sbi_err_map_linux_errno(ret.error); + } + + cpu_hw_evt->snapshot_set_done =3D true; + + return 0; +} + static u64 pmu_sbi_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; struct sbiret ret; u64 val =3D 0; + struct riscv_pmu *pmu =3D to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; union sbi_pmu_ctr_info info =3D pmu_ctr_list[idx]; =20 + /* Read the value from the shared memory directly */ + if (sbi_pmu_snapshot_available()) { + val =3D sdata->ctr_values[idx]; + return val; + } + if (pmu_sbi_is_fw_event(event)) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); @@ -539,6 +628,7 @@ static void pmu_sbi_ctr_start(struct perf_event *event,= u64 ival) struct hw_perf_event *hwc =3D &event->hw; unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; =20 + /* There is no benefit setting SNAPSHOT FLAG for a single counter */ #if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 1, flag, ival, ival >> 32, 0); @@ -559,16 +649,36 @@ static void pmu_sbi_ctr_stop(struct perf_event *event= , unsigned long flag) { struct sbiret ret; struct hw_perf_event *hwc =3D &event->hw; + struct riscv_pmu *pmu =3D to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; =20 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) pmu_sbi_reset_scounteren((void *)event); =20 + if (sbi_pmu_snapshot_available()) + flag |=3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, fla= g, 0, 0, 0); - if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STOPPED) && - flag !=3D SBI_PMU_STOP_FLAG_RESET) + if (!ret.error && sbi_pmu_snapshot_available()) { + /* + * The counter snapshot is based on the index base specified by hwc->idx. + * The actual counter value is updated in shared memory at index 0 when = counter + * mask is 0x01. To ensure accurate counter values, it's necessary to tr= ansfer + * the counter value to shared memory. However, if hwc->idx is zero, the= counter + * value is already correctly updated in shared memory, requiring no fur= ther + * adjustment. + */ + if (hwc->idx > 0) { + sdata->ctr_values[hwc->idx] =3D sdata->ctr_values[0]; + sdata->ctr_values[0] =3D 0; + } + } else if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STOPPED) && + flag !=3D SBI_PMU_STOP_FLAG_RESET) { pr_err("Stopping counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); + } } =20 static int pmu_sbi_find_num_ctrs(void) @@ -626,10 +736,14 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu = *pmu) static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) { struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + unsigned long flag =3D 0; + + if (sbi_pmu_snapshot_available()) + flag =3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; =20 /* No need to check the error here as we can't do anything about the erro= r */ sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, - cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0); + cpu_hw_evt->used_hw_ctrs[0], flag, 0, 0, 0); } =20 /* @@ -638,11 +752,10 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_= pmu *pmu) * while the overflowed counters need to be started with updated initializ= ation * value. */ -static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - unsigned long ctr_ovf_mask) +static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_= hw_evt, + unsigned long ctr_ovf_mask) { int idx =3D 0; - struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); struct perf_event *event; unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; unsigned long ctr_start_mask =3D 0; @@ -677,6 +790,49 @@ static inline void pmu_sbi_start_overflow_mask(struct = riscv_pmu *pmu, } } =20 +static noinline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events = *cpu_hw_evt, + unsigned long ctr_ovf_mask) +{ + int idx =3D 0; + struct perf_event *event; + unsigned long flag =3D SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT; + u64 max_period, init_val =3D 0; + struct hw_perf_event *hwc; + unsigned long ctr_start_mask =3D 0; + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; + + for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) { + if (ctr_ovf_mask & (1 << idx)) { + event =3D cpu_hw_evt->events[idx]; + hwc =3D &event->hw; + max_period =3D riscv_pmu_ctr_get_width_mask(event); + init_val =3D local64_read(&hwc->prev_count) & max_period; + sdata->ctr_values[idx] =3D init_val; + } + /* + * We donot need to update the non-overflow counters the previous + * value should have been there already. + */ + } + + ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[0]; + + /* Start all the counters in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask, + flag, 0, 0, 0); +} + +static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, + unsigned long ctr_ovf_mask) +{ + struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + + if (sbi_pmu_snapshot_available()) + pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + else + pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); +} + static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) { struct perf_sample_data data; @@ -690,6 +846,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *d= ev) unsigned long overflowed_ctrs =3D 0; struct cpu_hw_events *cpu_hw_evt =3D dev; u64 start_clock =3D sched_clock(); + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; =20 if (WARN_ON_ONCE(!cpu_hw_evt)) return IRQ_NONE; @@ -711,8 +868,10 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *= dev) pmu_sbi_stop_hw_ctrs(pmu); =20 /* Overflow status register should only be read after counter are stopped= */ - ALT_SBI_PMU_OVERFLOW(overflow); - + if (sbi_pmu_snapshot_available()) + overflow =3D sdata->ctr_overflow_mask; + else + ALT_SBI_PMU_OVERFLOW(overflow); /* * Overflow interrupt pending bit should only be cleared after stopping * all the counters to avoid any race condition. @@ -794,6 +953,9 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struc= t hlist_node *node) enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } =20 + if (sbi_pmu_snapshot_available()) + return pmu_sbi_snapshot_setup(pmu, cpu); + return 0; } =20 @@ -807,6 +969,9 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct h= list_node *node) /* Disable all counters access for user mode now */ csr_write(CSR_SCOUNTEREN, 0x0); =20 + if (sbi_pmu_snapshot_available()) + pmu_sbi_snapshot_disable(); + return 0; } =20 @@ -1076,10 +1241,6 @@ static int pmu_sbi_device_probe(struct platform_devi= ce *pdev) pmu->event_unmapped =3D pmu_sbi_event_unmapped; pmu->csr_index =3D pmu_sbi_csr_index; =20 - ret =3D cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node= ); - if (ret) - return ret; - ret =3D riscv_pm_pmu_register(pmu); if (ret) goto out_unregister; @@ -1088,8 +1249,32 @@ static int pmu_sbi_device_probe(struct platform_devi= ce *pdev) if (ret) goto out_unregister; =20 + /* SBI PMU Snapsphot is only available in SBI v2.0 */ + if (sbi_v2_available) { + ret =3D pmu_sbi_snapshot_alloc(pmu); + if (ret) + goto out_unregister; + + ret =3D pmu_sbi_snapshot_setup(pmu, smp_processor_id()); + if (!ret) { + pr_info("SBI PMU snapshot detected\n"); + /* + * We enable it once here for the boot cpu. If snapshot shmem setup + * fails during cpu hotplug process, it will fail to start the cpu + * as we can not handle hetergenous PMUs with different snapshot + * capability. + */ + static_branch_enable(&sbi_pmu_snapshot_available); + } + /* Snapshot is an optional feature. Continue if not available */ + } + register_sysctl("kernel", sbi_pmu_sysctl_table); =20 + ret =3D cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node= ); + if (ret) + return ret; + return 0; =20 out_unregister: diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 43282e22ebe1..c3fa90970042 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -39,6 +39,12 @@ struct cpu_hw_events { DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS); /* currently enabled firmware counters */ DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS); + /* The virtual address of the shared memory where counter snapshot will b= e taken */ + void *snapshot_addr; + /* The physical address of the shared memory where counter snapshot will = be taken */ + phys_addr_t snapshot_addr_phys; + /* Boolean flag to indicate setup is already done */ + bool snapshot_set_done; }; =20 struct riscv_pmu { --=20 2.34.1 From nobody Sun Feb 8 10:03:18 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C030482D1 for ; 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Wed, 28 Feb 2024 17:01:52 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:01:51 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 06/15] RISC-V: KVM: No need to update the counter value during reset Date: Wed, 28 Feb 2024 17:01:21 -0800 Message-Id: <20240229010130.1380926-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The virtual counter value is updated during pmu_ctr_read. There is no need to update it in reset case. Otherwise, it will be counted twice which is incorrect. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_pmu.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 86391a5061dd..b1574c043f77 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, = unsigned long ctr_base, { struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); int i, pmc_index, sbiret =3D 0; - u64 enabled, running; struct kvm_pmc *pmc; int fevent_code; =20 @@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, sbiret =3D SBI_ERR_ALREADY_STOPPED; } =20 - if (flags & SBI_PMU_STOP_FLAG_RESET) { - /* Relase the counter if this is a reset request */ - pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, - &enabled, &running); + if (flags & SBI_PMU_STOP_FLAG_RESET) + /* Release the counter if this is a reset request */ kvm_pmu_release_perf_event(pmc); - } } else { sbiret =3D SBI_ERR_INVALID_PARAM; } --=20 2.34.1 From nobody Sun Feb 8 10:03:18 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 110C94D9E0 for ; Thu, 29 Feb 2024 01:01:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709168516; cv=none; b=BH3qFjeLiLFzqitTZXAchW5BW40VZIemurC0egs9EAgzFNxIYWNu8WWHTy+PMDYBeQQET8o6qlZLGPIUpxPvZ0foEZKwhQVm5p1z0/IDD/OsKHkS80prt6b0EQwiV71VYak60Xj3IU2VjRCCNmDX7vVxOpATRQuuEWMxprDM9aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709168516; c=relaxed/simple; bh=1V+hd27rw6/WCAn1DleSGvGCcsHuYA/SEtOYZLS88jw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=af6jaIqIAFvgB964CssfSWd5FvzhC/BmD56k3xJHnrV2FezAWl1+E625FHq1tyZ+f5KS84WPX3126INyClG55SojX0uk5Y8cTg70xavnGsLn498F6gHjBUxvRr0WoaC1LI3g0O2dA7qXfYsgbyiWIlGXbNqEDzgX13eljoFcnQE= ARC-Authentication-Results: i=1; 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Wed, 28 Feb 2024 17:01:53 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:01:53 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 07/15] RISC-V: KVM: No need to exit to the user space if perf event failed Date: Wed, 28 Feb 2024 17:01:22 -0800 Message-Id: <20240229010130.1380926-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, we return a linux error code if creating a perf event failed in kvm. That shouldn't be necessary as guest can continue to operate without perf profiling or profiling with firmware counters. Return appropriate SBI error code to indicate that PMU configuration failed. An error message in kvm already describes the reason for failure. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 14 +++++++++----- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 +++--- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index b1574c043f77..29bf4ca798cb 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -229,8 +229,9 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pmu= *kvpmu, unsigned long ct return 0; } =20 -static int kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_even= t_attr *attr, - unsigned long flags, unsigned long eidx, unsigned long evtdata) +static long kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_eve= nt_attr *attr, + unsigned long flags, unsigned long eidx, + unsigned long evtdata) { struct perf_event *event; =20 @@ -454,7 +455,8 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata) { - int ctr_idx, ret, sbiret =3D 0; + int ctr_idx, sbiret =3D 0; + long ret; bool is_fevent; unsigned long event_code; u32 etype =3D kvm_pmu_get_perf_event_type(eidx); @@ -513,8 +515,10 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *= vcpu, unsigned long ctr_ba kvpmu->fw_event[event_code].started =3D true; } else { ret =3D kvm_pmu_create_perf_event(pmc, &attr, flags, eidx, evtdata); - if (ret) - return ret; + if (ret) { + sbiret =3D SBI_ERR_NOT_SUPPORTED; + goto out; + } } =20 set_bit(ctr_idx, kvpmu->pmc_in_use); diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index 7eca72df2cbd..b70179e9e875 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -42,9 +42,9 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, #endif /* * This can fail if perf core framework fails to create an event. - * Forward the error to userspace because it's an error which - * happened within the host kernel. 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Wed, 28 Feb 2024 17:01:55 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 08/15] RISC-V: KVM: Implement SBI PMU Snapshot feature Date: Wed, 28 Feb 2024 17:01:23 -0800 Message-Id: <20240229010130.1380926-9-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PMU Snapshot function allows to minimize the number of traps when the guest access configures/access the hpmcounters. If the snapshot feature is enabled, the hypervisor updates the shared memory with counter data and state of overflown counters. The guest can just read the shared memory instead of trap & emulate done by the hypervisor. This patch doesn't implement the counter overflow yet. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 7 ++ arch/riscv/kvm/vcpu_pmu.c | 120 +++++++++++++++++++++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 3 + drivers/perf/riscv_pmu_sbi.c | 2 +- 4 files changed, 129 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 395518a1664e..586bab84be35 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -50,6 +50,10 @@ struct kvm_pmu { bool init_done; /* Bit map of all the virtual counter used */ DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); + /* The address of the counter snapshot area (guest physical address) */ + gpa_t snapshot_addr; + /* The actual data of the snapshot */ + struct riscv_pmu_snapshot_data *sdata; }; =20 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu_context) @@ -85,6 +89,9 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcp= u, unsigned long ctr_ba int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_pmu_setup_snapshot(struct kvm_vcpu *vcpu, unsigned long= saddr_low, + unsigned long saddr_high, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 29bf4ca798cb..74865e6050a1 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -311,6 +311,81 @@ int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu,= unsigned int csr_num, return ret; } =20 +static void kvm_pmu_clear_snapshot_area(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int snapshot_area_size =3D sizeof(struct riscv_pmu_snapshot_data); + + if (kvpmu->sdata) { + memset(kvpmu->sdata, 0, snapshot_area_size); + if (kvpmu->snapshot_addr !=3D INVALID_GPA) + kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, + kvpmu->sdata, snapshot_area_size); + kfree(kvpmu->sdata); + kvpmu->sdata =3D NULL; + } + kvpmu->snapshot_addr =3D INVALID_GPA; +} + +int kvm_riscv_vcpu_pmu_setup_snapshot(struct kvm_vcpu *vcpu, unsigned long= saddr_low, + unsigned long saddr_high, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int snapshot_area_size =3D sizeof(struct riscv_pmu_snapshot_data); + int sbiret =3D 0; + gpa_t saddr; + unsigned long hva; + bool writable; + + if (!kvpmu) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + if (saddr_low =3D=3D -1 && saddr_high =3D=3D -1) { + kvm_pmu_clear_snapshot_area(vcpu); + return 0; + } + + saddr =3D saddr_low; + + if (saddr_high !=3D 0) { + if (IS_ENABLED(CONFIG_32BIT)) + saddr |=3D ((gpa_t)saddr << 32); + else + sbiret =3D SBI_ERR_INVALID_ADDRESS; + goto out; + } + + if (kvm_is_error_gpa(vcpu->kvm, saddr)) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + hva =3D kvm_vcpu_gfn_to_hva_prot(vcpu, saddr >> PAGE_SHIFT, &writable); + if (kvm_is_error_hva(hva) || !writable) { + sbiret =3D SBI_ERR_INVALID_ADDRESS; + goto out; + } + + kvpmu->snapshot_addr =3D saddr; + kvpmu->sdata =3D kzalloc(snapshot_area_size, GFP_ATOMIC); + if (!kvpmu->sdata) + return -ENOMEM; + + if (kvm_vcpu_write_guest(vcpu, saddr, kvpmu->sdata, snapshot_area_size)) { + kfree(kvpmu->sdata); + kvpmu->snapshot_addr =3D INVALID_GPA; + sbiret =3D SBI_ERR_FAILURE; + } + +out: + retdata->err_val =3D sbiret; + + return 0; +} + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi_return *retdata) { @@ -344,20 +419,33 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcp= u, unsigned long ctr_base, int i, pmc_index, sbiret =3D 0; struct kvm_pmc *pmc; int fevent_code; + bool snap_flag_set =3D flags & SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT; =20 if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret =3D SBI_ERR_INVALID_PARAM; goto out; } =20 + if (snap_flag_set && kvpmu->snapshot_addr =3D=3D INVALID_GPA) { + sbiret =3D SBI_ERR_NO_SHMEM; + goto out; + } + /* Start the counters that have been configured and requested by the gues= t */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { pmc_index =3D i + ctr_base; if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; pmc =3D &kvpmu->pmc[pmc_index]; - if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) + if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) { pmc->counter_val =3D ival; + } else if (snap_flag_set) { + kvm_vcpu_read_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, + sizeof(struct riscv_pmu_snapshot_data)); + /* The counter index in the snapshot are relative to the counter base */ + pmc->counter_val =3D kvpmu->sdata->ctr_values[i]; + } + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { fevent_code =3D get_event_code(pmc->event_idx); if (fevent_code >=3D SBI_PMU_FW_MAX) { @@ -398,14 +486,21 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu= , unsigned long ctr_base, { struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); int i, pmc_index, sbiret =3D 0; + u64 enabled, running; struct kvm_pmc *pmc; int fevent_code; + bool snap_flag_set =3D flags & SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; =20 - if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { + if ((kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0)) { sbiret =3D SBI_ERR_INVALID_PARAM; goto out; } =20 + if (snap_flag_set && kvpmu->snapshot_addr =3D=3D INVALID_GPA) { + sbiret =3D SBI_ERR_NO_SHMEM; + goto out; + } + /* Stop the counters that have been configured and requested by the guest= */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { pmc_index =3D i + ctr_base; @@ -438,9 +533,28 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, } else { sbiret =3D SBI_ERR_INVALID_PARAM; } + + if (snap_flag_set && !sbiret) { + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; + else if (pmc->perf_event) + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, + &enabled, &running); + /* TODO: Add counter overflow support when sscofpmf support is added */ + kvpmu->sdata->ctr_values[i] =3D pmc->counter_val; + kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, + sizeof(struct riscv_pmu_snapshot_data)); + } + if (flags & SBI_PMU_STOP_FLAG_RESET) { pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; clear_bit(pmc_index, kvpmu->pmc_in_use); + if (snap_flag_set) { + /* Clear the snapshot area for the upcoming deletion event */ + kvpmu->sdata->ctr_values[i] =3D 0; + kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, + sizeof(struct riscv_pmu_snapshot_data)); + } } } =20 @@ -566,6 +680,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) kvpmu->num_hw_ctrs =3D num_hw_ctrs + 1; kvpmu->num_fw_ctrs =3D SBI_PMU_FW_MAX; memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); + kvpmu->snapshot_addr =3D INVALID_GPA; =20 if (kvpmu->num_hw_ctrs > RISCV_KVM_MAX_HW_CTRS) { pr_warn_once("Limiting the hardware counters to 32 as specified by the I= SA"); @@ -625,6 +740,7 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) } bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); + kvm_pmu_clear_snapshot_area(vcpu); } =20 void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index b70179e9e875..9f61136e4bb1 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -64,6 +64,9 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, case SBI_EXT_PMU_COUNTER_FW_READ: ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); 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Wed, 28 Feb 2024 17:01:57 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:01:56 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 09/15] RISC-V: KVM: Add perf sampling support for guests Date: Wed, 28 Feb 2024 17:01:24 -0800 Message-Id: <20240229010130.1380926-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM enables perf for guest via counter virtualization. However, the sampling can not be supported as there is no mechanism to enabled trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot to provide the counter overflow data via the shared memory. In case of sampling event, the host first guest the LCOFI interrupt and injects to the guest via irq filtering mechanism defined in AIA specification. Thus, ssaia must be enabled in the host in order to use perf sampling in the guest. No other AIA dpeendancy w.r.t kernel is required. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 3 +- arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 ++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/aia.c | 5 ++ arch/riscv/kvm/vcpu.c | 14 ++++-- arch/riscv/kvm/vcpu_onereg.c | 9 +++- arch/riscv/kvm/vcpu_pmu.c | 72 ++++++++++++++++++++++++--- 7 files changed, 96 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 603e5a3c61f9..c0de2fd6c564 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -168,7 +168,8 @@ #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ (_AC(1, UL) << IRQ_S_TIMER) | \ - (_AC(1, UL) << IRQ_S_EXT)) + (_AC(1, UL) << IRQ_S_EXT) | \ + (_AC(1, UL) << IRQ_PMU_OVF)) =20 /* AIA CSR bits */ #define TOPI_IID_SHIFT 16 diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 586bab84be35..8cb21a4f862c 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -36,6 +36,7 @@ struct kvm_pmc { bool started; /* Monitoring event ID */ unsigned long event_idx; + struct kvm_vcpu *vcpu; }; =20 /* PMU data structure per vcpu */ @@ -50,6 +51,8 @@ struct kvm_pmu { bool init_done; /* Bit map of all the virtual counter used */ DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); + /* Bit map of all the virtual counter overflown */ + DECLARE_BITMAP(pmc_overflown, RISCV_KVM_MAX_COUNTERS); /* The address of the counter snapshot area (guest physical address) */ gpa_t snapshot_addr; /* The actual data of the snapshot */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 7499e88a947c..e8b7545f1803 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -166,6 +166,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZVFH, KVM_RISCV_ISA_EXT_ZVFHMIN, KVM_RISCV_ISA_EXT_ZFA, + KVM_RISCV_ISA_EXT_SSCOFPMF, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index a944294f6f23..0f0a9d11bb5f 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -545,6 +545,9 @@ void kvm_riscv_aia_enable(void) enable_percpu_irq(hgei_parent_irq, irq_get_trigger_type(hgei_parent_irq)); csr_set(CSR_HIE, BIT(IRQ_S_GEXT)); + /* Enable IRQ filtering for overflow interrupt only if sscofpmf is presen= t */ + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) + csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF)); } =20 void kvm_riscv_aia_disable(void) @@ -558,6 +561,8 @@ void kvm_riscv_aia_disable(void) return; hgctrl =3D get_cpu_ptr(&aia_hgei); =20 + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) + csr_clear(CSR_HVIEN, BIT(IRQ_PMU_OVF)); /* Disable per-CPU SGEI interrupt */ csr_clear(CSR_HIE, BIT(IRQ_S_GEXT)); disable_percpu_irq(hgei_parent_irq); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index b5ca9f2e98ac..fcd8ad4de4d2 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -365,6 +365,12 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *v= cpu) } } =20 + /* Sync up the HVIP.LCOFIP bit changes (only clear) by the guest */ + if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { + if (!test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask)) + clear_bit(IRQ_PMU_OVF, v->irqs_pending); + } + /* Sync-up AIA high interrupts */ kvm_riscv_vcpu_aia_sync_interrupts(vcpu); =20 @@ -382,7 +388,8 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu,= unsigned int irq) if (irq < IRQ_LOCAL_MAX && irq !=3D IRQ_VS_SOFT && irq !=3D IRQ_VS_TIMER && - irq !=3D IRQ_VS_EXT) + irq !=3D IRQ_VS_EXT && + irq !=3D IRQ_PMU_OVF) return -EINVAL; =20 set_bit(irq, vcpu->arch.irqs_pending); @@ -397,14 +404,15 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcp= u, unsigned int irq) int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) { /* - * We only allow VS-mode software, timer, and external + * We only allow VS-mode software, timer, counter overflow and external * interrupts when irq is one of the local interrupts * defined by RISC-V privilege specification. */ if (irq < IRQ_LOCAL_MAX && irq !=3D IRQ_VS_SOFT && irq !=3D IRQ_VS_TIMER && - irq !=3D IRQ_VS_EXT) + irq !=3D IRQ_VS_EXT && + irq !=3D IRQ_PMU_OVF) return -EINVAL; =20 clear_bit(irq, vcpu->arch.irqs_pending); diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 5f7355e96008..a072910820c2 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] =3D { /* Multi letter extensions (alphabetically sorted) */ KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -115,6 +116,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned= long ext) case KVM_RISCV_ISA_EXT_I: case KVM_RISCV_ISA_EXT_M: case KVM_RISCV_ISA_EXT_SSTC: + case KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_RISCV_ISA_EXT_SVINVAL: case KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_RISCV_ISA_EXT_ZBA: @@ -171,8 +173,13 @@ void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu) for (i =3D 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) { host_isa =3D kvm_isa_ext_arr[i]; if (__riscv_isa_extension_available(NULL, host_isa) && - kvm_riscv_vcpu_isa_enable_allowed(i)) + kvm_riscv_vcpu_isa_enable_allowed(i)) { + /* Sscofpmf depends on interrupt filtering defined in ssaia */ + if (host_isa =3D=3D RISCV_ISA_EXT_SSCOFPMF && + !__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA)) + continue; set_bit(host_isa, vcpu->arch.isa); + } } } =20 diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 74865e6050a1..a02f7b981005 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -39,7 +39,7 @@ static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc) u64 sample_period; =20 if (!pmc->counter_val) - sample_period =3D counter_val_mask + 1; + sample_period =3D counter_val_mask; else sample_period =3D (-pmc->counter_val) & counter_val_mask; =20 @@ -229,6 +229,47 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pm= u *kvpmu, unsigned long ct return 0; } =20 +static void kvm_riscv_pmu_overflow(struct perf_event *perf_event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct kvm_pmc *pmc =3D perf_event->overflow_handler_context; + struct kvm_vcpu *vcpu =3D pmc->vcpu; + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct riscv_pmu *rpmu =3D to_riscv_pmu(perf_event->pmu); + u64 period; + + /* + * Stop the event counting by directly accessing the perf_event. + * Otherwise, this needs to deferred via a workqueue. + * That will introduce skew in the counter value because the actual + * physical counter would start after returning from this function. + * It will be stopped again once the workqueue is scheduled + */ + rpmu->pmu.stop(perf_event, PERF_EF_UPDATE); + + /* + * The hw counter would start automatically when this function returns. + * Thus, the host may continue to interrupt and inject it to the guest + * even without the guest configuring the next event. Depending on the ha= rdware + * the host may have some sluggishness only if privilege mode filtering i= s not + * available. In an ideal world, where qemu is not the only capable hardw= are, + * this can be removed. + * FYI: ARM64 does this way while x86 doesn't do anything as such. + * TODO: Should we keep it for RISC-V ? + */ + period =3D -(local64_read(&perf_event->count)); + + local64_set(&perf_event->hw.period_left, 0); + perf_event->attr.sample_period =3D period; + perf_event->hw.sample_period =3D period; + + set_bit(pmc->idx, kvpmu->pmc_overflown); + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_PMU_OVF); + + rpmu->pmu.start(perf_event, PERF_EF_RELOAD); +} + static long kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_eve= nt_attr *attr, unsigned long flags, unsigned long eidx, unsigned long evtdata) @@ -248,7 +289,7 @@ static long kvm_pmu_create_perf_event(struct kvm_pmc *p= mc, struct perf_event_att */ attr->sample_period =3D kvm_pmu_get_sample_period(pmc); =20 - event =3D perf_event_create_kernel_counter(attr, -1, current, NULL, pmc); + event =3D perf_event_create_kernel_counter(attr, -1, current, kvm_riscv_p= mu_overflow, pmc); if (IS_ERR(event)) { pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); return PTR_ERR(event); @@ -436,6 +477,8 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu,= unsigned long ctr_base, pmc_index =3D i + ctr_base; if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; + /* The guest started the counter again. Reset the overflow status */ + clear_bit(pmc_index, kvpmu->pmc_overflown); pmc =3D &kvpmu->pmc[pmc_index]; if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) { pmc->counter_val =3D ival; @@ -474,6 +517,10 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu= , unsigned long ctr_base, } } =20 + /* The guest have serviced the interrupt and starting the counter again */ + if (test_bit(IRQ_PMU_OVF, vcpu->arch.irqs_pending)) + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_PMU_OVF); + out: retdata->err_val =3D sbiret; =20 @@ -540,7 +587,13 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, else if (pmc->perf_event) pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &running); - /* TODO: Add counter overflow support when sscofpmf support is added */ + /* + * The counter and overflow indicies in the snapshot region are w.r.to + * cbase. Modify the set bit in the counter mask instead of the pmc_ind= ex + * which indicates the absolute counter index. + */ + if (test_bit(pmc_index, kvpmu->pmc_overflown)) + kvpmu->sdata->ctr_overflow_mask |=3D (1UL << i); kvpmu->sdata->ctr_values[i] =3D pmc->counter_val; kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, sizeof(struct riscv_pmu_snapshot_data)); @@ -549,15 +602,20 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu= , unsigned long ctr_base, if (flags & SBI_PMU_STOP_FLAG_RESET) { pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; clear_bit(pmc_index, kvpmu->pmc_in_use); + clear_bit(pmc_index, kvpmu->pmc_overflown); if (snap_flag_set) { /* Clear the snapshot area for the upcoming deletion event */ kvpmu->sdata->ctr_values[i] =3D 0; + /* + * Only clear the given counter as the caller is responsible to + * validate both the overflow mask and configured counters. + */ + kvpmu->sdata->ctr_overflow_mask &=3D ~(1UL << i); kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, sizeof(struct riscv_pmu_snapshot_data)); } } } - out: retdata->err_val =3D sbiret; =20 @@ -700,6 +758,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) pmc =3D &kvpmu->pmc[i]; pmc->idx =3D i; pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; + pmc->vcpu =3D vcpu; if (i < kvpmu->num_hw_ctrs) { pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_HW; if (i < 3) @@ -732,13 +791,14 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) if (!kvpmu) return; =20 - for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_MAX_COUNTERS) { + for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_KVM_MAX_COUNTERS) { pmc =3D &kvpmu->pmc[i]; pmc->counter_val =3D 0; kvm_pmu_release_perf_event(pmc); pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; } - bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); + bitmap_zero(kvpmu->pmc_in_use, RISCV_KVM_MAX_COUNTERS); + bitmap_zero(kvpmu->pmc_overflown, RISCV_KVM_MAX_COUNTERS); memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); kvm_pmu_clear_snapshot_area(vcpu); } --=20 2.34.1 From nobody Sun Feb 8 10:03:18 2026 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F7235336A for ; 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Wed, 28 Feb 2024 17:01:58 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:01:58 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Albert Ou , Alexandre Ghiti , Andrew Jones , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 10/15] RISC-V: KVM: Support 64 bit firmware counters on RV32 Date: Wed, 28 Feb 2024 17:01:25 -0800 Message-Id: <20240229010130.1380926-11-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware counters for RV32 based systems. Add infrastructure to support that. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 ++- arch/riscv/kvm/vcpu_pmu.c | 37 ++++++++++++++++++++++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 +++++ 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 8cb21a4f862c..e0ad27dea46c 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -20,7 +20,7 @@ static_assert(RISCV_KVM_MAX_COUNTERS <=3D 64); =20 struct kvm_fw_event { /* Current value of the event */ - unsigned long value; + u64 value; =20 /* Event monitoring status */ bool started; @@ -91,6 +91,8 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcp= u, unsigned long ctr_ba struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long= cidx, + struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_pmu_setup_snapshot(struct kvm_vcpu *vcpu, unsigned long= saddr_low, unsigned long saddr_high, unsigned long flags, diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index a02f7b981005..469bb430cf97 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -196,6 +196,29 @@ static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsi= gned long eidx, return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask); } =20 +static int pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, + unsigned long *out_val) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + int fevent_code; + + if (!IS_ENABLED(CONFIG_32BIT)) + return -EINVAL; + + pmc =3D &kvpmu->pmc[cidx]; + + if (pmc->cinfo.type !=3D SBI_PMU_CTR_TYPE_FW) + return -EINVAL; + + fevent_code =3D get_event_code(pmc->event_idx); + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; + + *out_val =3D pmc->counter_val >> 32; + + return 0; +} + static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, unsigned long *out_val) { @@ -702,6 +725,18 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *= vcpu, unsigned long ctr_ba return 0; } =20 +int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long= cidx, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret; + + ret =3D pmu_fw_ctr_read_hi(vcpu, cidx, &retdata->out_val); + if (ret =3D=3D -EINVAL) + retdata->err_val =3D SBI_ERR_INVALID_PARAM; + + return 0; +} + int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata) { @@ -775,7 +810,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) pmc->cinfo.csr =3D CSR_CYCLE + i; } else { pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_FW; - pmc->cinfo.width =3D BITS_PER_LONG - 1; + pmc->cinfo.width =3D 63; } } =20 diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index 9f61136e4bb1..58a0e5587e2a 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -64,6 +64,12 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, case SBI_EXT_PMU_COUNTER_FW_READ: ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); 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Wed, 28 Feb 2024 17:02:00 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 11/15] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Date: Wed, 28 Feb 2024 17:01:26 -0800 Message-Id: <20240229010130.1380926-12-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The KVM RISC-V allows Sscofpmf extension for Guest/VM so let us add this extension to get-reg-list test. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones Reviewed-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 8cece02ca23a..ca6d98a5dce5 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -43,6 +43,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _V: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSAIA: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVNAPOT: @@ -406,6 +407,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_o= ff) KVM_ISA_EXT_ARR(V), KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -927,6 +929,7 @@ KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); 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Wed, 28 Feb 2024 17:02:02 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:02:01 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 12/15] KVM: riscv: selftests: Add SBI PMU extension definitions Date: Wed, 28 Feb 2024 17:01:27 -0800 Message-Id: <20240229010130.1380926-13-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SBI PMU extension definition is required for upcoming SBI PMU selftests. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- .../selftests/kvm/include/riscv/processor.h | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index f75c381fa35a..a49a39c8e8d4 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -169,17 +169,84 @@ void vm_install_exception_handler(struct kvm_vm *vm, = int vector, exception_handl enum sbi_ext_id { SBI_EXT_BASE =3D 0x10, SBI_EXT_STA =3D 0x535441, + SBI_EXT_PMU =3D 0x504D55, }; =20 enum sbi_ext_base_fid { SBI_EXT_BASE_PROBE_EXT =3D 3, }; =20 +enum sbi_ext_pmu_fid { + SBI_EXT_PMU_NUM_COUNTERS =3D 0, + SBI_EXT_PMU_COUNTER_GET_INFO, + SBI_EXT_PMU_COUNTER_CFG_MATCH, + SBI_EXT_PMU_COUNTER_START, + SBI_EXT_PMU_COUNTER_STOP, + SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, +}; + +union sbi_pmu_ctr_info { + unsigned long value; + struct { + unsigned long csr:12; + unsigned long width:6; +#if __riscv_xlen =3D=3D 32 + unsigned long reserved:13; +#else + unsigned long reserved:45; +#endif + unsigned long type:1; + }; +}; + struct sbiret { long error; long value; }; =20 +/** General pmu event codes specified in SBI PMU extension */ +enum sbi_pmu_hw_generic_events_t { + SBI_PMU_HW_NO_EVENT =3D 0, + SBI_PMU_HW_CPU_CYCLES =3D 1, + SBI_PMU_HW_INSTRUCTIONS =3D 2, + SBI_PMU_HW_CACHE_REFERENCES =3D 3, + SBI_PMU_HW_CACHE_MISSES =3D 4, + SBI_PMU_HW_BRANCH_INSTRUCTIONS =3D 5, + SBI_PMU_HW_BRANCH_MISSES =3D 6, + SBI_PMU_HW_BUS_CYCLES =3D 7, + SBI_PMU_HW_STALLED_CYCLES_FRONTEND =3D 8, + SBI_PMU_HW_STALLED_CYCLES_BACKEND =3D 9, + SBI_PMU_HW_REF_CPU_CYCLES =3D 10, + + SBI_PMU_HW_GENERAL_MAX, +}; + +/* SBI PMU counter types */ +enum sbi_pmu_ctr_type { + SBI_PMU_CTR_TYPE_HW =3D 0x0, + SBI_PMU_CTR_TYPE_FW, +}; + +/* Flags defined for config matching function */ +#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) +#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) +#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) +#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) +#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) +#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) +#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) + +/* Flags defined for counter start function */ +#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT BIT(1) + +/* Flags defined for counter stop function */ +#define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) + struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, --=20 2.34.1 From nobody Sun Feb 8 10:03:19 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92D0A54FB5 for ; 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Wed, 28 Feb 2024 17:02:03 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:02:03 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 13/15] KVM: riscv: selftests: Add SBI PMU selftest Date: Wed, 28 Feb 2024 17:01:28 -0800 Message-Id: <20240229010130.1380926-14-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This test implements basic sanity test and cycle/instret event counting tests. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- tools/testing/selftests/kvm/Makefile | 1 + tools/testing/selftests/kvm/riscv/sbi_pmu.c | 340 ++++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 tools/testing/selftests/kvm/riscv/sbi_pmu.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 426f85798aea..b2dce6843b9e 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -195,6 +195,7 @@ TEST_GEN_PROGS_riscv +=3D kvm_create_max_vcpus TEST_GEN_PROGS_riscv +=3D kvm_page_table_test TEST_GEN_PROGS_riscv +=3D set_memory_region_test TEST_GEN_PROGS_riscv +=3D steal_time +TEST_GEN_PROGS_riscv +=3D riscv/sbi_pmu =20 SPLIT_TESTS +=3D arch_timer SPLIT_TESTS +=3D get-reg-list diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu.c b/tools/testing/se= lftests/kvm/riscv/sbi_pmu.c new file mode 100644 index 000000000000..fc1fc5eea99e --- /dev/null +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * arch_timer.c - Tests the riscv64 sstc timer IRQ functionality + * + * The test validates the sstc timer IRQs using vstimecmp registers. + * It's ported from the aarch64 arch_timer test. + * + * Copyright (c) 2024, Rivos Inc. + */ + +#include +#include +#include +#include +#include +#include "kvm_util.h" +#include "test_util.h" +#include "processor.h" + +/* Maximum counters (firmware + hardware)*/ +#define RISCV_MAX_PMU_COUNTERS 64 +union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; + +/* Cache the available counters in a bitmask */ +static unsigned long counter_mask_available; + +unsigned long pmu_csr_read_num(int csr_num) +{ +#define switchcase_csr_read(__csr_num, __val) {\ + case __csr_num: \ + __val =3D csr_read(__csr_num); \ + break; } +#define switchcase_csr_read_2(__csr_num, __val) {\ + switchcase_csr_read(__csr_num + 0, __val) \ + switchcase_csr_read(__csr_num + 1, __val)} +#define switchcase_csr_read_4(__csr_num, __val) {\ + switchcase_csr_read_2(__csr_num + 0, __val) \ + switchcase_csr_read_2(__csr_num + 2, __val)} +#define switchcase_csr_read_8(__csr_num, __val) {\ + switchcase_csr_read_4(__csr_num + 0, __val) \ + switchcase_csr_read_4(__csr_num + 4, __val)} +#define switchcase_csr_read_16(__csr_num, __val) {\ + switchcase_csr_read_8(__csr_num + 0, __val) \ + switchcase_csr_read_8(__csr_num + 8, __val)} +#define switchcase_csr_read_32(__csr_num, __val) {\ + switchcase_csr_read_16(__csr_num + 0, __val) \ + switchcase_csr_read_16(__csr_num + 16, __val)} + + unsigned long ret =3D 0; + + switch (csr_num) { + switchcase_csr_read_32(CSR_CYCLE, ret) + switchcase_csr_read_32(CSR_CYCLEH, ret) + default : + break; + } + + return ret; +#undef switchcase_csr_read_32 +#undef switchcase_csr_read_16 +#undef switchcase_csr_read_8 +#undef switchcase_csr_read_4 +#undef switchcase_csr_read_2 +#undef switchcase_csr_read +} + +static inline void dummy_func_loop(int iter) +{ + int i =3D 0; + + while (i < iter) { + asm volatile("nop"); + i++; + } +} + +static void guest_illegal_exception_handler(struct ex_regs *regs) +{ + __GUEST_ASSERT(regs->cause =3D=3D EXC_INST_ILLEGAL, + "Unexpected exception handler %lx\n", regs->cause); + + /* skip the trapping instruction */ + regs->epc +=3D 4; +} + +static unsigned long get_counter_index(unsigned long cbase, unsigned long = cmask, + unsigned long cflags, + unsigned long event) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmas= k, + cflags, event, 0, 0); + __GUEST_ASSERT(ret.error =3D=3D 0, "config matching failed %ld\n", ret.er= ror); + GUEST_ASSERT((ret.value < RISCV_MAX_PMU_COUNTERS) && + ((1UL << ret.value) & counter_mask_available)); + + return ret.value; +} + +static unsigned long get_num_counters(void) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0= ); + + __GUEST_ASSERT(ret.error =3D=3D 0, "Unable to retrieve number of counters= from SBI PMU"); + + __GUEST_ASSERT(ret.value < RISCV_MAX_PMU_COUNTERS, + "Invalid number of counters %ld\n", ret.value); + + return ret.value; +} + +static void update_counter_info(int num_counters) +{ + int i =3D 0; + struct sbiret ret; + + for (i =3D 0; i < num_counters; i++) { + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0,= 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (!ret.error) + GUEST_ASSERT_NE(ret.value, 0); + + ctrinfo_arr[i].value =3D ret.value; + counter_mask_available |=3D BIT(i); + } + + GUEST_ASSERT(counter_mask_available > 0); +} + +static unsigned long read_counter(int idx, union sbi_pmu_ctr_info ctrinfo) +{ + unsigned long counter_val =3D 0; + struct sbiret ret; + + __GUEST_ASSERT(ctrinfo.type < 2, "Invalid counter type %d", ctrinfo.type); + + if (ctrinfo.type =3D=3D SBI_PMU_CTR_TYPE_HW) { + counter_val =3D pmu_csr_read_num(ctrinfo.csr); + } else if (ctrinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, idx, 0, 0, 0= , 0, 0); + GUEST_ASSERT(ret.error =3D=3D 0); + counter_val =3D ret.value; + } + + return counter_val; +} + +static void start_counter(unsigned long counter, unsigned long start_flags, + unsigned long ival) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, counter, 1, sta= rt_flags, + ival, 0, 0); + __GUEST_ASSERT(ret.error =3D=3D 0, "Unable to start counter %ld\n", count= er); +} + +static void stop_counter(unsigned long counter, unsigned long stop_flags) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop= _flags, + 0, 0, 0); + if (stop_flags & SBI_PMU_STOP_FLAG_RESET) + __GUEST_ASSERT(ret.error =3D=3D SBI_ERR_ALREADY_STOPPED, + "Unable to stop counter %ld\n", counter); + else + __GUEST_ASSERT(ret.error =3D=3D 0, "Unable to stop counter %ld error %ld= \n", + counter, ret.error); +} + +static void test_pmu_event(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_pre, counter_value_post; + unsigned long counter_init_value =3D 100; + + counter =3D get_counter_index(0, counter_mask_available, 0, event); + counter_value_pre =3D read_counter(counter, ctrinfo_arr[counter]); + + /* Do not set the initial value */ + start_counter(counter, 0, counter_init_value); + dummy_func_loop(10000); + + stop_counter(counter, 0); + + counter_value_post =3D read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_value_pre, + "counter_value_post %lx counter_value_pre %lx\n", + counter_value_post, counter_value_pre); + + /* Now set the initial value and compare */ + start_counter(counter, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_init_va= lue); + dummy_func_loop(10000); + + stop_counter(counter, 0); + + counter_value_post =3D read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_init_value, + "counter_value_post %lx counter_init_value %lx\n", + counter_value_post, counter_init_value); + + stop_counter(counter, SBI_PMU_STOP_FLAG_RESET); +} + +static void test_invalid_event(void) +{ + struct sbiret ret; + unsigned long event =3D 0x1234; /* A random event */ + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, 0, + counter_mask_available, 0, event, 0, 0); + GUEST_ASSERT_EQ(ret.error, SBI_ERR_NOT_SUPPORTED); +} + +static void test_pmu_events(int cpu) +{ + int num_counters =3D 0; + + /* Get the counter details */ + num_counters =3D get_num_counters(); + update_counter_info(num_counters); + + /* Sanity testing for any random invalid event */ + test_invalid_event(); + + /* Only these two events are guranteed to be present */ + test_pmu_event(SBI_PMU_HW_CPU_CYCLES); + test_pmu_event(SBI_PMU_HW_INSTRUCTIONS); + + GUEST_DONE(); +} + +static void test_pmu_basic_sanity(int cpu) +{ + long out_val =3D 0; + bool probe; + struct sbiret ret; + int num_counters =3D 0, i; + unsigned long counter_val =3D -1; + union sbi_pmu_ctr_info ctrinfo; + + probe =3D guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val =3D=3D 1); + + num_counters =3D get_num_counters(); + + for (i =3D 0; i < num_counters; i++) { + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, + 0, 0, 0, 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (!ret.error) + GUEST_ASSERT_NE(ret.value, 0); + else + continue; + + ctrinfo.value =3D ret.value; + + /* Accesibility check of hardware and read capability of firmware counte= rs */ + counter_val =3D read_counter(i, ctrinfo); + /* The spec doesn't mandate any initial value. Verify if a sane value */ + GUEST_ASSERT_NE(counter_val, -1); + } + + GUEST_DONE(); +} + +static void run_vcpu(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + case UCALL_DONE: + case UCALL_SYNC: + break; + default: + TEST_FAIL("Unknown ucall %lu", uc.cmd); + break; + } +} + +void test_vm_destroy(struct kvm_vm *vm) +{ + memset(ctrinfo_arr, 0, sizeof(union sbi_pmu_ctr_info) * RISCV_MAX_PMU_COU= NTERS); + counter_mask_available =3D 0; + kvm_vm_free(vm); +} + +static void test_vm_basic_test(void *guest_code) +{ + struct kvm_vm *vm; + struct kvm_vcpu *vcpu; + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(KVM_RISCV_SBI_EXT_P= MU)), + "SBI PMU not available, skipping test"); + vm_init_vector_tables(vm); + /* Illegal instruction handler is required to verify read access without = configuration */ + vm_install_exception_handler(vm, EXC_INST_ILLEGAL, guest_illegal_exceptio= n_handler); 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Wed, 28 Feb 2024 17:02:05 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:02:05 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 14/15] KVM: riscv: selftests: Add a test for PMU snapshot functionality Date: Wed, 28 Feb 2024 17:01:29 -0800 Message-Id: <20240229010130.1380926-15-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- .../selftests/kvm/include/riscv/processor.h | 25 ++++ .../selftests/kvm/lib/riscv/processor.c | 12 ++ tools/testing/selftests/kvm/riscv/sbi_pmu.c | 124 ++++++++++++++++++ 3 files changed, 161 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index a49a39c8e8d4..e114d039e87b 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -173,6 +173,7 @@ enum sbi_ext_id { }; =20 enum sbi_ext_base_fid { + SBI_EXT_BASE_GET_IMP_VERSION =3D 2, SBI_EXT_BASE_PROBE_EXT =3D 3, }; =20 @@ -201,6 +202,12 @@ union sbi_pmu_ctr_info { }; }; =20 +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + struct sbiret { long error; long value; @@ -247,6 +254,14 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_STOP_FLAG_RESET (1 << 0) #define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) =20 +#define SBI_STA_SHMEM_DISABLE -1 + +/* SBI spec version fields */ +#define SBI_SPEC_VERSION_DEFAULT 0x1 +#define SBI_SPEC_VERSION_MAJOR_SHIFT 24 +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff + struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, @@ -254,6 +269,16 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned lon= g arg0, =20 bool guest_sbi_probe_extension(int extid, long *out_val); =20 +/* Make SBI version */ +static inline unsigned long sbi_mk_version(unsigned long major, + unsigned long minor) +{ + return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << + SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; +} + +unsigned long get_host_sbi_impl_version(void); + static inline void local_irq_enable(void) { csr_set(CSR_SSTATUS, SR_SIE); diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index ec66d331a127..b0162d923e38 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -499,3 +499,15 @@ bool guest_sbi_probe_extension(int extid, long *out_va= l) =20 return true; } + +unsigned long get_host_sbi_impl_version(void) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0, + 0, 0, 0, 0, 0); + + GUEST_ASSERT(!ret.error); + + return ret.value; +} diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu.c b/tools/testing/se= lftests/kvm/riscv/sbi_pmu.c index fc1fc5eea99e..8ea2a6db6610 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu.c @@ -21,6 +21,11 @@ #define RISCV_MAX_PMU_COUNTERS 64 union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; =20 +/* Snapshot shared memory data */ +#define PMU_SNAPSHOT_GPA_BASE (1 << 30) +static void *snapshot_gva; +static vm_paddr_t snapshot_gpa; + /* Cache the available counters in a bitmask */ static unsigned long counter_mask_available; =20 @@ -173,6 +178,20 @@ static void stop_counter(unsigned long counter, unsign= ed long stop_flags) counter, ret.error); } =20 +static void snapshot_set_shmem(vm_paddr_t gpa, unsigned long flags) +{ + unsigned long lo =3D (unsigned long)gpa; +#if __riscv_xlen =3D=3D 32 + unsigned long hi =3D (unsigned long)(gpa >> 32); +#else + unsigned long hi =3D gpa =3D=3D -1 ? -1 : 0; +#endif + struct sbiret ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHM= EM, + lo, hi, flags, 0, 0, 0); + + GUEST_ASSERT(ret.value =3D=3D 0 && ret.error =3D=3D 0); +} + static void test_pmu_event(unsigned long event) { unsigned long counter; @@ -207,6 +226,43 @@ static void test_pmu_event(unsigned long event) stop_counter(counter, SBI_PMU_STOP_FLAG_RESET); } =20 +static void test_pmu_event_snapshot(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_pre, counter_value_post; + unsigned long counter_init_value =3D 100; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + + counter =3D get_counter_index(0, counter_mask_available, 0, event); + counter_value_pre =3D read_counter(counter, ctrinfo_arr[counter]); + + /* Do not set the initial value */ + start_counter(counter, 0, 0); + dummy_func_loop(10000); + + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + /* The counter value is updated w.r.t relative index of cbase */ + counter_value_post =3D READ_ONCE(snapshot_data->ctr_values[0]); + __GUEST_ASSERT(counter_value_post > counter_value_pre, + "counter_value_post %lx counter_value_pre %lx\n", + counter_value_post, counter_value_pre); + + /* Now set the initial value and compare */ + WRITE_ONCE(snapshot_data->ctr_values[0], counter_init_value); + start_counter(counter, SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT, 0); + dummy_func_loop(10000); + + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + counter_value_post =3D READ_ONCE(snapshot_data->ctr_values[0]); + __GUEST_ASSERT(counter_value_post > counter_init_value, + "counter_value_post %lx counter_init_value %lx for counter\n", + counter_value_post, counter_init_value); + + stop_counter(counter, SBI_PMU_STOP_FLAG_RESET); +} + static void test_invalid_event(void) { struct sbiret ret; @@ -270,6 +326,41 @@ static void test_pmu_basic_sanity(int cpu) GUEST_DONE(); } =20 +static void test_pmu_events_snaphost(int cpu) +{ + long out_val =3D 0; + bool probe; + int num_counters =3D 0; + unsigned long sbi_impl_version; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + int i; + + probe =3D guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val =3D=3D 1); + + sbi_impl_version =3D get_host_sbi_impl_version(); + if (sbi_impl_version >=3D sbi_mk_version(2, 0)) + __GUEST_ASSERT(0, "SBI implementation version doesn't support PMU Snapsh= ot"); + + snapshot_set_shmem(snapshot_gpa, 0); + + /* Get the counter details */ + num_counters =3D get_num_counters(); + update_counter_info(num_counters); + + /* Validate shared memory access */ + GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_overflow_mask), 0); + for (i =3D 0; i < num_counters; i++) { + if (counter_mask_available & (1UL << i)) + GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_values[i]), 0); + } + /* Only these two events are guranteed to be present */ + test_pmu_event_snapshot(SBI_PMU_HW_CPU_CYCLES); + test_pmu_event_snapshot(SBI_PMU_HW_INSTRUCTIONS); + + GUEST_DONE(); +} + static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -328,6 +419,36 @@ static void test_vm_events_test(void *guest_code) test_vm_destroy(vm); } =20 +static void test_vm_setup_snapshot_mem(struct kvm_vm *vm, struct kvm_vcpu = *vcpu) +{ + vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, PMU_SNAPSHOT_GPA_BA= SE, 1, 1, 0); + /* PMU Snapshot requires single page only */ + virt_map(vm, PMU_SNAPSHOT_GPA_BASE, PMU_SNAPSHOT_GPA_BASE, 1); + + /* PMU_SNAPSHOT_GPA_BASE is identity mapped */ + snapshot_gva =3D (void *)(PMU_SNAPSHOT_GPA_BASE); + snapshot_gpa =3D addr_gva2gpa(vcpu->vm, (vm_vaddr_t)snapshot_gva); + sync_global_to_guest(vcpu->vm, snapshot_gva); + sync_global_to_guest(vcpu->vm, snapshot_gpa); +} + +static void test_vm_events_snapshot_test(void *guest_code) +{ + struct kvm_vm *vm =3D NULL; + struct kvm_vcpu *vcpu =3D NULL; + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(KVM_RISCV_SBI_EXT_P= MU)), + "SBI PMU not available, skipping test"); + + test_vm_setup_snapshot_mem(vm, vcpu); + + vcpu_args_set(vcpu, 1, 0); + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + int main(void) { test_vm_basic_test(test_pmu_basic_sanity); @@ -336,5 +457,8 @@ int main(void) test_vm_events_test(test_pmu_events); pr_info("SBI PMU event verification test : PASS\n"); =20 + test_vm_events_snapshot_test(test_pmu_events_snaphost); + pr_info("SBI PMU event verification with snapshot test : PASS\n"); + return 0; } --=20 2.34.1 From nobody Sun Feb 8 10:03:19 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D495654FA5 for ; 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Wed, 28 Feb 2024 17:02:07 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:02:07 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Conor Dooley , Guo Ren , Icenowy Zheng , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Will Deacon Subject: [PATCH v4 15/15] KVM: riscv: selftests: Add a test for counter overflow Date: Wed, 28 Feb 2024 17:01:30 -0800 Message-Id: <20240229010130.1380926-16-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a test for verifying overflow interrupt. Currently, it relies on overflow support on cycle/instret events. This test works for cycle/ instret events which support sampling via hpmcounters on the platform. There are no ISA extensions to detect if a platform supports that. Thus, this test will fail on platform with virtualization but doesn't support overflow on these two events. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- tools/testing/selftests/kvm/riscv/sbi_pmu.c | 126 +++++++++++++++++++- 1 file changed, 125 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu.c b/tools/testing/se= lftests/kvm/riscv/sbi_pmu.c index 8ea2a6db6610..c0264c636054 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu.c @@ -8,6 +8,7 @@ * Copyright (c) 2024, Rivos Inc. */ =20 +#include "asm/csr.h" #include #include #include @@ -16,6 +17,7 @@ #include "kvm_util.h" #include "test_util.h" #include "processor.h" +#include "arch_timer.h" =20 /* Maximum counters (firmware + hardware)*/ #define RISCV_MAX_PMU_COUNTERS 64 @@ -26,6 +28,11 @@ union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTER= S]; static void *snapshot_gva; static vm_paddr_t snapshot_gpa; =20 +static int pmu_irq =3D IRQ_PMU_OVF; + +static int vcpu_shared_irq_count; +static int counter_in_use; + /* Cache the available counters in a bitmask */ static unsigned long counter_mask_available; =20 @@ -69,7 +76,9 @@ unsigned long pmu_csr_read_num(int csr_num) #undef switchcase_csr_read } =20 -static inline void dummy_func_loop(int iter) +static void stop_counter(unsigned long counter, unsigned long stop_flags); + +static inline void dummy_func_loop(uint64_t iter) { int i =3D 0; =20 @@ -88,6 +97,26 @@ static void guest_illegal_exception_handler(struct ex_re= gs *regs) regs->epc +=3D 4; } =20 +static void guest_irq_handler(struct ex_regs *regs) +{ + unsigned int irq_num =3D regs->cause & ~CAUSE_IRQ_FLAG; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + unsigned long overflown_mask; + + /* Stop all counters first to avoid further interrupts */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, 1UL << counter_in_use, + SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT, 0, 0, 0); + + csr_clear(CSR_SIP, BIT(pmu_irq)); + + overflown_mask =3D READ_ONCE(snapshot_data->ctr_overflow_mask); + GUEST_ASSERT(overflown_mask & (1UL << counter_in_use)); + + /* Validate that we are in the correct irq handler */ + GUEST_ASSERT_EQ(irq_num, pmu_irq); + WRITE_ONCE(vcpu_shared_irq_count, vcpu_shared_irq_count+1); +} + static unsigned long get_counter_index(unsigned long cbase, unsigned long = cmask, unsigned long cflags, unsigned long event) @@ -263,6 +292,32 @@ static void test_pmu_event_snapshot(unsigned long even= t) stop_counter(counter, SBI_PMU_STOP_FLAG_RESET); } =20 +static void test_pmu_event_overflow(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_post; + unsigned long counter_init_value =3D ULONG_MAX - 10000; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + + counter =3D get_counter_index(0, counter_mask_available, 0, event); + counter_in_use =3D counter; + + /* The counter value is updated w.r.t relative index of cbase passed to s= tart/stop */ + WRITE_ONCE(snapshot_data->ctr_values[0], counter_init_value); + start_counter(counter, SBI_PMU_START_FLAG_INIT_FROM_SNAPSHOT, 0); + dummy_func_loop(10000); + udelay(msecs_to_usecs(2000)); + /* irq handler should have stopped the counter */ + + counter_value_post =3D READ_ONCE(snapshot_data->ctr_values[counter_in_use= ]); + /* The counter value after stopping should be less the init value due to = overflow */ + __GUEST_ASSERT(counter_value_post < counter_init_value, + "counter_value_post %lx counter_init_value %lx for counter\n", + counter_value_post, counter_init_value); + + stop_counter(counter, SBI_PMU_STOP_FLAG_RESET); +} + static void test_invalid_event(void) { struct sbiret ret; @@ -361,6 +416,43 @@ static void test_pmu_events_snaphost(int cpu) GUEST_DONE(); } =20 +static void test_pmu_events_overflow(int cpu) +{ + long out_val =3D 0; + bool probe; + int num_counters =3D 0; + unsigned long sbi_impl_version; + + probe =3D guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val =3D=3D 1); + + sbi_impl_version =3D get_host_sbi_impl_version(); + if (sbi_impl_version >=3D sbi_mk_version(2, 0)) + __GUEST_ASSERT(0, "SBI implementation version doesn't support PMU Snapsh= ot"); + + snapshot_set_shmem(snapshot_gpa, 0); + csr_set(CSR_IE, BIT(pmu_irq)); + local_irq_enable(); + + /* Get the counter details */ + num_counters =3D get_num_counters(); + update_counter_info(num_counters); + + /* + * Qemu supports overflow for cycle/instruction. + * This test may fail on any platform that do not support overflow for th= ese two events. + */ + test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, 1); + + /* Renable the interrupt again for another event */ + csr_set(CSR_IE, BIT(pmu_irq)); + test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, 2); + + GUEST_DONE(); +} + static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -449,6 +541,35 @@ static void test_vm_events_snapshot_test(void *guest_c= ode) test_vm_destroy(vm); } =20 +static void test_vm_events_overflow(void *guest_code) +{ + struct kvm_vm *vm =3D NULL; + struct kvm_vcpu *vcpu =3D NULL; + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(KVM_RISCV_SBI_EXT_P= MU)), + "SBI PMU not available, skipping test"); + + __TEST_REQUIRE(__vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(KVM_RISCV_ISA_EXT_S= SCOFPMF)), + "Sscofpmf is not available, skipping overflow test"); + + + test_vm_setup_snapshot_mem(vm, vcpu); + vm_init_vector_tables(vm); + vm_install_interrupt_handler(vm, guest_irq_handler); + + vcpu_init_vector_tables(vcpu); + /* Initialize guest timer frequency. */ + vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency), &timer_freq); + sync_global_to_guest(vm, timer_freq); + + vcpu_args_set(vcpu, 1, 0); + + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + int main(void) { test_vm_basic_test(test_pmu_basic_sanity); @@ -460,5 +581,8 @@ int main(void) test_vm_events_snapshot_test(test_pmu_events_snaphost); pr_info("SBI PMU event verification with snapshot test : PASS\n"); =20 + test_vm_events_overflow(test_pmu_events_overflow); + pr_info("SBI PMU event verification with overflow test : PASS\n"); + return 0; } --=20 2.34.1