From nobody Sun Feb 8 10:43:41 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF5427C6D2; Thu, 29 Feb 2024 11:41:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709206909; cv=none; b=KofrE2jrrCmYZ92Uislh7UXlB22n554Xf7OSw0MxGqygyO0iwzh+2Rk6qbM8wspkOAQcPKXzF+pyaAydDjqsyxI/iHDY9EMaqkECRkiSsk5nFOFv2DGaRMVqKW5gipubb2qeBmAEefIv7Wt8YI43cqHiopNEhsK4B+WDT0+ujNQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709206909; c=relaxed/simple; bh=okvhTFBRLW4R7YsUbijePM2TCWLMQsafMS/zHyX7gbA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Ir1aIxx8J0uv2xAwVhgGuSdT+xZJ49pFIGEAHvwiagghPnpRpoGggflh7BUJNCxGyaxBsTWWaCluxvUfiZC6t35jdJdmmcfHk/oHc/aw2WxJkeIvY7zNtdD/0cWy/xf1QQst1X0MYzildbfARRL4Tsr9s2/6P0dXoAMyhktQHQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=NNZbJ/9t; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="NNZbJ/9t" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1709206907; x=1740742907; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=okvhTFBRLW4R7YsUbijePM2TCWLMQsafMS/zHyX7gbA=; b=NNZbJ/9tpJFaweG7svxcVdENvn41ZCv0vaB1MQzAuSftp44ksAiNJiEY XMsovhp8vctBs7zEZTxxHAZnWQ2B7GISEVzQVrnjrP6YMNJtLZglKolQp ge8L63NMlt8eGJdOc6UF3HeAMB6TWM8PH5PlcOxurypvNPOzn1XgzUcav tHd0H8zqLGdyxEthESpXPGf3Uc59DE+3qQbHBVx332ev9CbThXCflHVIU oiyhIHT5YlJMMfNws7oyx28sV6H1PRhLJTIEjFEjOpmyge1qrdz3Jl79Q Umc1nhb2u0Ne9tROwYGkmVrvcsTKV3LUnnKGJ14/NyV014F2C1Gge+JiY g==; X-CSE-ConnectionGUID: 3CkcnVRnRlyAYMMQwYqwlA== X-CSE-MsgGUID: EU6h/PGDTPyePZNLbNrRIg== X-IronPort-AV: E=Sophos;i="6.06,194,1705388400"; d="scan'208";a="17008186" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Feb 2024 04:41:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 29 Feb 2024 04:41:37 -0700 Received: from [127.0.1.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 29 Feb 2024 04:41:33 -0700 From: Balakrishnan Sambath Date: Thu, 29 Feb 2024 17:09:30 +0530 Subject: [PATCH 1/3] ARM: dts: microchip: sama5d2: Move pinfunc.h headers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240229-pio4-pinctrl-yaml-v1-1-c4d8279c083f@microchip.com> References: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> In-Reply-To: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Linus Walleij CC: , , , , "Balakrishnan Sambath" X-Mailer: b4 0.13.0 Move sama5d2-pinfunc.h into include/dt-bindings/pinctrl so that we can include it in yaml dt-binding examples. Signed-off-by: Balakrishnan Sambath --- arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi | = 2 +- arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi | = 2 +- arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi | = 2 +- arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts | = 2 +- arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts | = 2 +- arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts | = 2 +- arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts | = 2 +- .../dts/microchip =3D> include/dt-bindings/pinctrl}/sama5d2-pinfunc.h = | 0 8 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi b/arch/ar= m/boot/dts/microchip/at91-kizbox3_common.dtsi index 465664628419..30a0119d260e 100644 --- a/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi @@ -11,7 +11,7 @@ */ /dts-v1/; #include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" +#include #include #include #include diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi b/arch/arm= /boot/dts/microchip/at91-sama5d27_som1.dtsi index 95ecb7d040a8..6c8f658ec51c 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi @@ -7,7 +7,7 @@ * 2017 Claudiu Beznea */ #include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" +#include #include =20 / { diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi b/arch/a= rm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi index 4617805c7748..6b8e688bb98a 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi @@ -8,7 +8,7 @@ * Author: Eugen Hristev */ #include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" +#include #include #include #include diff --git a/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts b/arch= /arm/boot/dts/microchip/at91-sama5d29_curiosity.dts index 6b02b7bcfd49..944cc68784a4 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts @@ -9,7 +9,7 @@ */ /dts-v1/; #include "sama5d29.dtsi" -#include "sama5d2-pinfunc.h" +#include #include #include #include diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts b/arch/arm/bo= ot/dts/microchip/at91-sama5d2_icp.dts index 999adeca6f33..62d331db8dd5 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts @@ -10,7 +10,7 @@ */ /dts-v1/; #include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" +#include #include #include #include diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts b/arch/arm= /boot/dts/microchip/at91-sama5d2_ptc_ek.dts index 200b20515ab1..28df6bc7b28f 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts @@ -8,7 +8,7 @@ */ /dts-v1/; #include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" +#include #include #include #include diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts b/arch/a= rm/boot/dts/microchip/at91-sama5d2_xplained.dts index 6680031387e8..60adaae39c83 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts @@ -7,7 +7,7 @@ */ /dts-v1/; #include "sama5d2.dtsi" -#include "sama5d2-pinfunc.h" +#include #include #include #include diff --git a/arch/arm/boot/dts/microchip/sama5d2-pinfunc.h b/include/dt-bin= dings/pinctrl/sama5d2-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/microchip/sama5d2-pinfunc.h rename to include/dt-bindings/pinctrl/sama5d2-pinfunc.h --=20 2.25.1 From nobody Sun Feb 8 10:43:41 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0713B7C0A1; Thu, 29 Feb 2024 11:42:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709206950; cv=none; b=IRpdJmQkz10c+LJsdy7vkH7WgtY5kKZH2riR9kk308KGJqqQmA2G0e8y1wcNchARTiTU6LgAKeqgSCQdcZ9tbu7nKo6dSvNTh/b4tyvoNsZUrdXeooB6567BSkdnpk81Oo8V9k9klTE/fsQ+exg0KTZduFU5cCc0CNA4Ta40paI= ARC-Message-Signature: i=1; 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Thu, 29 Feb 2024 04:41:41 -0700 Received: from [127.0.1.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 29 Feb 2024 04:41:37 -0700 From: Balakrishnan Sambath Date: Thu, 29 Feb 2024 17:09:31 +0530 Subject: [PATCH 2/3] ARM: dts: microchip: sama7g5: Move pinfunc.h headers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240229-pio4-pinctrl-yaml-v1-2-c4d8279c083f@microchip.com> References: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> In-Reply-To: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Linus Walleij CC: , , , , "Balakrishnan Sambath" X-Mailer: b4 0.13.0 Move sama7g5-pinfunc.h into include/dt-bindings/pinctrl so that we can include it in yaml dt-binding examples. Signed-off-by: Balakrishnan Sambath --- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | = 2 +- .../dts/microchip =3D> include/dt-bindings/pinctrl}/sama7g5-pinfunc.h = | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot= /dts/microchip/at91-sama7g5ek.dts index 217e9b96c61e..a92c37e57aaf 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -9,7 +9,7 @@ * */ /dts-v1/; -#include "sama7g5-pinfunc.h" +#include #include "sama7g5.dtsi" #include #include diff --git a/arch/arm/boot/dts/microchip/sama7g5-pinfunc.h b/include/dt-bin= dings/pinctrl/sama7g5-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/microchip/sama7g5-pinfunc.h rename to include/dt-bindings/pinctrl/sama7g5-pinfunc.h --=20 2.25.1 From nobody Sun Feb 8 10:43:41 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36EB57C094; Thu, 29 Feb 2024 11:42:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709206939; cv=none; b=JsmCveYi8tIqdZgiPck5Lc3Tf+rgp/JpYkSwQ1ObdaugllLZr5M6SYKnMYb1Qli3PWta0FdvZTM6RXI117tlyM4osyTkxmRywQFvW68CR1r1gmo0loAXcfWnTzsjL+PxR5jAedn+YHLF5YGEEzTpj4qaMkdUBeRECnkCk2yBbkg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709206939; c=relaxed/simple; bh=88/nCfzcv/0mBvz7vctQH4WqIZwLFpdPUBRZoFLWORs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Ax1M/tVsajddnaNLIz4nCw+vBQc/INVUirXz/o94bHEya10JWfVOE3WEsYXZ5FD3F3neiFVmA2RoTEQY4QbbbJYDxkZCrnjoqzAUgVoiT5wxvzJXPEclGmwCgJ3iQdflbbkIWLsDJ9evkk0YTOkolnxOtKgC1lzsrDc5WthcO1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=nww28hpV; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="nww28hpV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1709206937; x=1740742937; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=88/nCfzcv/0mBvz7vctQH4WqIZwLFpdPUBRZoFLWORs=; b=nww28hpVyvOqhGMkGarA4erIy5O4P2IWJy/mqZ76VUcpcl/Of81JfMPY rQhhSwuYqUD6PZbCXYWgYG9ej43yLBgc71ljUzYPe7l7GmAB19HUyMi/l EAMsCtN3niEbo6zqzTQeYoY+7Npa6ln1OJfUIiU9H9rM4dGVSAbuksLhv iM0MmWHPTHsnaBWmKIybXmfVf6ysCcsUtvZrkTgJ6xOTQvxv6Fh8L0ZIg tDLQFlFS6fwAYq/sLzAARf7n26JzntHe3IYXTIEnyVA+V45VBdlmz0WaG ncI6Ju+ebE6WOCBLtXJrtx2E1kNQ/RVqdrNIMVUv84Jb3H28Cmt00U5fv Q==; X-CSE-ConnectionGUID: d8+oGP1LQdGqNaTtcEJPXQ== X-CSE-MsgGUID: q8U8MYpsRv2FsgSctH5nmA== X-IronPort-AV: E=Sophos;i="6.06,194,1705388400"; d="scan'208";a="247759793" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Feb 2024 04:42:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 29 Feb 2024 04:41:45 -0700 Received: from [127.0.1.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 29 Feb 2024 04:41:42 -0700 From: Balakrishnan Sambath Date: Thu, 29 Feb 2024 17:09:32 +0530 Subject: [PATCH 3/3] dt-bindings: pinctrl: at91-pio4: convert Atmel's PIO4 bindings to json-schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240229-pio4-pinctrl-yaml-v1-3-c4d8279c083f@microchip.com> References: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> In-Reply-To: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Linus Walleij CC: , , , , "Balakrishnan Sambath" X-Mailer: b4 0.13.0 Convert the existing text DT bindings of Atmel's PIO4 pincontroller to yaml based DT schema. Signed-off-by: Balakrishnan Sambath --- .../bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 98 --------------- .../bindings/pinctrl/atmel,sama5d2-pinctrl.yaml | 140 +++++++++++++++++= ++++ 2 files changed, 140 insertions(+), 98 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinc= trl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl= .txt deleted file mode 100644 index 774c3c269c40..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel PIO4 Controller - -The Atmel PIO4 controller is used to select the function of a pin and to -configure it. - -Required properties: -- compatible: - "atmel,sama5d2-pinctrl" - "microchip,sama7g5-pinctrl" -- reg: base address and length of the PIO controller. -- interrupts: interrupt outputs from the controller, one for each bank. -- interrupt-controller: mark the device node as an interrupt controller. -- #interrupt-cells: should be two. -- gpio-controller: mark the device node as a gpio controller. -- #gpio-cells: should be two. - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.tx= t for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -Subnode format -Each node (or subnode) will list the pins it needs and how to configured t= hese -pins. - - node { - pinmux =3D ; - GENERIC_PINCONFIG; - }; - -Required properties: -- pinmux: integer array. Each integer represents a pin number plus mux and -ioset settings. Use the macros from boot/dts/-pinfunc.h file to get t= he -right representation of the pin. - -Optional properties: -- GENERIC_PINCONFIG: generic pinconfig options to use: - - bias-disable, bias-pull-down, bias-pull-up, drive-open-drain, - drive-push-pull input-schmitt-enable, input-debounce, output-low, - output-high. - - for microchip,sama7g5-pinctrl only: - - slew-rate: 0 - disabled, 1 - enabled (default) -- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for -high drive. The default value is low drive. - -Example: - -#include - -... -{ - pioA: pinctrl@fc038000 { - compatible =3D "atmel,sama5d2-pinctrl"; - reg =3D <0xfc038000 0x600>; - interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH 7>, - <68 IRQ_TYPE_LEVEL_HIGH 7>, - <69 IRQ_TYPE_LEVEL_HIGH 7>, - <70 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #interrupt-cells =3D <2>; - gpio-controller; - #gpio-cells =3D <2>; - clocks =3D <&pioA_clk>; - - pinctrl_i2c0_default: i2c0_default { - pinmux =3D , - ; - bias-disable; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux =3D , - ; - bias-pull-up; - atmel,drive-strength =3D ; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux =3D , - , - , - , - ; - bias-pull-up; - }; - - ck_cd { - pinmux =3D , - ; - bias-disable; - }; - }; - ... - }; -}; -... diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,sama5d2-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/atmel,sama5d2-pinctrl.ya= ml new file mode 100644 index 000000000000..8a2dee1d6dd3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/atmel,sama5d2-pinctrl.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/atmel,sama5d2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIO4 Controller + +maintainers: + - Balakrishnan Sambath + +description: + The Microchip PIO4 controller is used to select the function of a pin an= d to + configure it. + + +properties: + compatible: + enum: + - microchip,sama7g5-pinctrl + - atmel,sama5d2-pinctrl + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + description: + Interrupt outputs from the controller, one for each bank. + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + clocks: + maxItems: 1 +if: + properties: + compatible: + contains: + const: microchip,sama7g5-pinctrl +then: + patternProperties: + '^.*([-_]default)?$': + anyOf: + - $ref: "#/$defs/mchp-pio4-pincfg-node-1" + - patternProperties: + '^[a-z_-][a-z_-]*$': + $ref: "#/$defs/mchp-pio4-pincfg-node-1" +else: + patternProperties: + '^.*([-_]default)?$': + anyOf: + - $ref: "#/$defs/mchp-pio4-pincfg-node-2" + - patternProperties: + '^[a-z_-][a-z_-]*$': + $ref: "#/$defs/mchp-pio4-pincfg-node-2" + +$defs: + mchp-pio4-pincfg-node-1: + $ref: pincfg-node.yaml#properties + properties: + pinmux: + $ref: pinmux-node.yaml#/properties/pinmux + atmel,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + required: + - pinmux + + mchp-pio4-pincfg-node-2: + $ref: pincfg-node.yaml#properties + properties: + pinmux: + $ref: pinmux-node.yaml#/properties/pinmux + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pinctrl@fc038000 { + compatible =3D "atmel,sama5d2-pinctrl"; + reg =3D <0xfc038000 0x600>; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH 7>, + <68 IRQ_TYPE_LEVEL_HIGH 7>, + <69 IRQ_TYPE_LEVEL_HIGH 7>, + <70 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + clocks =3D <&pioA_clk>; + + pinctrl_i2c0_default: i2c0_default { + pinmux =3D , + ; + bias-disable; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux =3D , + , + , + , + ; + bias-pull-up; + }; + + ck_cd { + pinmux =3D , + ; + bias-disable; + }; + }; + }; +... --=20 2.25.1