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charset="utf-8" Add snps,dw-pcie-ep.yaml. Remove context that exist in snps,dw-pcie-ep.yaml. Add an example for pcie-ep. Signed-off-by: Frank Li --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.y= aml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml index 0af70a4bc5d91..e75b8853dca8c 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -10,8 +10,7 @@ maintainers: - Frank Li =20 description: - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP - and thus inherits all the common properties defined in snps,dw-pcie.yaml. + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. =20 This controller derives its clocks from the Reset Configuration Word (RC= W) which is used to describe the PLL settings at the time of chip-reset. @@ -35,31 +34,18 @@ properties: - const: fsl,ls-pcie-ep =20 reg: - description: base addresses and lengths of the PCIe controller registe= r blocks. + maxItems: 2 + + reg-names: + maxItems: 2 =20 interrupts: - description: A list of interrupt outputs of the controller. Must conta= in an - entry for each entry in the interrupt-names property. + minItems: 1 + maxItems: 3 =20 interrupt-names: minItems: 1 maxItems: 3 - description: It could include the following entries. - items: - oneOf: - - description: - Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used. - const: aer - - description: - Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used. - const: pme - - description: - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). - const: intr =20 fsl,pcie-scfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -68,10 +54,7 @@ properties: The second entry is the physical PCIe controller index starting from= '0'. This is used to get SCFG PEXN registers =20 - dma-coherent: - description: Indicates that the hardware IP block can ensure the coher= ency - of the data transferred from/to the IP block. This can avoid the sof= tware - cache flush/invalid actions, and improve the performance significant= ly + dma-coherent: true =20 big-endian: $ref: /schemas/types.yaml#/definitions/flag @@ -87,3 +70,24 @@ required: - fsl,pcie-scfg - dma-coherence =20 +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie-ep@3400000 { + compatible =3D "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names =3D "dbi", "addr_space"; + interrupts =3D ; /* PME interrupt= */ + interrupt-names =3D "app"; + }; + }; +... --=20 2.34.1