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charset="utf-8" Split layerscape-pci.txt into two yaml files: fsl,layerscape-pcie-ep.yaml and fsl,layerscape-pcie.yaml. yaml files contain the same content as the original txt file. The subsequent commit will fix DTB_CHECK failure. Signed-off-by: Frank Li --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 89 +++++++++++++ .../bindings/pci/fsl,layerscape-pcie.yaml | 123 ++++++++++++++++++ .../bindings/pci/layerscape-pci.txt | 79 ----------- 3 files changed, 212 insertions(+), 79 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pc= ie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pc= ie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.y= aml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml new file mode 100644 index 0000000000000..0af70a4bc5d91 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Root Complex(RC) controller + +maintainers: + - Frank Li + +description: + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + + This controller derives its clocks from the Reset Configuration Word (RC= W) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'versi= on' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller ve= rsion + information. + +properties: + compatible: + items: + - enum: + - fsl,ls1028a-pcie-ep + - fsl,ls2046a-pcie-ep + - fsl,ls2088a-pcie-ep + - fsl,ls1046a-pcie-ep + - fsl,ls1043a-pcie-ep + - fsl,ls1012a-pcie-ep + - fsl,lx2160ar2-pcie-ep + - const: fsl,ls-pcie-ep + + reg: + description: base addresses and lengths of the PCIe controller registe= r blocks. + + interrupts: + description: A list of interrupt outputs of the controller. Must conta= in an + entry for each entry in the interrupt-names property. + + interrupt-names: + minItems: 1 + maxItems: 3 + description: It could include the following entries. + items: + oneOf: + - description: + Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used. + const: aer + - description: + Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used. + const: pme + - description: + Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). + const: intr + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Must include two entries. + The first entry must be a link to the SCFG device node + The second entry is the physical PCIe controller index starting from= '0'. + This is used to get SCFG PEXN registers + + dma-coherent: + description: Indicates that the hardware IP block can ensure the coher= ency + of the data transferred from/to the IP block. This can avoid the sof= tware + cache flush/invalid actions, and improve the performance significant= ly + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, sp= ecify + this property. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-names + - fsl,pcie-scfg + - dma-coherence + diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml= b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml new file mode 100644 index 0000000000000..c37578fde8bb1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Root Complex(RC) controller + +maintainers: + - Frank Li + +description: + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + + This controller derives its clocks from the Reset Configuration Word (RC= W) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'versi= on' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller ve= rsion + information. + +properties: + compatible: + enum: + - fsl,ls1021a-pcie + - fsl,ls2080a-pcie + - fsl,ls2085a-pcie + - fsl,ls2088a-pcie + - fsl,ls1088a-pcie + - fsl,ls1046a-pcie + - fsl,ls1043a-pcie + - fsl,ls1012a-pcie + - fsl,ls1028a-pcie + - fsl,lx2160a-pcie + + reg: + description: base addresses and lengths of the PCIe controller registe= r blocks. + + interrupts: + description: A list of interrupt outputs of the controller. Must conta= in an + entry for each entry in the interrupt-names property. + + interrupt-names: + minItems: 1 + maxItems: 3 + description: It could include the following entries. + items: + oneOf: + - description: + Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used. + const: aer + - description: + Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used. + const: pme + - description: + Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). + const: intr + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Must include two entries. + The first entry must be a link to the SCFG device node + The second entry is the physical PCIe controller index starting from= '0'. + This is used to get SCFG PEXN registers + + dma-coherent: + description: Indicates that the hardware IP block can ensure the coher= ency + of the data transferred from/to the IP block. This can avoid the sof= tware + cache flush/invalid actions, and improve the performance significant= ly + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, sp= ecify + this property. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-names + - fsl,pcie-scfg + - dma-coherence + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@3400000 { + compatible =3D "fsl,ls1088a-pcie"; + reg =3D <0x00 0x03400000 0x0 0x00100000>, /* controller registers = */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names =3D "regs", "config"; + interrupts =3D <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names =3D "aer"; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + device_type =3D "pci"; + bus-range =3D <0x0 0xff>; + ranges =3D <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x000100= 00 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>= ; /* non-prefetchable memory */ + msi-parent =3D <&its>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map =3D <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Doc= umentation/devicetree/bindings/pci/layerscape-pci.txt deleted file mode 100644 index ee8a4791a78b4..0000000000000 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ /dev/null @@ -1,79 +0,0 @@ -Freescale Layerscape PCIe controller - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in snps,dw-pcie.yaml. - -This controller derives its clocks from the Reset Configuration Word (RCW) -which is used to describe the PLL settings at the time of chip-reset. - -Also as per the available Reference Manuals, there is no specific 'version' -register available in the Freescale PCIe controller register set, -which can allow determining the underlying DesignWare PCIe controller vers= ion -information. - -Required properties: -- compatible: should contain the platform identifier such as: - RC mode: - "fsl,ls1021a-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" - "fsl,ls2088a-pcie" - "fsl,ls1088a-pcie" - "fsl,ls1046a-pcie" - "fsl,ls1043a-pcie" - "fsl,ls1012a-pcie" - "fsl,ls1028a-pcie" - EP mode: - "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" -- reg: base addresses and lengths of the PCIe controller register blocks. -- interrupts: A list of interrupt outputs of the controller. Must contain = an - entry for each entry in the interrupt-names property. -- interrupt-names: It could include the following entries: - "aer": Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used - "pme": Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used - "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). -- fsl,pcie-scfg: Must include two entries. - The first entry must be a link to the SCFG device node - The second entry is the physical PCIe controller index starting from '0'. - This is used to get SCFG PEXN registers -- dma-coherent: Indicates that the hardware IP block can ensure the cohere= ncy - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly. - -Optional properties: -- big-endian: If the PEX_LUT and PF register block is in big-endian, speci= fy - this property. - -Example: - - pcie@3400000 { - compatible =3D "fsl,ls1088a-pcie"; - reg =3D <0x00 0x03400000 0x0 0x00100000>, /* controller re= gisters */ - <0x20 0x00000000 0x0 0x00002000>; /* configuration s= pace */ - reg-names =3D "regs", "config"; - interrupts =3D <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interru= pt */ - interrupt-names =3D "aer"; - #address-cells =3D <3>; - #size-cells =3D <2>; - device_type =3D "pci"; - dma-coherent; - num-viewport =3D <256>; - bus-range =3D <0x0 0xff>; - ranges =3D <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 = 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x= 40000000>; /* non-prefetchable memory */ - msi-parent =3D <&its>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVE= L_HIGH>, - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_= HIGH>, - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_= HIGH>, - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_= HIGH>; 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charset="utf-8" Add snps,dw-pcie.yaml reference. Clean up all context that already exist in snps,dw-pcie.yaml. Update interrupt-names requirement for difference compatible string. Signed-off-by: Frank Li --- .../bindings/pci/fsl,layerscape-pcie.yaml | 102 +++++++++++++----- 1 file changed, 77 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml= b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml index c37578fde8bb1..b57b627c18e95 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -11,7 +11,6 @@ maintainers: =20 description: This PCIe RC controller is based on the Synopsys DesignWare PCIe IP - and thus inherits all the common properties defined in snps,dw-pcie.yaml. =20 This controller derives its clocks from the Reset Configuration Word (RC= W) which is used to describe the PLL settings at the time of chip-reset. @@ -36,31 +35,18 @@ properties: - fsl,lx2160a-pcie =20 reg: - description: base addresses and lengths of the PCIe controller registe= r blocks. + maxItems: 2 + + reg-names: + maxItems: 2 =20 interrupts: - description: A list of interrupt outputs of the controller. Must conta= in an - entry for each entry in the interrupt-names property. + minItems: 1 + maxItems: 3 =20 interrupt-names: minItems: 1 maxItems: 3 - description: It could include the following entries. - items: - oneOf: - - description: - Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used. - const: aer - - description: - Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used. - const: pme - - description: - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). - const: intr =20 fsl,pcie-scfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -69,10 +55,11 @@ properties: The second entry is the physical PCIe controller index starting from= '0'. This is used to get SCFG PEXN registers =20 - dma-coherent: - description: Indicates that the hardware IP block can ensure the coher= ency - of the data transferred from/to the IP block. This can avoid the sof= tware - cache flush/invalid actions, and improve the performance significant= ly + dma-coherent: true + + msi-parent: true + + iommu-map: true =20 big-endian: $ref: /schemas/types.yaml#/definitions/flag @@ -88,6 +75,70 @@ required: - fsl,pcie-scfg - dma-coherence =20 +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: + properties: + compatible: + enum: + - fsl,lx2160a-pcie + then: + properties: + interrupts: + maxItems: 3 + interrupt-names: + items: + - const: pme + - const: aer + - const: intr + + - if: + properties: + compatible: + enum: + - fsl,ls1028a-pcie + - fsl,ls1046a-pcie + - fsl,ls1043a-pcie + - fsl,ls1012a-pcie + then: + properties: + interrupts: + maxItems: 2 + interrupt-names: + items: + - const: pme + - const: aer + + - if: + properties: + compatible: + enum: + - fsl,ls2080a-pcie + - fsl,ls2085a-pcie + - fsl,ls2088a-pcie + - fsl,ls1021a-pcie + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: intr + + - if: + properties: + compatible: + enum: + - fsl,ls1088a-pcie + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: aer + examples: - | #include @@ -100,7 +151,7 @@ examples: compatible =3D "fsl,ls1088a-pcie"; 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Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by AS8PR04MB8370.eurprd04.prod.outlook.com (2603:10a6:20b:3b1::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.39; Wed, 28 Feb 2024 19:03:48 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9af4:87e:d74:94aa]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9af4:87e:d74:94aa%7]) with mapi id 15.20.7316.035; Wed, 28 Feb 2024 19:03:48 +0000 From: Frank Li To: helgaas@kernel.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, conor@kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, robh@kernel.org Subject: [PATCH v5 3/5] dt-bindings: pci: layerscape-pci: Remove 'fsl,pcie-scfg' and 'dma-coherence' from required Date: Wed, 28 Feb 2024 14:03:19 -0500 Message-Id: <20240228190321.580846-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240228190321.580846-1-Frank.Li@nxp.com> References: <20240228190321.580846-1-Frank.Li@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0165.namprd05.prod.outlook.com (2603:10b6:a03:339::20) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|AS8PR04MB8370:EE_ X-MS-Office365-Filtering-Correlation-Id: e4509bab-1705-42e8-03bc-08dc388ffea7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" Remove 'fsl,pcie-scfg' and 'dma-coherence' properties from required because not all chips is dma coherenced and have supplement configuration unit (scfg). Signed-off-by: Frank Li --- Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml= b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml index b57b627c18e95..137cc17933a4b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -72,8 +72,6 @@ required: - compatible - reg - interrupt-names - - fsl,pcie-scfg - - dma-coherence =20 allOf: - $ref: /schemas/pci/pci-bus.yaml# --=20 2.34.1 From nobody Sun Feb 8 05:13:00 2026 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2073.outbound.protection.outlook.com [40.107.247.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B737C15E5DE; Wed, 28 Feb 2024 19:03:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add snps,dw-pcie-ep.yaml. Remove context that exist in snps,dw-pcie-ep.yaml. Add an example for pcie-ep. Signed-off-by: Frank Li --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.y= aml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml index 0af70a4bc5d91..e75b8853dca8c 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -10,8 +10,7 @@ maintainers: - Frank Li =20 description: - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP - and thus inherits all the common properties defined in snps,dw-pcie.yaml. + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. =20 This controller derives its clocks from the Reset Configuration Word (RC= W) which is used to describe the PLL settings at the time of chip-reset. @@ -35,31 +34,18 @@ properties: - const: fsl,ls-pcie-ep =20 reg: - description: base addresses and lengths of the PCIe controller registe= r blocks. + maxItems: 2 + + reg-names: + maxItems: 2 =20 interrupts: - description: A list of interrupt outputs of the controller. Must conta= in an - entry for each entry in the interrupt-names property. + minItems: 1 + maxItems: 3 =20 interrupt-names: minItems: 1 maxItems: 3 - description: It could include the following entries. - items: - oneOf: - - description: - Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used. - const: aer - - description: - Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used. - const: pme - - description: - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). - const: intr =20 fsl,pcie-scfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -68,10 +54,7 @@ properties: The second entry is the physical PCIe controller index starting from= '0'. This is used to get SCFG PEXN registers =20 - dma-coherent: - description: Indicates that the hardware IP block can ensure the coher= ency - of the data transferred from/to the IP block. This can avoid the sof= tware - cache flush/invalid actions, and improve the performance significant= ly + dma-coherent: true =20 big-endian: $ref: /schemas/types.yaml#/definitions/flag @@ -87,3 +70,24 @@ required: - fsl,pcie-scfg - dma-coherence =20 +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie-ep@3400000 { + compatible =3D "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; + reg =3D <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names =3D "dbi", "addr_space"; + interrupts =3D ; /* PME interrupt= */ + interrupt-names =3D "app"; + }; + }; +... --=20 2.34.1 From nobody Sun Feb 8 05:13:00 2026 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2073.outbound.protection.outlook.com [40.107.247.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECA8315F30B; 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charset="utf-8" Remove 'fsl,pcie-scfg' and 'dma-coherence' properties from required because not all chips is dma coherenced and have supplement configuration unit (scfg). Signed-off-by: Frank Li --- .../devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.y= aml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml index e75b8853dca8c..07965683beece 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -67,8 +67,6 @@ required: - compatible - reg - interrupt-names - - fsl,pcie-scfg - - dma-coherence =20 allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# --=20 2.34.1