From nobody Mon Feb 9 01:45:27 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 663311DDC5 for ; Wed, 28 Feb 2024 08:22:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709108569; cv=none; b=I6slRGKhEkSt+Q6Jj4bfs8sheLqQt7nVkkwqPm7SBk+wmuMEre8gZPzot08nQo0WUUQD/oPaXtaxdbne3Jyd7oitJAIhmFePgE+VlQtW+d8W8aGi4rIs9W4oQBxDzaooAVPnr+W59N9m8x6cxNwDkdD6P6P3sfyg4mBWM/Myj+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709108569; c=relaxed/simple; bh=QLeUI4nJDeR341Zp+d1czOyITgxQLEsVmfTk45EbLos=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=EVfI3FR+rsdC5Jcwhmp1/KN7HBHynwDSxIJIfOubsEOQTEDi7fbotKNoOpgYcRN+Zv909AinSfA20fDQF1IUdGYN03OBkxXujCSA5xGA1pb2LJY+RBZEhA5zVGtzoz14s3hPbv5ArqHp51ATBcwfHe71goKtanI1cIg1Vcr+/Gc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cJ2ihBuB; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cJ2ihBuB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709108567; x=1740644567; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=QLeUI4nJDeR341Zp+d1czOyITgxQLEsVmfTk45EbLos=; b=cJ2ihBuBERKtfbjkQ2pIbV44rZRWv/ZfLg48njy8KhymFpSqZIlZaGP4 iydhuu+q+qrkrBz8gJxJMW1nf3xyKfvE3Ol7uVo+qfA23xTI1NFRar5zK KPMZmqfVru4/0YTQ1UTCEmDZQSDVPlSMNvBsuGGFR4Jx4dn0eI9pWchC2 gA5ikNaS8r7qrE/S1rjaMLOHymWORpOIW+wAArCFzOhim0rfcQN4K7NYw BduzLMKn30cyBghLgmApJVuyTeihXZ6vFRoma5ily1cfUW6+p+m4VL6p7 4x40WTiqbM0g8GJEcl541ct8Igs2r3JAH3oJJFTiVAJYQpZkv7S1nORyx A==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="28927508" X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="28927508" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2024 00:22:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="7918131" Received: from wufei-optiplex-7090.sh.intel.com ([10.239.158.51]) by orviesa008.jf.intel.com with ESMTP; 28 Feb 2024 00:22:43 -0800 From: Fei Wu To: atishp@atishpatra.org, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandre Ghiti Cc: Fei Wu , Atish Patra Subject: [PATCH v3] perf: RISCV: Fix panic on pmu overflow handler Date: Wed, 28 Feb 2024 16:27:52 +0800 Message-Id: <20240228082752.2612302-1-fei2.wu@intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" (1 << idx) of int is not desired when setting bits in unsigned long overflowed_ctrs, use BIT() instead. This panic happens when running 'perf record -e branches' on sophgo sg2042. [ 273.311852] Unable to handle kernel NULL pointer dereference at virtual = address 0000000000000098 [ 273.320851] Oops [#1] [ 273.323179] Modules linked in: [ 273.326303] CPU: 0 PID: 1475 Comm: perf Not tainted 6.6.0-rc3+ #9 [ 273.332521] Hardware name: Sophgo Mango (DT) [ 273.336878] epc : riscv_pmu_ctr_get_width_mask+0x8/0x62 [ 273.342291] ra : pmu_sbi_ovf_handler+0x2e0/0x34e [ 273.347091] epc : ffffffff80aecd98 ra : ffffffff80aee056 sp : fffffff6e3= 6928b0 [ 273.354454] gp : ffffffff821f82d0 tp : ffffffd90c353200 t0 : 0000002ade= 4f9978 [ 273.361815] t1 : 0000000000504d55 t2 : ffffffff8016cd8c s0 : fffffff6e3= 692a70 [ 273.369180] s1 : 0000000000000020 a0 : 0000000000000000 a1 : 00001a8e81= 800000 [ 273.376540] a2 : 0000003c00070198 a3 : 0000003c00db75a4 a4 : 0000000000= 000015 [ 273.383901] a5 : ffffffd7ff8804b0 a6 : 0000000000000015 a7 : 0000000000= 00002a [ 273.391327] s2 : 000000000000ffff s3 : 0000000000000000 s4 : ffffffd7ff= 8803b0 [ 273.398773] s5 : 0000000000504d55 s6 : ffffffd905069800 s7 : ffffffff82= 1fe210 [ 273.406139] s8 : 000000007fffffff s9 : ffffffd7ff8803b0 s10: ffffffd903= f29098 [ 273.413660] s11: 0000000080000000 t3 : 0000000000000003 t4 : ffffffff80= 17a0ca [ 273.421022] t5 : ffffffff8023cfc2 t6 : ffffffd9040780e8 [ 273.426437] status: 0000000200000100 badaddr: 0000000000000098 cause: 00= 0000000000000d [ 273.434512] [] riscv_pmu_ctr_get_width_mask+0x8/0x62 [ 273.441169] [] handle_percpu_devid_irq+0x98/0x1ee [ 273.447562] [] generic_handle_domain_irq+0x28/0x36 [ 273.454151] [] riscv_intc_irq+0x36/0x4e [ 273.459659] [] handle_riscv_irq+0x4a/0x74 [ 273.465442] [] do_irq+0x62/0x92 [ 273.470360] Code: 0420 60a2 6402 5529 0141 8082 0013 0000 0013 0000 (6d5= c) b783 [ 273.477921] ---[ end trace 0000000000000000 ]--- [ 273.482630] Kernel panic - not syncing: Fatal exception in interrupt Reviewed-by: Atish Patra Signed-off-by: Fei Wu Reviewed-by: Alexandre Ghiti --- drivers/perf/riscv_pmu_sbi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16acd4dcdb96..452aab49db1e 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -512,7 +512,7 @@ static void pmu_sbi_set_scounteren(void *arg) =20 if (event->hw.idx !=3D -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) | (1 << pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event))); } =20 static void pmu_sbi_reset_scounteren(void *arg) @@ -521,7 +521,7 @@ static void pmu_sbi_reset_scounteren(void *arg) =20 if (event->hw.idx !=3D -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) & ~(1 << pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event))); } =20 static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) @@ -731,14 +731,14 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void = *dev) /* compute hardware counter index */ hidx =3D info->csr - CSR_CYCLE; /* check if the corresponding bit is set in sscountovf */ - if (!(overflow & (1 << hidx))) + if (!(overflow & BIT(hidx))) continue; =20 /* * Keep a track of overflowed counters so that they can be started * with updated initial value. */ - overflowed_ctrs |=3D 1 << lidx; + overflowed_ctrs |=3D BIT(lidx); hw_evt =3D &event->hw; riscv_pmu_event_update(event); perf_sample_data_init(&data, 0, hw_evt->last_period); --=20 2.34.1