From nobody Sat Feb 7 17:19:47 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52B964A1A for ; Wed, 28 Feb 2024 05:33:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709098387; cv=none; b=gYLe1ypKO2wXBbkT6siYLZQTYrpM8N+QEmX2j78I8LScVUc8SqW+TLSBeh621hVQwJH5SOYPGjSTW4uyaasTO2HXtwQhHYcId5LYQ+uQvEj7evIwf/H/OYYPFm/EKlRbfyQzzrpoydY1S7KaUMHB3rme75CtJFud4bgGdJ3KXGA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709098387; c=relaxed/simple; bh=z/BnArCvPNt7MT9ga2Arel3xPYZRjie7hVWYkQTMgwg=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=WfHq+h+dfzz14VdO6Ufb0YAQZatp7xBbgQsCG1xanRZTPdP9EHhwvNqA/8XrohoePR3lpeGPYmMpF3VOq3o4v0jVYr1JSy40ZfDZzA/fDKfyJ3fEA258xuA/GlCrBQtmuiCsl6w7FajF+UzeQaJJiPz2E2SF3pFspvgTRlSNKDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kvNJfRZz; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kvNJfRZz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709098386; x=1740634386; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=z/BnArCvPNt7MT9ga2Arel3xPYZRjie7hVWYkQTMgwg=; b=kvNJfRZzOwIsiOZyBz3REuU8cYSvf7Kz+DMW+DtB3x+g3c8ND6zzvA8f MlQ2BcMs5xlo7z/IghOYWnhZYfLqqJ7wIjLYa8o7jHGVHL1vnNo5ntSh9 qAT243bael3B1hAfrgfxKzHAYYlNwVfUVw7G+FPqNJm7kfaSm2u7cRaaN JpqLQDlomrpllkeVdF2PSc7Q3rDhmcjPC5KtQcVfMdeB1lxPALKvDg/bt oVl4viR8SIRUeF5HezdRkOlqq550BlQeqbm60tH/xmYUYFWqJiSeszWxS DXqsoybkz6mJmYGAnWkPeVfaQ5Jas7gDARfYKO8j+/GAI6Ozsg032NXSJ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="20935832" X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="20935832" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2024 21:33:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="12031899" Received: from wufei-optiplex-7090.sh.intel.com ([10.239.158.51]) by orviesa003.jf.intel.com with ESMTP; 27 Feb 2024 21:33:03 -0800 From: Fei Wu To: atishp@atishpatra.org, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandre Ghiti Cc: Fei Wu Subject: [PATCH v2] perf: RISCV: Fix panic on pmu overflow handler Date: Wed, 28 Feb 2024 13:38:22 +0800 Message-Id: <20240228053822.2610915-1-fei2.wu@intel.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" (1 << idx) of int is not desired when setting bits in unsigned long overflowed_ctrs, use BIT() instead. This panic happens when running 'perf record -e branches' on sophgo sg2042. [ 273.311852] Unable to handle kernel NULL pointer dereference at virtual = address 0000000000000098 [ 273.320851] Oops [#1] [ 273.323179] Modules linked in: [ 273.326303] CPU: 0 PID: 1475 Comm: perf Not tainted 6.6.0-rc3+ #9 [ 273.332521] Hardware name: Sophgo Mango (DT) [ 273.336878] epc : riscv_pmu_ctr_get_width_mask+0x8/0x62 [ 273.342291] ra : pmu_sbi_ovf_handler+0x2e0/0x34e [ 273.347091] epc : ffffffff80aecd98 ra : ffffffff80aee056 sp : fffffff6e3= 6928b0 [ 273.354454] gp : ffffffff821f82d0 tp : ffffffd90c353200 t0 : 0000002ade= 4f9978 [ 273.361815] t1 : 0000000000504d55 t2 : ffffffff8016cd8c s0 : fffffff6e3= 692a70 [ 273.369180] s1 : 0000000000000020 a0 : 0000000000000000 a1 : 00001a8e81= 800000 [ 273.376540] a2 : 0000003c00070198 a3 : 0000003c00db75a4 a4 : 0000000000= 000015 [ 273.383901] a5 : ffffffd7ff8804b0 a6 : 0000000000000015 a7 : 0000000000= 00002a [ 273.391327] s2 : 000000000000ffff s3 : 0000000000000000 s4 : ffffffd7ff= 8803b0 [ 273.398773] s5 : 0000000000504d55 s6 : ffffffd905069800 s7 : ffffffff82= 1fe210 [ 273.406139] s8 : 000000007fffffff s9 : ffffffd7ff8803b0 s10: ffffffd903= f29098 [ 273.413660] s11: 0000000080000000 t3 : 0000000000000003 t4 : ffffffff80= 17a0ca [ 273.421022] t5 : ffffffff8023cfc2 t6 : ffffffd9040780e8 [ 273.426437] status: 0000000200000100 badaddr: 0000000000000098 cause: 00= 0000000000000d [ 273.434512] [] riscv_pmu_ctr_get_width_mask+0x8/0x62 [ 273.441169] [] handle_percpu_devid_irq+0x98/0x1ee [ 273.447562] [] generic_handle_domain_irq+0x28/0x36 [ 273.454151] [] riscv_intc_irq+0x36/0x4e [ 273.459659] [] handle_riscv_irq+0x4a/0x74 [ 273.465442] [] do_irq+0x62/0x92 [ 273.470360] Code: 0420 60a2 6402 5529 0141 8082 0013 0000 0013 0000 (6d5= c) b783 [ 273.477921] ---[ end trace 0000000000000000 ]--- [ 273.482630] Kernel panic - not syncing: Fatal exception in interrupt Signed-off-by: Fei Wu Reviewed-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16acd4dcdb96..335171db9647 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -731,14 +731,14 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void = *dev) /* compute hardware counter index */ hidx =3D info->csr - CSR_CYCLE; /* check if the corresponding bit is set in sscountovf */ - if (!(overflow & (1 << hidx))) + if (!(overflow & BIT(hidx))) continue; =20 /* * Keep a track of overflowed counters so that they can be started * with updated initial value. */ - overflowed_ctrs |=3D 1 << lidx; + overflowed_ctrs |=3D BIT(lidx); hw_evt =3D &event->hw; riscv_pmu_event_update(event); perf_sample_data_init(&data, 0, hw_evt->last_period); --=20 2.34.1