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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BL02EPF0001A101.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7292.25 via Frontend Transport; Wed, 28 Feb 2024 04:21:53 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 27 Feb 2024 22:21:50 -0600 Received: from xsjssw-mmedia3.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 27 Feb 2024 22:21:50 -0600 From: Vishal Sagar To: , CC: , , , , Subject: [PATCH v2 1/2] dmaengine: xilinx: dpdma: Fix race condition in vsync IRQ Date: Tue, 27 Feb 2024 20:21:23 -0800 Message-ID: <20240228042124.3074044-2-vishal.sagar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240228042124.3074044-1-vishal.sagar@amd.com> References: <20240228042124.3074044-1-vishal.sagar@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: vishal.sagar@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A101:EE_|BL3PR12MB6643:EE_ X-MS-Office365-Filtering-Correlation-Id: 90a48606-6ccd-469e-2ccd-08dc3814cac8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2024 04:21:53.1916 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90a48606-6ccd-469e-2ccd-08dc3814cac8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A101.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6643 Content-Type: text/plain; charset="utf-8" From: Neel Gandhi The vchan_next_desc() function, called from xilinx_dpdma_chan_queue_transfer(), must be called with virt_dma_chan.lock held. This isn't correctly handled in all code paths, resulting in a race condition between the .device_issue_pending() handler and the IRQ handler which causes DMA to randomly stop. Fix it by taking the lock around xilinx_dpdma_chan_queue_transfer() calls that are missing it. Signed-off-by: Neel Gandhi Signed-off-by: Radhey Shyam Pandey Signed-off-by: Tomi Valkeinen Signed-off-by: Vishal Sagar Link: https://lore.kernel.org/all/20220122121407.11467-1-neel.gandhi@xilinx= .com Reviewed-by: Sean Anderson --- drivers/dma/xilinx/xilinx_dpdma.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_= dpdma.c index b82815e64d24..28d9af8f00f0 100644 --- a/drivers/dma/xilinx/xilinx_dpdma.c +++ b/drivers/dma/xilinx/xilinx_dpdma.c @@ -1097,12 +1097,14 @@ static void xilinx_dpdma_chan_vsync_irq(struct xil= inx_dpdma_chan *chan) * Complete the active descriptor, if any, promote the pending * descriptor to active, and queue the next transfer, if any. */ + spin_lock(&chan->vchan.lock); if (chan->desc.active) vchan_cookie_complete(&chan->desc.active->vdesc); chan->desc.active =3D pending; chan->desc.pending =3D NULL; =20 xilinx_dpdma_chan_queue_transfer(chan); + spin_unlock(&chan->vchan.lock); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2024 04:21:53.5041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddd54d75-d375-408e-dc05-08dc3814caf7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A101.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8564 Content-Type: text/plain; charset="utf-8" From: Rohit Visavalia This patch adds support for DPDMA cyclic dma mode, DMA cyclic transfers are required by audio streaming. Signed-off-by: Rohit Visavalia Signed-off-by: Radhey Shyam Pandey Signed-off-by: Vishal Sagar Reviewed-by: Tomi Valkeinen Tested-by: Tomi Valkeinen --- drivers/dma/xilinx/xilinx_dpdma.c | 97 +++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_= dpdma.c index 28d9af8f00f0..88ad2f35538a 100644 --- a/drivers/dma/xilinx/xilinx_dpdma.c +++ b/drivers/dma/xilinx/xilinx_dpdma.c @@ -669,6 +669,84 @@ static void xilinx_dpdma_chan_free_tx_desc(struct virt= _dma_desc *vdesc) kfree(desc); } =20 +/** + * xilinx_dpdma_chan_prep_cyclic - Prepare a cyclic dma descriptor + * @chan: DPDMA channel + * @buf_addr: buffer address + * @buf_len: buffer length + * @period_len: number of periods + * @flags: tx flags argument passed in to prepare function + * + * Prepare a tx descriptor incudling internal software/hardware descriptors + * for the given cyclic transaction. + * + * Return: A dma async tx descriptor on success, or NULL. + */ +static struct dma_async_tx_descriptor * +xilinx_dpdma_chan_prep_cyclic(struct xilinx_dpdma_chan *chan, + dma_addr_t buf_addr, size_t buf_len, + size_t period_len, unsigned long flags) +{ + struct xilinx_dpdma_tx_desc *tx_desc; + struct xilinx_dpdma_sw_desc *sw_desc, *last =3D NULL; + unsigned int periods =3D buf_len / period_len; + unsigned int i; + + tx_desc =3D xilinx_dpdma_chan_alloc_tx_desc(chan); + if (!tx_desc) + return (void *)tx_desc; + + for (i =3D 0; i < periods; i++) { + struct xilinx_dpdma_hw_desc *hw_desc; + + if (!IS_ALIGNED(buf_addr, XILINX_DPDMA_ALIGN_BYTES)) { + dev_err(chan->xdev->dev, + "buffer should be aligned at %d B\n", + XILINX_DPDMA_ALIGN_BYTES); + goto error; + } + + sw_desc =3D xilinx_dpdma_chan_alloc_sw_desc(chan); + if (!sw_desc) + goto error; + + xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, last, + &buf_addr, 1); + hw_desc =3D &sw_desc->hw; + hw_desc->xfer_size =3D period_len; + hw_desc->hsize_stride =3D + FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, + period_len) | + FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK, + period_len); + hw_desc->control |=3D XILINX_DPDMA_DESC_CONTROL_PREEMBLE; + hw_desc->control |=3D XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE; + hw_desc->control |=3D XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR; + + list_add_tail(&sw_desc->node, &tx_desc->descriptors); + + buf_addr +=3D period_len; + last =3D sw_desc; + } + + sw_desc =3D list_first_entry(&tx_desc->descriptors, + struct xilinx_dpdma_sw_desc, node); + last->hw.next_desc =3D lower_32_bits(sw_desc->dma_addr); + if (chan->xdev->ext_addr) + last->hw.addr_ext |=3D + FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK, + upper_32_bits(sw_desc->dma_addr)); + + last->hw.control |=3D XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME; + + return vchan_tx_prep(&chan->vchan, &tx_desc->vdesc, flags); + +error: + xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc); + + return NULL; +} + /** * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma * descriptor @@ -1190,6 +1268,23 @@ static void xilinx_dpdma_chan_handle_err(struct xili= nx_dpdma_chan *chan) /* -----------------------------------------------------------------------= ------ * DMA Engine Operations */ +static struct dma_async_tx_descriptor * +xilinx_dpdma_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, + enum dma_transfer_direction direction, + unsigned long flags) +{ + struct xilinx_dpdma_chan *chan =3D to_xilinx_chan(dchan); + + if (direction !=3D DMA_MEM_TO_DEV) + return NULL; + + if (buf_len % period_len) + return NULL; + + return xilinx_dpdma_chan_prep_cyclic(chan, buf_addr, buf_len, + period_len, flags); +} =20 static struct dma_async_tx_descriptor * xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan, @@ -1673,6 +1768,7 @@ static int xilinx_dpdma_probe(struct platform_device = *pdev) =20 dma_cap_set(DMA_SLAVE, ddev->cap_mask); dma_cap_set(DMA_PRIVATE, ddev->cap_mask); + dma_cap_set(DMA_CYCLIC, ddev->cap_mask); dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask); dma_cap_set(DMA_REPEAT, ddev->cap_mask); dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask); @@ -1680,6 +1776,7 @@ static int xilinx_dpdma_probe(struct platform_device = *pdev) =20 ddev->device_alloc_chan_resources =3D xilinx_dpdma_alloc_chan_resources; ddev->device_free_chan_resources =3D xilinx_dpdma_free_chan_resources; + ddev->device_prep_dma_cyclic =3D xilinx_dpdma_prep_dma_cyclic; ddev->device_prep_interleaved_dma =3D xilinx_dpdma_prep_interleaved_dma; /* TODO: Can we achieve better granularity ? */ ddev->device_tx_status =3D dma_cookie_status; --=20 2.25.1