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Signed-off-by: Peng Fan --- .../devicetree/bindings/clock/imx95-blk-ctl.yaml | 61 ++++++++++++++++++= ++++ include/dt-bindings/clock/nxp,imx95-clock.h | 32 ++++++++++++ 2 files changed, 93 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml b/D= ocumentation/devicetree/bindings/clock/imx95-blk-ctl.yaml new file mode 100644 index 000000000000..179bdd33504c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx95-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX95 Block Control + +maintainers: + - Peng Fan + +properties: + compatible: + items: + - enum: + - nxp,imx95-cameramix-csr + - nxp,imx95-display-master-csr + - nxp,imx95-dispmix-lvds-csr + - nxp,imx95-dispmix-csr + - nxp,imx95-netcmix-blk-ctrl + - nxp,imx95-vpumix-csr + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the cl= ock + ID in its "clocks" phandle cell. See + include/dt-bindings/clock/nxp,imx95-clock.h + + mux-controller: + type: object + $ref: /schemas/mux/reg-mux.yaml + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + #include + + syscon@4c410000 { + compatible =3D "fsl,imx95-vpumix-blk-ctrl", "syscon"; + reg =3D <0x4c410000 0x10000>; + #clock-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindi= ngs/clock/nxp,imx95-clock.h new file mode 100644 index 000000000000..09120e098a97 --- /dev/null +++ b/include/dt-bindings/clock/nxp,imx95-clock.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX95_H +#define __DT_BINDINGS_CLOCK_IMX95_H + +#define IMX95_CLK_DISPMIX_ENG0_SEL 0 +#define IMX95_CLK_DISPMIX_ENG1_SEL 1 +#define IMX95_CLK_DISPMIX_END 2 + +#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 +#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 +#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 +#define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 +#define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 +#define IMX95_CLK_DISPMIX_LVDS_CSR_END 5 + +#define IMX95_CLK_VPUBLK_WAVE 0 +#define IMX95_CLK_VPUBLK_JPEG_ENC 1 +#define IMX95_CLK_VPUBLK_JPEG_DEC 2 +#define IMX95_CLK_VPUBLK_END 3 + +#define IMX95_CLK_CAMBLK_CSI2_FOR0 0 +#define IMX95_CLK_CAMBLK_CSI2_FOR1 1 +#define IMX95_CLK_CAMBLK_ISP_AXI 2 +#define IMX95_CLK_CAMBLK_ISP_PIXEL 3 +#define IMX95_CLK_CAMBLK_ISP 4 +#define IMX95_CLK_CAMBLK_END 5 + +#endif /* __DT_BINDINGS_CLOCK_IMX95_H */ --=20 2.37.1 From nobody Mon Feb 9 01:22:18 2026 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2084.outbound.protection.outlook.com [40.107.21.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A83220DF5; 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This patch is to add the clock feature of BLK CTL modules Signed-off-by: Peng Fan --- drivers/clk/imx/Kconfig | 7 + drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx95-blk-ctl.c | 438 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 446 insertions(+) diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index db3bca5f4ec9..6da0fba68225 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -114,6 +114,13 @@ config CLK_IMX93 help Build the driver for i.MX93 CCM Clock Driver =20 +config CLK_IMX95_BLK_CTL + tristate "IMX95 Clock Driver for BLK CTL" + depends on ARCH_MXC || COMPILE_TEST + select MXC_CLK + help + Build the clock driver for i.MX95 BLK CTL + config CLK_IMXRT1050 tristate "IMXRT1050 CCM Clock Driver" depends on SOC_IMXRT || COMPILE_TEST diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index d4b8e10b1970..03f2b2a1ab63 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp.o clk-imx8mp-aud= iomix.o obj-$(CONFIG_CLK_IMX8MQ) +=3D clk-imx8mq.o =20 obj-$(CONFIG_CLK_IMX93) +=3D clk-imx93.o +obj-$(CONFIG_CLK_IMX95_BLK_CTL) +=3D clk-imx95-blk-ctl.o =20 obj-$(CONFIG_MXC_CLK_SCU) +=3D clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-ac= m.o clk-imx-scu-$(CONFIG_CLK_IMX8QXP) +=3D clk-scu.o clk-imx8qxp.o \ diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx9= 5-blk-ctl.c new file mode 100644 index 000000000000..4448b7a3a2a3 --- /dev/null +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + CLK_GATE, + CLK_DIVIDER, + CLK_MUX, +}; + +struct imx95_blk_ctl { + struct device *dev; + spinlock_t lock; + struct clk *clk_apb; + + void __iomem *base; + /* clock gate register */ + u32 clk_reg_restore; +}; + +struct imx95_blk_ctl_clk_dev_data { + const char *name; + const char * const *parent_names; + u32 num_parents; + u32 reg; + u32 bit_idx; + u32 bit_width; + u32 clk_type; + u32 flags; + u32 flags2; + u32 type; +}; + +struct imx95_blk_ctl_dev_data { + const struct imx95_blk_ctl_clk_dev_data *clk_dev_data; + u32 num_clks; + bool rpm_enabled; + u32 clk_reg_offset; +}; + +static const struct imx95_blk_ctl_clk_dev_data vpublk_clk_dev_data[] =3D { + [IMX95_CLK_VPUBLK_WAVE] =3D { + .name =3D "vpublk_wave_vpu", + .parent_names =3D (const char *[]){ "vpu", }, + .num_parents =3D 1, + .reg =3D 8, + .bit_idx =3D 0, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_VPUBLK_JPEG_ENC] =3D { + .name =3D "vpublk_jpeg_enc", + .parent_names =3D (const char *[]){ "vpujpeg", }, + .num_parents =3D 1, + .reg =3D 8, + .bit_idx =3D 1, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_VPUBLK_JPEG_DEC] =3D { + .name =3D "vpublk_jpeg_dec", + .parent_names =3D (const char *[]){ "vpujpeg", }, + .num_parents =3D 1, + .reg =3D 8, + .bit_idx =3D 2, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + } +}; + +static const struct imx95_blk_ctl_dev_data vpublk_dev_data =3D { + .num_clks =3D IMX95_CLK_VPUBLK_END, + .clk_dev_data =3D vpublk_clk_dev_data, + .rpm_enabled =3D true, + .clk_reg_offset =3D 8, +}; + +static const struct imx95_blk_ctl_clk_dev_data camblk_clk_dev_data[] =3D { + [IMX95_CLK_CAMBLK_CSI2_FOR0] =3D { + .name =3D "camblk_csi2_for0", + .parent_names =3D (const char *[]){ "camisi", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 0, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_CAMBLK_CSI2_FOR1] =3D { + .name =3D "camblk_csi2_for1", + .parent_names =3D (const char *[]){ "camisi", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 1, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_CAMBLK_ISP_AXI] =3D { + .name =3D "camblk_isp_axi", + .parent_names =3D (const char *[]){ "camaxi", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 4, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_CAMBLK_ISP_PIXEL] =3D { + .name =3D "camblk_isp_pixel", + .parent_names =3D (const char *[]){ "camisi", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 5, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_CAMBLK_ISP] =3D { + .name =3D "camblk_isp", + .parent_names =3D (const char *[]){ "camisi", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 6, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + } +}; + +static const struct imx95_blk_ctl_dev_data camblk_dev_data =3D { + .num_clks =3D IMX95_CLK_CAMBLK_END, + .clk_dev_data =3D camblk_clk_dev_data, + .clk_reg_offset =3D 0, +}; + +static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] =3D { + [IMX95_CLK_DISPMIX_LVDS_PHY_DIV] =3D { + .name =3D "ldb_phy_div", + .parent_names =3D (const char *[]){ "ldbpll", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 0, + .bit_width =3D 1, + .type =3D CLK_DIVIDER, + .flags2 =3D CLK_DIVIDER_POWER_OF_TWO, + }, + [IMX95_CLK_DISPMIX_LVDS_CH0_GATE] =3D { + .name =3D "lvds_ch0_gate", + .parent_names =3D (const char *[]){ "ldb_phy_div", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 1, + .bit_width =3D 1, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_DISPMIX_LVDS_CH1_GATE] =3D { + .name =3D "lvds_ch1_gate", + .parent_names =3D (const char *[]){ "ldb_phy_div", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 2, + .bit_width =3D 1, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_DISPMIX_PIX_DI0_GATE] =3D { + .name =3D "lvds_di0_gate", + .parent_names =3D (const char *[]){ "ldb_pll_div7", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 3, + .bit_width =3D 1, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, + [IMX95_CLK_DISPMIX_PIX_DI1_GATE] =3D { + .name =3D "lvds_di1_gate", + .parent_names =3D (const char *[]){ "ldb_pll_div7", }, + .num_parents =3D 1, + .reg =3D 0, + .bit_idx =3D 4, + .bit_width =3D 1, + .type =3D CLK_GATE, + .flags =3D CLK_SET_RATE_PARENT, + .flags2 =3D CLK_GATE_SET_TO_DISABLE, + }, +}; + +static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data =3D { + .num_clks =3D IMX95_CLK_DISPMIX_LVDS_CSR_END, + .clk_dev_data =3D lvds_clk_dev_data, + .clk_reg_offset =3D 0, +}; + +static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = =3D { + [IMX95_CLK_DISPMIX_ENG0_SEL] =3D { + .name =3D "disp_engine0_sel", + .parent_names =3D (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7= ", }, + .num_parents =3D 4, + .reg =3D 0, + .bit_idx =3D 0, + .bit_width =3D 2, + .type =3D CLK_MUX, + .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, + }, + [IMX95_CLK_DISPMIX_ENG1_SEL] =3D { + .name =3D "disp_engine1_sel", + .parent_names =3D (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7= ", }, + .num_parents =3D 4, + .reg =3D 0, + .bit_idx =3D 2, + .bit_width =3D 2, + .type =3D CLK_MUX, + .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, + } +}; + +static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data =3D { + .num_clks =3D IMX95_CLK_DISPMIX_END, + .clk_dev_data =3D dispmix_csr_clk_dev_data, + .clk_reg_offset =3D 0, +}; + +static int imx95_bc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + const struct imx95_blk_ctl_dev_data *bc_data; + struct imx95_blk_ctl *bc; + struct clk_hw_onecell_data *clk_hw_data; + struct clk_hw **hws; + void __iomem *base; + int i, ret; + + bc =3D devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL); + if (!bc) + return -ENOMEM; + bc->dev =3D dev; + dev_set_drvdata(&pdev->dev, bc); + + spin_lock_init(&bc->lock); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + bc->base =3D base; + bc->clk_apb =3D devm_clk_get(dev, NULL); + if (IS_ERR(bc->clk_apb)) + return dev_err_probe(dev, PTR_ERR(bc->clk_apb), "failed to get APB clock= \n"); + + ret =3D clk_prepare_enable(bc->clk_apb); + if (ret) { + dev_err(dev, "failed to enable apb clock: %d\n", ret); + return ret; + } + + bc_data =3D of_device_get_match_data(dev); + if (!bc_data) + return devm_of_platform_populate(dev); + + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc_data->= num_clks), + GFP_KERNEL); + if (!clk_hw_data) + return -ENOMEM; + + if (bc_data->rpm_enabled) + pm_runtime_enable(&pdev->dev); + + clk_hw_data->num =3D bc_data->num_clks; + hws =3D clk_hw_data->hws; + + for (i =3D 0; i < bc_data->num_clks; i++) { + const struct imx95_blk_ctl_clk_dev_data *data =3D &bc_data->clk_dev_data= [i]; + void __iomem *reg =3D base + data->reg; + + if (data->type =3D=3D CLK_MUX) { + hws[i] =3D clk_hw_register_mux(dev, data->name, data->parent_names, + data->num_parents, data->flags, reg, + data->bit_idx, data->bit_width, + data->flags2, &bc->lock); + } else if (data->type =3D=3D CLK_DIVIDER) { + hws[i] =3D clk_hw_register_divider(dev, data->name, data->parent_names[= 0], + data->flags, reg, data->bit_idx, + data->bit_width, data->flags2, &bc->lock); + } else { + hws[i] =3D clk_hw_register_gate(dev, data->name, data->parent_names[0], + data->flags, reg, data->bit_idx, + data->flags2, &bc->lock); + } + if (IS_ERR(hws[i])) { + ret =3D PTR_ERR(hws[i]); + dev_err(dev, "failed to register: %s:%d\n", data->name, ret); + goto cleanup; + } + } + + ret =3D of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_h= w_data); + if (ret) + goto cleanup; + + ret =3D devm_of_platform_populate(dev); + if (ret) { + of_clk_del_provider(dev->of_node); + goto cleanup; + } + + if (pm_runtime_enabled(bc->dev)) + clk_disable_unprepare(bc->clk_apb); + + return 0; + +cleanup: + for (i =3D 0; i < bc_data->num_clks; i++) { + if (IS_ERR_OR_NULL(hws[i])) + continue; + clk_hw_unregister(hws[i]); + } + + if (bc_data->rpm_enabled) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +#ifdef CONFIG_PM +static int imx95_bc_runtime_suspend(struct device *dev) +{ + struct imx95_blk_ctl *bc =3D dev_get_drvdata(dev); + + clk_disable_unprepare(bc->clk_apb); + return 0; +} + +static int imx95_bc_runtime_resume(struct device *dev) +{ + struct imx95_blk_ctl *bc =3D dev_get_drvdata(dev); + + return clk_prepare_enable(bc->clk_apb); +} +#endif + +#ifdef CONFIG_PM_SLEEP +static int imx95_bc_suspend(struct device *dev) +{ + struct imx95_blk_ctl *bc =3D dev_get_drvdata(dev); + const struct imx95_blk_ctl_dev_data *bc_data; + int ret; + + bc_data =3D of_device_get_match_data(dev); + if (!bc_data) + return 0; + + if (bc_data->rpm_enabled) { + ret =3D pm_runtime_get_sync(bc->dev); + if (ret < 0) { + pm_runtime_put_noidle(bc->dev); + return ret; + } + } + + bc->clk_reg_restore =3D readl(bc->base + bc_data->clk_reg_offset); + + return 0; +} + +static int imx95_bc_resume(struct device *dev) +{ + struct imx95_blk_ctl *bc =3D dev_get_drvdata(dev); + const struct imx95_blk_ctl_dev_data *bc_data; + + bc_data =3D of_device_get_match_data(dev); + if (!bc_data) + return 0; + + writel(bc->clk_reg_restore, bc->base + bc_data->clk_reg_offset); + + if (bc_data->rpm_enabled) + pm_runtime_put(bc->dev); + + return 0; +} +#endif + +static const struct dev_pm_ops imx95_bc_pm_ops =3D { + SET_RUNTIME_PM_OPS(imx95_bc_runtime_suspend, imx95_bc_runtime_resume, NUL= L) + SET_SYSTEM_SLEEP_PM_OPS(imx95_bc_suspend, imx95_bc_resume) +}; + +static const struct of_device_id imx95_bc_of_match[] =3D { + { .compatible =3D "nxp,imx95-cameramix-csr", .data =3D &camblk_dev_data }, + { .compatible =3D "nxp,imx95-display-master-csr", }, + { .compatible =3D "nxp,imx95-dispmix-lvds-csr", .data =3D &lvds_csr_dev_d= ata }, + { .compatible =3D "nxp,imx95-dispmix-csr", .data =3D &dispmix_csr_dev_dat= a }, + { .compatible =3D "nxp,imx95-netcmix-blk-ctrl", }, + { .compatible =3D "nxp,imx95-vpumix-csr", .data =3D &vpublk_dev_data }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx95_blk_ctl_match); + +static struct platform_driver imx95_bc_driver =3D { + .probe =3D imx95_bc_probe, + .driver =3D { + .name =3D "imx95-blk-ctl", + .of_match_table =3D of_match_ptr(imx95_bc_of_match), + .pm =3D &imx95_bc_pm_ops, + }, +}; +module_platform_driver(imx95_bc_driver); + +MODULE_DESCRIPTION("NXP i.MX95 blk ctl driver"); +MODULE_LICENSE("GPL"); --=20 2.37.1