From nobody Sat Feb 7 16:05:45 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27CEA1EB40; Tue, 27 Feb 2024 16:47:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052445; cv=none; b=CAnoD0gjI+ONa82pgey94FVMlmmh0lME1EPOw5FZ/lrLII8jfKx7scMisgpe6w76LobK/bnLxYeo51jsfKTVr4FPA8ztR2nmhZUrWTnvUr6t+DROlEgNGcxQU1KTIVE82i2ksyiITo71hh9X/799/Mkr7kTU+WV07BeGUH4Kuik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052445; c=relaxed/simple; bh=lB9WvV3bGuw1pVIKL43i9Syk3YH1W07y1NHUAoHcvbk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VBtVyUs9oS5KjEKXtvc0KDJ5ggHPhlWMxJN0YnvATxW7NsCu76lzbvATfelIIk8ySodK7FeIAnwfXapZ7sZZ7NnLv3Qwkuiox24O2GF60fOC3+OZCTJk4tHfFxLNncU6tW/Gx/8cdA5Fa5fzsSCRYq501qwFUkoxQZG3kODixjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i53875b6c.versanet.de ([83.135.91.108] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rf0bk-0006qV-IF; Tue, 27 Feb 2024 17:47:08 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, quentin.schulz@theobroma-systems.com, heiko@sntech.de, Heiko Stuebner , Sugar Zhang , Cristian Ciocaltea Subject: [PATCH 1/4] arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s Date: Tue, 27 Feb 2024 17:46:56 +0100 Message-Id: <20240227164659.705271-2-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240227164659.705271-1-heiko@sntech.de> References: <20240227164659.705271-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner The rockchip,trcm-sync-tx-only property is at this time only documented for the tdm variant of Rockchip i2s controllers. While there was a series [0] adding code and binding for the property, it doesn't seem to have gone forward back in 2021. So for now fix the devicetree check by removing the property from rk3588 i2s controllers until support for it gets merged. [0] https://patchwork.kernel.org/project/linux-rockchip/patch/1629796734-42= 43-5-git-send-email-sugar.zhang@rock-chips.com/ Fixes: 8ae112a5554f ("arm64: dts: rockchip: Add rk3588s I2S nodes") Cc: Sugar Zhang Cc: Cristian Ciocaltea Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 36b1b7acfe6a1..82350ddb262f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1704,7 +1704,6 @@ i2s2_2ch: i2s@fe490000 { dmas =3D <&dmac1 0>, <&dmac1 1>; dma-names =3D "tx", "rx"; power-domains =3D <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2s2m1_lrck &i2s2m1_sclk @@ -1725,7 +1724,6 @@ i2s3_2ch: i2s@fe4a0000 { dmas =3D <&dmac1 2>, <&dmac1 3>; dma-names =3D "tx", "rx"; power-domains =3D <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; pinctrl-names =3D "default"; pinctrl-0 =3D <&i2s3_lrck &i2s3_sclk --=20 2.39.2 From nobody Sat Feb 7 16:05:45 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B240F1D698; Tue, 27 Feb 2024 16:47:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052445; cv=none; b=S60NyuQ8vIKtGbvOzyw34XURpsP2BbSjErcC/0lykj+d2fMQLGZNJ4deTDwNn2/RPJLpw6IAwCtat4qe95o5l+htSz8/RAtHo28xjyoSgw0xsBkmMf0rHPfi1JhVr1XuwlwLMCviGLqB/kbsx8boH2aX0w4jprVjaneagl4BLhs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052445; c=relaxed/simple; bh=4YgqCK8WBP7AmGB7o9PSymrPmWweUxISragNOxh6s0A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nsLoLNLF9It+76giP4u3EJyLOPDX9eRfvDVicklwllbmWZBjfnTh9GF2ezmlkrRMPLJZrfXYXBwRuugos0M0o+TGJK1Nkqjhl0WDwIpkToTv3SIkSe8tEuQDC1N2l/kKvdzXXKQ/X9I5tvECr3xxAHUNvrvkvBaPi1i4GGoXec0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i53875b6c.versanet.de ([83.135.91.108] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rf0bl-0006qV-2r; Tue, 27 Feb 2024 17:47:09 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, quentin.schulz@theobroma-systems.com, heiko@sntech.de, Heiko Stuebner Subject: [PATCH 2/4] dt-bindings: arm: rockchip: Add Theobroma-Systems RK3588 Q7 with baseboard Date: Tue, 27 Feb 2024 17:46:57 +0100 Message-Id: <20240227164659.705271-3-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240227164659.705271-1-heiko@sntech.de> References: <20240227164659.705271-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Add binding for the Tiger Q7 SoM when used in conjunction with the Haikou baseboard. Signed-off-by: Heiko Stuebner Acked-by: Krzysztof Kozlowski Reviewed-by: Quentin Schulz --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 5cf5cbef2cf55..864d7c77077e4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -898,6 +898,12 @@ properties: - const: tsd,rk3588-jaguar - const: rockchip,rk3588 =20 + - description: Theobroma Systems RK3588-Q7 with Haikou baseboard + items: + - const: tsd,rk3588-tiger-haikou + - const: tsd,rk3588-tiger + - const: rockchip,rk3588 + - description: Tronsmart Orion R68 Meta items: - const: tronsmart,orion-r68-meta --=20 2.39.2 From nobody Sat Feb 7 16:05:45 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A4AB200DE; Tue, 27 Feb 2024 16:47:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052445; cv=none; b=VSVzTaudn7lKUc66Pma+FUzIVkS5NGDUGmgbHjdpZKJs+4CzBI9X8PvvzNnjeNnaUpBuHDgfuR4hOY0daUC6yozq0stog14g0upjPCk4wsOaM0LWh5tRXYI6HBSSSjkFFPeNHHBLVj18jk/9JUwkEJfovZXOoTrsgahms5XvmjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052445; c=relaxed/simple; bh=xMgc+bR0iC2SFq1Xjk4R1zvMmiTeDJ/Jqvvtl191vO8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SZJI0swZzg99xRUihlt7sja8rDSgMgQi0bxoA4BZo1O574RKlatjh2Or4WaAGAeSVb8fI1zrcIlRlZwGn8c6wSkQap6GwVsbeC3lDvgTojPHq0OpG/EAkgrBw0bkRdaFKAGADcJSDuSFToKpPzDRKH3ZwNZasKm593H2gjHSW/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i53875b6c.versanet.de ([83.135.91.108] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rf0bl-0006qV-Jf; Tue, 27 Feb 2024 17:47:09 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, quentin.schulz@theobroma-systems.com, heiko@sntech.de, Heiko Stuebner Subject: [PATCH 3/4] arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM Date: Tue, 27 Feb 2024 17:46:58 +0100 Message-Id: <20240227164659.705271-4-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240227164659.705271-1-heiko@sntech.de> References: <20240227164659.705271-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector * Gigabit Ethernet with on-module GbE PHY * HDMI/eDP * MIPI-DSI * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) * HDMI input over FPC connector * CAN * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host * PCIe - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes * on-module ATtiny816 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- .../arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 691 ++++++++++++++++++ 1 file changed, 691 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi new file mode 100644 index 0000000000000..bb24044e27f2c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + compatible =3D "tsd,rk3588-tiger", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + rtc0 =3D &rtc_twi; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-0 =3D <&emmc_reset>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&module_led_pin>; + + /* Named LED1 on the board */ + led-1 { + gpios =3D <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_HEARTBEAT; + linux,default-trigger =3D "heartbeat"; + color =3D ; + }; + }; + + /* + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE + * clock generator. + * The clock output is gated via the OE pin on the clock generator. + * This is modeled as a fixed-clock plus a gpio-gate-clock. + */ + pcie_refclk_gen: pcie-refclk-gen-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + pcie_refclk: pcie-refclk-clock { + compatible =3D "gpio-gate-clock"; + clocks =3D <&pcie_refclk_gen>; + #clock-cells =3D <0>; + enable-gpios =3D <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M= 1_L */ + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc_1v2_s3: vcc-1v2-s3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v2_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_baseboard>; + }; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii"; + phy-supply =3D <&vcc_1v2_s3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_rx_bus2 + &gmac0_tx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins + ð_reset>; + tx_delay =3D <0x10>; + rx_delay =3D <0x10>; + snps,reset-gpio =3D <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 10000 100000>; +}; + +&i2c1 { + pinctrl-0 =3D <&i2c1m0_xfer>; +}; + +&i2c1m0_xfer { + rockchip,pins =3D + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2m3_xfer>; + status =3D "okay"; +}; + +&i2c2m3_xfer { + rockchip,pins =3D + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c3 { + pinctrl-0 =3D <&i2c3m0_xfer>; +}; + +&i2c4 { + pinctrl-0 =3D <&i2c4m4_xfer>; + status =3D "okay"; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + pinctrl-0 =3D <&i2c5m1_xfer>; +}; + +&i2c5m1_xfer { + rockchip,pins =3D + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c6 { + status =3D "okay"; + + /* + * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus, + * but SOC can handle only up to (400kHz). + */ + clock-frequency =3D <400000>; + + fan@18 { + compatible =3D "ti,amc6821"; + reg =3D <0x18>; + }; + + rtc_twi: rtc@6f { + compatible =3D "isil,isl1208"; + reg =3D <0x6f>; + }; +}; + +&i2c6m0_xfer { + rockchip,pins =3D + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c7 { + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c7m0_xfer { + rockchip,pins =3D + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c8 { + pinctrl-0 =3D <&i2c8m2_xfer>; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@6 { + /* KSZ9031 or KSZ9131 */ + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x6>; + clocks =3D <&cru REFCLKO25M_ETH0_OUT>; + }; +}; + +&pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks =3D <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie_refclk>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + reset-gpios =3D <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins =3D <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + eth_reset: eth-reset { + rockchip,pins =3D <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + module_led_pin: module-led-pin { + rockchip,pins =3D <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply =3D <&vcc_1v8_s0>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-pwrseq =3D <&emmc_pwrseq>; + no-sdio; + no-sd; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; + supports-cqe; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vcc_1v8_s3>; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + max-frequency =3D <150000000>; + vqmmc-supply =3D <&vccio_sd_s0>; +}; + +&spi0 { + pinctrl-0 =3D <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; +}; + +&spi2 { + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + num-cs =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + status =3D "okay"; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency =3D <1000000>; + system-power-controller; + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name =3D "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name =3D "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name =3D "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name =3D "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name =3D "vcc_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name =3D "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name =3D "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name =3D "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-name =3D "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name =3D "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name =3D "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name =3D "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name =3D "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name =3D "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name =3D "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name =3D "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name =3D "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name =3D "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name =3D "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status =3D "okay"; +}; + +/* Mule-ATtiny UPDI */ +&uart4 { + pinctrl-0 =3D <&uart4m2_xfer>; + status =3D "okay"; +}; --=20 2.39.2 From nobody Sat Feb 7 16:05:45 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27D2A200DB; Tue, 27 Feb 2024 16:47:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052444; cv=none; b=Rrdq47dwlUTcPJ7YuWQ1GHW9hHqkV4ewRMLNPx8GrZDjMprbofaXK0reHrOIvNlfbAB2wPd3nkMjqYeeKWMM2ea2sg/Ko+6QSLeS2kvKulmmqOzax3/MMqvAUumopHhKpSgj7vCJhjlRLCjHDI8/Uqv9ZH9t9PcM8/gS0HSjZLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709052444; c=relaxed/simple; bh=UeZjUsiTKcYCzP2F1s53IBwax22EOM05dQxjQiIM2ms=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=psWargEGIK5vQ0j6iZ4+8vgGSoWKbrCMChMTSYvDkHTXmpRABGzRelzJxq8mBFn2cemP0OgTyURlzwuqgJpqcPvrpZDd8lY/wzDLNyfCGs1ihTwbBAsGBzelgUVQXk9RPFpeYuodbezBTtxWyS0nnFWZ18mIaNhnddY1SDuiq10= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i53875b6c.versanet.de ([83.135.91.108] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rf0bm-0006qV-3l; Tue, 27 Feb 2024 17:47:10 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, quentin.schulz@theobroma-systems.com, heiko@sntech.de, Heiko Stuebner Subject: [PATCH 4/4] arm64: dts: rockchip: add Haikou baseboard with RK3588-Q7 SoM Date: Tue, 27 Feb 2024 17:46:59 +0100 Message-Id: <20240227164659.705271-5-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240227164659.705271-1-heiko@sntech.de> References: <20240227164659.705271-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Heiko Stuebner Haikou is a Qseven and =CE=BCQseven baseboard featuring PCIe, USB3 and a video connector for a MIPI-DSI/CSI adapter. This dts is for usage with the RK3588-Q7 SoM Tiger. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-tiger-haikou.dts | 266 ++++++++++++++++++ 2 files changed, 267 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index a7b30e11beaf4..a44a9e15c9f62 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-turing-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-indiedroid-nova.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/ar= m64/boot/dts/rockchip/rk3588-tiger-haikou.dts new file mode 100644 index 0000000000000..c9340923dcb98 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include +#include "rk3588-tiger.dtsi" + +/ { + model =3D "Theobroma Systems RK3588-Q7 SoM on Haikou devkit"; + compatible =3D "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger", "rockchip,r= k3588"; + + aliases { + ethernet0 =3D &gmac0; + mmc1 =3D &sdmmc; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + dc_12v: dc-12v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&haikou_keys_pin>; + + button-batlow-n { + label =3D "BATLOW#"; + linux,code =3D ; + gpios =3D <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + }; + + button-slp-btn-n { + label =3D "SLP_BTN#"; + linux,code =3D ; + gpios =3D <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + button-wake-n { + label =3D "WAKE#"; + linux,code =3D ; + gpios =3D <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-lid-btn-n { + label =3D "LID_BTN#"; + linux,code =3D ; + linux,input-type =3D ; + gpios =3D <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + }; + + i2s3-sound { + compatible =3D "simple-audio-card"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,name =3D "Haikou,I2S-codec"; + simple-audio-card,mclk-fs =3D <512>; + simple-audio-card,frame-master =3D <&sgtl5000_codec>; + simple-audio-card,bitclock-master =3D <&sgtl5000_codec>; + + sgtl5000_codec: simple-audio-card,codec { + sound-dai =3D <&sgtl5000>; + }; + + simple-audio-card,cpu { + sound-dai =3D <&i2s3_2ch>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24576000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&dc_12v>; + }; + + vcc3v3_low_noise: vcc3v3-low-noise-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_low_noise"; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_usb>; + }; + + vcc5v0_baseboard: vcc5v0-baseboard-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vddd_audio_1v6: vddd-audio-1v6-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vddd_audio_1v6"; + regulator-boot-on; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <1600000>; + vin-supply =3D <&vcc5v0_usb>; + }; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + + eeprom@50 { + reg =3D <0x50>; + compatible =3D "atmel,24c01"; + pagesize =3D <8>; + size =3D <128>; + vcc-supply =3D <&vcc3v3_baseboard>; + }; +}; + +&i2c5 { + status =3D "okay"; + clock-frequency =3D <400000>; + + sgtl5000: codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + clocks =3D <&sgtl5000_clk>; + #sound-dai-cells =3D <0>; + VDDA-supply =3D <&vcc3v3_low_noise>; + VDDIO-supply =3D <&vcc3v3_baseboard>; + VDDD-supply =3D <&vddd_audio_1v6>; + }; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2s3_2ch { + status =3D "okay"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + vpcie3v3-supply =3D <&vcc3v3_baseboard>; + status =3D "okay"; +}; + +&pinctrl { + haikou { + haikou_keys_pin: haikou-keys-pin { + rockchip,pins =3D + /* BATLOW# */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + /* WAKE# */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, + /* LID_BTN */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + /* while the same pin, sdmmc_det does not detect card changes */ + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-0 =3D <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_baseboard>; + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m2_xfer>; + status =3D "okay"; +}; + +&uart5 { + rts-gpios =3D <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +/* host0 on Q7_USB_P2, lower usb3 port */ +&usb_host0_ehci { + status =3D "okay"; +}; + +/* host0 on Q7_USB_P2, lower usb3 port */ +&usb_host0_ohci { + status =3D "okay"; +}; + +/* host1 on Q7_USB_P3, usb2 port */ +&usb_host1_ehci { + status =3D "okay"; +}; + +/* host1 on Q7_USB_P3, usb2 port */ +&usb_host1_ohci { + status =3D "okay"; +}; + +/* host2 on Q7_USB_P2, lower usb3 port */ +&usb_host2_xhci { + status =3D "okay"; +}; --=20 2.39.2