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charset="utf-8" From: Lucas Stach Add a DT binding for the HDMI PHY found on the i.MX8MP SoC. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Reviewed-by: Luca Ceresoli --- V6: No Change V5: No Change V4: No Change V3: Removed mintems at the request of Krzysztof and add his reviewed-by V2: I (Adam) tried to help move this along, so I took Lucas' patch and attempted to apply fixes based on feedback. I don't have all the history, so apologies for that. Added phy-cells to the required list and fixed an error due to the word 'binding' being in the title. --- .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-p= hy.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml= b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml new file mode 100644 index 000000000000..c43e86a8c2e0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI PHY + +maintainers: + - Lucas Stach + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi-phy + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: apb + - const: ref + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + + phy@32fdff00 { + compatible =3D "fsl,imx8mp-hdmi-phy"; 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Mon, 26 Feb 2024 15:45:40 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Lucas Stach , Luca Ceresoli , Richard Leitner , Marco Felsch , Alexander Stein , Frieder Schrempf , Adam Ford , Marek Vasut , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V6 2/6] phy: freescale: add Samsung HDMI PHY Date: Mon, 26 Feb 2024 17:45:13 -0600 Message-ID: <20240226234532.80114-3-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240226234532.80114-1-aford173@gmail.com> References: <20240226234532.80114-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lucas Stach This adds the driver for the Samsung HDMI PHY found on the i.MX8MP SoC. Based on downstream implementation from Sandor Yu . According to the TRM, the PHY receives parallel data from the link and serializes it. It also sets the PLL clock needed for the TX serializer. Tested-by: Luca Ceresoli (v2) Tested-by: Richard Leitner (v2) Co-developed-by: Marco Felsch Signed-off-by: Marco Felsch Signed-off-by: Lucas Stach Tested-by: Alexander Stein Tested-by: Frieder Schrempf # Kontron BL Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli --- V6: Set Kconfig dependency to include COMMON_CLK due to build errors V5: Remove an unnecessary include Migrate from of_clk_add_provider to of_clk_add_hw_provider Make const structures static Fix uninitialized variables and prevent div by 0 Mark PM functions as __maybe_unused V4: - I (Adam) added a comment in the code for clarifcation based on questions from Luca concerning a difference between the code and the ref manual. - Fixed the GENMASK on REG14 - Expanded the commit message briefly describing a bit more of what this driver does. - Removed some unnecessary include files. v3: - use GENMASK/FIELD_PREP - lowercase hex values - correct coding style v2: - use DEFINE_RUNTIME_DEV_PM_OPS --- drivers/phy/freescale/Kconfig | 6 + drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 720 +++++++++++++++++++ 3 files changed, 727 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 853958fb2c06..45aaaea14fb4 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE Enable this to add support for the PCIE PHY as found on i.MX8M family of SOCs. =20 +config PHY_FSL_SAMSUNG_HDMI_PHY + tristate "Samsung HDMI PHY support" + depends on OF && HAS_IOMEM && COMMON_CLK + help + Enable this to add support for the Samsung HDMI PHY in i.MX8MP. + endif =20 config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index cedb328bc4d2..c4386bfdb853 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) +=3D phy-fsl-imx8qm-lvds-p= hy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) +=3D phy-fsl-imx8-mipi-dphy.o obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) +=3D phy-fsl-imx8m-pcie.o obj-$(CONFIG_PHY_FSL_LYNX_28G) +=3D phy-fsl-lynx-28g.o +obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) +=3D phy-fsl-samsung-hdmi.o diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c new file mode 100644 index 000000000000..89e2c01f2ccf --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -0,0 +1,720 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * Copyright 2022 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_REG_00 0x00 +#define PHY_REG_01 0x04 +#define PHY_REG_02 0x08 +#define PHY_REG_08 0x20 +#define PHY_REG_09 0x24 +#define PHY_REG_10 0x28 +#define PHY_REG_11 0x2c + +#define PHY_REG_12 0x30 +#define REG12_CK_DIV_MASK GENMASK(5, 4) + +#define PHY_REG_13 0x34 +#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) + +#define PHY_REG_14 0x38 +#define REG14_TOL_MASK GENMASK(7, 4) +#define REG14_RP_CODE_MASK GENMASK(3, 1) +#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) + +#define PHY_REG_15 0x3c +#define PHY_REG_16 0x40 +#define PHY_REG_17 0x44 +#define PHY_REG_18 0x48 +#define PHY_REG_19 0x4c +#define PHY_REG_20 0x50 + +#define PHY_REG_21 0x54 +#define REG21_SEL_TX_CK_INV BIT(7) +#define REG21_PMS_S_MASK GENMASK(3, 0) + +#define PHY_REG_22 0x58 +#define PHY_REG_23 0x5c +#define PHY_REG_24 0x60 +#define PHY_REG_25 0x64 +#define PHY_REG_26 0x68 +#define PHY_REG_27 0x6c +#define PHY_REG_28 0x70 +#define PHY_REG_29 0x74 +#define PHY_REG_30 0x78 +#define PHY_REG_31 0x7c +#define PHY_REG_32 0x80 + +/* + * REG33 does not match the ref manual. According to Sandor Yu from NXP, + * "There is a doc issue on the i.MX8MP latest RM" + * REG33 is being used per guidance from Sandor + */ + +#define PHY_REG_33 0x84 +#define REG33_MODE_SET_DONE BIT(7) +#define REG33_FIX_DA BIT(1) + +#define PHY_REG_34 0x88 +#define REG34_PHY_READY BIT(7) +#define REG34_PLL_LOCK BIT(6) +#define REG34_PHY_CLK_READY BIT(5) + +#define PHY_REG_35 0x8c +#define PHY_REG_36 0x90 +#define PHY_REG_37 0x94 +#define PHY_REG_38 0x98 +#define PHY_REG_39 0x9c +#define PHY_REG_40 0xa0 +#define PHY_REG_41 0xa4 +#define PHY_REG_42 0xa8 +#define PHY_REG_43 0xac +#define PHY_REG_44 0xb0 +#define PHY_REG_45 0xb4 +#define PHY_REG_46 0xb8 +#define PHY_REG_47 0xbc + +#define PHY_PLL_DIV_REGS_NUM 6 + +struct phy_config { + u32 pixclk; + u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM]; +}; + +static const struct phy_config phy_pll_cfg[] =3D { + { + .pixclk =3D 22250000, + .pll_div_regs =3D { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk =3D 23750000, + .pll_div_regs =3D { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, + }, { + .pixclk =3D 24000000, + .pll_div_regs =3D { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 24024000, + .pll_div_regs =3D { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, + }, { + .pixclk =3D 25175000, + .pll_div_regs =3D { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, + }, { + .pixclk =3D 25200000, + .pll_div_regs =3D { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 26750000, + .pll_div_regs =3D { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk =3D 27000000, + .pll_div_regs =3D { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 27027000, + .pll_div_regs =3D { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk =3D 29500000, + .pll_div_regs =3D { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, + }, { + .pixclk =3D 30750000, + .pll_div_regs =3D { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk =3D 30888000, + .pll_div_regs =3D { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, + }, { + .pixclk =3D 33750000, + .pll_div_regs =3D { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, + }, { + .pixclk =3D 35000000, + .pll_div_regs =3D { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, + }, { + .pixclk =3D 36000000, + .pll_div_regs =3D { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 36036000, + .pll_div_regs =3D { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk =3D 40000000, + .pll_div_regs =3D { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 43200000, + .pll_div_regs =3D { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 43243200, + .pll_div_regs =3D { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk =3D 44500000, + .pll_div_regs =3D { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, + }, { + .pixclk =3D 47000000, + .pll_div_regs =3D { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, + }, { + .pixclk =3D 47500000, + .pll_div_regs =3D { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, + }, { + .pixclk =3D 50349650, + .pll_div_regs =3D { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, + }, { + .pixclk =3D 50400000, + .pll_div_regs =3D { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 53250000, + .pll_div_regs =3D { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, + }, { + .pixclk =3D 53500000, + .pll_div_regs =3D { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk =3D 54000000, + .pll_div_regs =3D { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 54054000, + .pll_div_regs =3D { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk =3D 59000000, + .pll_div_regs =3D { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, + }, { + .pixclk =3D 59340659, + .pll_div_regs =3D { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, + }, { + .pixclk =3D 59400000, + .pll_div_regs =3D { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 61500000, + .pll_div_regs =3D { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk =3D 63500000, + .pll_div_regs =3D { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, + }, { + .pixclk =3D 67500000, + .pll_div_regs =3D { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, + }, { + .pixclk =3D 70000000, + .pll_div_regs =3D { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, + }, { + .pixclk =3D 72000000, + .pll_div_regs =3D { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 72072000, + .pll_div_regs =3D { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk =3D 74176000, + .pll_div_regs =3D { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, + }, { + .pixclk =3D 74250000, + .pll_div_regs =3D { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, + }, { + .pixclk =3D 78500000, + .pll_div_regs =3D { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, + }, { + .pixclk =3D 80000000, + .pll_div_regs =3D { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 82000000, + .pll_div_regs =3D { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk =3D 82500000, + .pll_div_regs =3D { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, + }, { + .pixclk =3D 89000000, + .pll_div_regs =3D { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, + }, { + .pixclk =3D 90000000, + .pll_div_regs =3D { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, + }, { + .pixclk =3D 94000000, + .pll_div_regs =3D { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, + }, { + .pixclk =3D 95000000, + .pll_div_regs =3D { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, + }, { + .pixclk =3D 98901099, + .pll_div_regs =3D { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, + }, { + .pixclk =3D 99000000, + .pll_div_regs =3D { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, + }, { + .pixclk =3D 100699300, + .pll_div_regs =3D { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, + }, { + .pixclk =3D 100800000, + .pll_div_regs =3D { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 102500000, + .pll_div_regs =3D { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, + }, { + .pixclk =3D 104750000, + .pll_div_regs =3D { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, + }, { + .pixclk =3D 106500000, + .pll_div_regs =3D { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, + }, { + .pixclk =3D 107000000, + .pll_div_regs =3D { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk =3D 108000000, + .pll_div_regs =3D { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 108108000, + .pll_div_regs =3D { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk =3D 118000000, + .pll_div_regs =3D { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, + }, { + .pixclk =3D 118800000, + .pll_div_regs =3D { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 123000000, + .pll_div_regs =3D { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk =3D 127000000, + .pll_div_regs =3D { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, + }, { + .pixclk =3D 135000000, + .pll_div_regs =3D { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, + }, { + .pixclk =3D 135580000, + .pll_div_regs =3D { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, + }, { + .pixclk =3D 137520000, + .pll_div_regs =3D { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, + }, { + .pixclk =3D 138750000, + .pll_div_regs =3D { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, + }, { + .pixclk =3D 140000000, + .pll_div_regs =3D { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, + }, { + .pixclk =3D 144000000, + .pll_div_regs =3D { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 148352000, + .pll_div_regs =3D { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, + }, { + .pixclk =3D 148500000, + .pll_div_regs =3D { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, + }, { + .pixclk =3D 154000000, + .pll_div_regs =3D { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, + }, { + .pixclk =3D 157000000, + .pll_div_regs =3D { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, + }, { + .pixclk =3D 160000000, + .pll_div_regs =3D { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, + }, { + .pixclk =3D 162000000, + .pll_div_regs =3D { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, + }, { + .pixclk =3D 164000000, + .pll_div_regs =3D { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, + }, { + .pixclk =3D 165000000, + .pll_div_regs =3D { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, + }, { + .pixclk =3D 180000000, + .pll_div_regs =3D { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 185625000, + .pll_div_regs =3D { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, + }, { + .pixclk =3D 188000000, + .pll_div_regs =3D { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, + }, { + .pixclk =3D 198000000, + .pll_div_regs =3D { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, + }, { + .pixclk =3D 205000000, + .pll_div_regs =3D { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, + }, { + .pixclk =3D 209500000, + .pll_div_regs =3D { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, + }, { + .pixclk =3D 213000000, + .pll_div_regs =3D { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, + }, { + .pixclk =3D 216000000, + .pll_div_regs =3D { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 216216000, + .pll_div_regs =3D { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk =3D 237600000, + .pll_div_regs =3D { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 254000000, + .pll_div_regs =3D { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, + }, { + .pixclk =3D 277500000, + .pll_div_regs =3D { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, + }, { + .pixclk =3D 288000000, + .pll_div_regs =3D { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk =3D 297000000, + .pll_div_regs =3D { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, + }, +}; + +struct reg_settings { + u8 reg; + u8 val; +}; + +static const struct reg_settings common_phy_cfg[] =3D { + { PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 }, + { PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 }, + { PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 }, + /* REG12 pixclk specific */ + /* REG13 pixclk specific */ + /* REG14 pixclk specific */ + { PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c }, + { PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 }, + { PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 }, + /* REG21 pixclk specific */ + { PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 }, + { PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f }, + { PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 }, + { PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 }, + { PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 }, + { PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 }, + { PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 }, + { PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 }, + { PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 }, + { PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 }, + { PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f }, + { PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 }, + { PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 } +}; + +struct fsl_samsung_hdmi_phy { + struct device *dev; + void __iomem *regs; + struct clk *apbclk; + struct clk *refclk; + + /* clk provider */ + struct clk_hw hw; + const struct phy_config *cur_cfg; +}; + +static inline struct fsl_samsung_hdmi_phy * +to_fsl_samsung_hdmi_phy(struct clk_hw *hw) +{ + return container_of(hw, struct fsl_samsung_hdmi_phy, hw); +} + +static void +fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *cfg) +{ + u8 div =3D 0x1; + + switch (cfg->pixclk) { + case 22250000 ... 33750000: + div =3D 0xf; + break; + case 35000000 ... 40000000: + div =3D 0xb; + break; + case 43200000 ... 47500000: + div =3D 0x9; + break; + case 50349650 ... 63500000: + div =3D 0x7; + break; + case 67500000 ... 90000000: + div =3D 0x5; + break; + case 94000000 ... 148500000: + div =3D 0x3; + break; + case 154000000 ... 297000000: + div =3D 0x1; + break; + } + + writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), + phy->regs + PHY_REG_21); +} + +static void +fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *p= hy, + const struct phy_config *cfg) +{ + u32 pclk =3D cfg->pixclk; + u32 fld_tg_code; + u32 pclk_khz; + u8 div =3D 1; + + switch (cfg->pixclk) { + case 22250000 ... 47500000: + div =3D 1; + break; + case 50349650 ... 99000000: + div =3D 2; + break; + case 100699300 ... 198000000: + div =3D 4; + break; + case 205000000 ... 297000000: + div =3D 8; + break; + } + + writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12); + + /* + * Calculation for the frequency lock detector target code (fld_tg_code) + * is based on reference manual register description of PHY_REG13 + * (13.10.3.1.14.2): + * 1st) Calculate int_pllclk which is determinded by FLD_CK_DIV + * 2nd) Increase resolution to avoid rounding issues + * 3th) Do the div (256 / Freq. of int_pllclk) * 24 + * 4th) Reduce the resolution and always round up since the NXP + * settings rounding up always too. TODO: Check if that is + * correct. + */ + pclk /=3D div; + pclk_khz =3D pclk / 1000; + fld_tg_code =3D 256 * 1000 * 1000 / pclk_khz * 24; + fld_tg_code =3D DIV_ROUND_UP(fld_tg_code, 1000); + + /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ + writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), + phy->regs + PHY_REG_13); + writeb(FIELD_PREP(REG14_TOL_MASK, 2) | + FIELD_PREP(REG14_RP_CODE_MASK, 2) | + FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), + phy->regs + PHY_REG_14); +} + +static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *cfg) +{ + int i, ret; + u8 val; + + /* HDMI PHY init */ + writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); + + /* common PHY registers */ + for (i =3D 0; i < ARRAY_SIZE(common_phy_cfg); i++) + writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg); + + /* set individual PLL registers PHY_REG2 ... PHY_REG7 */ + for (i =3D 0; i < PHY_PLL_DIV_REGS_NUM; i++) + writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4); + + fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); + fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); + + writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33); + + ret =3D readb_poll_timeout(phy->regs + PHY_REG_34, val, + val & REG34_PLL_LOCK, 50, 20000); + if (ret) + dev_err(phy->dev, "PLL failed to lock\n"); + + return ret; +} + +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); + + if (!phy->cur_cfg) + return 74250000; + + return phy->cur_cfg->pixclk; +} + +static long phy_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + int i; + + for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) + if (phy_pll_cfg[i].pixclk <=3D rate) + return phy_pll_cfg[i].pixclk; + + return -EINVAL; +} + +static int phy_clk_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); + int i; + + for (i =3D ARRAY_SIZE(phy_pll_cfg) - 1; i >=3D 0; i--) + if (phy_pll_cfg[i].pixclk <=3D rate) + break; + + if (i < 0) + return -EINVAL; + + phy->cur_cfg =3D &phy_pll_cfg[i]; + + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); +} + +static const struct clk_ops phy_clk_ops =3D { + .recalc_rate =3D phy_clk_recalc_rate, + .round_rate =3D phy_clk_round_rate, + .set_rate =3D phy_clk_set_rate, +}; + +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy) +{ + struct device *dev =3D phy->dev; + struct device_node *np =3D dev->of_node; + struct clk_init_data init; + const char *parent_name; + struct clk *phyclk; + int ret; + + parent_name =3D __clk_get_name(phy->refclk); + + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + init.flags =3D 0; + init.name =3D "hdmi_pclk"; + init.ops =3D &phy_clk_ops; + + phy->hw.init =3D &init; + + phyclk =3D devm_clk_register(dev, &phy->hw); + if (IS_ERR(phyclk)) + return dev_err_probe(dev, PTR_ERR(phyclk), + "failed to register clock\n"); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk); + if (ret) + return dev_err_probe(dev, ret, + "failed to register clock provider\n"); + + return 0; +} + +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) +{ + struct fsl_samsung_hdmi_phy *phy; + int ret; + + phy =3D devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + platform_set_drvdata(pdev, phy); + phy->dev =3D &pdev->dev; + + phy->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return PTR_ERR(phy->regs); + + phy->apbclk =3D devm_clk_get(phy->dev, "apb"); + if (IS_ERR(phy->apbclk)) + return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), + "failed to get apb clk\n"); + + phy->refclk =3D devm_clk_get(phy->dev, "ref"); + if (IS_ERR(phy->refclk)) + return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), + "failed to get ref clk\n"); + + ret =3D clk_prepare_enable(phy->apbclk); + if (ret) { + dev_err(phy->dev, "failed to enable apbclk\n"); + return ret; + } + + pm_runtime_get_noresume(phy->dev); + pm_runtime_set_active(phy->dev); + pm_runtime_enable(phy->dev); + + ret =3D phy_clk_register(phy); + if (ret) { + dev_err(&pdev->dev, "register clk failed\n"); + goto register_clk_failed; + } + + pm_runtime_put(phy->dev); + + return 0; + +register_clk_failed: + clk_disable_unprepare(phy->apbclk); + + return ret; +} + +static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + + return 0; +} + +static int __maybe_unused fsl_samsung_hdmi_phy_suspend(struct device *dev) +{ + struct fsl_samsung_hdmi_phy *phy =3D dev_get_drvdata(dev); + + clk_disable_unprepare(phy->apbclk); + + return 0; +} + +static int __maybe_unused fsl_samsung_hdmi_phy_resume(struct device *dev) +{ + struct fsl_samsung_hdmi_phy *phy =3D dev_get_drvdata(dev); + int ret =3D 0; + + ret =3D clk_prepare_enable(phy->apbclk); + if (ret) { + dev_err(phy->dev, "failed to enable apbclk\n"); + return ret; + } + + if (phy->cur_cfg) + ret =3D fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); + + return ret; + +} + +static DEFINE_RUNTIME_DEV_PM_OPS(fsl_samsung_hdmi_phy_pm_ops, + fsl_samsung_hdmi_phy_suspend, + fsl_samsung_hdmi_phy_resume, NULL); + +static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] =3D { + { + .compatible =3D "fsl,imx8mp-hdmi-phy", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match); + +static struct platform_driver fsl_samsung_hdmi_phy_driver =3D { + .probe =3D fsl_samsung_hdmi_phy_probe, + .remove =3D fsl_samsung_hdmi_phy_remove, + .driver =3D { + .name =3D "fsl-samsung-hdmi-phy", + .of_match_table =3D fsl_samsung_hdmi_phy_of_match, + .pm =3D pm_ptr(&fsl_samsung_hdmi_phy_pm_ops), + }, +}; +module_platform_driver(fsl_samsung_hdmi_phy_driver); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sat Feb 7 17:19:47 2026 Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A785C135A5C; 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charset="utf-8" From: Lucas Stach This adds the PGC and HDMI blk-ctrl nodes providing power control for HDMI subsystem peripherals. Signed-off-by: Adam Ford Signed-off-by: Lucas Stach Tested-by: Marek Vasut Tested-by: Luca Ceresoli --- V6: No Change V5: No Change V4: No Change V3: The hdmi_blk_ctrl was in the wrong place, so move it to AIPS4. power-domains@ fixed to read power-domain@ V2: Add missing power-domains hdcp and hrv --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index bfc5c81a5bd4..c9bcb6641de7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -836,6 +836,23 @@ pgc_mediamix: power-domain@10 { <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; =20 + pgc_hdmimix: power-domain@14 { + #power-domain-cells =3D <0>; + reg =3D ; + clocks =3D <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks =3D <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates =3D <500000000>, <133000000>; + }; + + pgc_hdmi_phy: power-domain@15 { + #power-domain-cells =3D <0>; + reg =3D ; + }; + pgc_mipi_phy2: power-domain@16 { #power-domain-cells =3D <0>; reg =3D ; @@ -1889,6 +1906,27 @@ hsio_blk_ctrl: blk-ctrl@32f10000 { #power-domain-cells =3D <1>; #clock-cells =3D <0>; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible =3D "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg =3D <0x32fc0000 0x1000>; + clocks =3D <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names =3D "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains =3D <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; + power-domain-names =3D "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; + #power-domain-cells =3D <1>; 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charset="utf-8" From: Lucas Stach The HDMI irqsteer is a secondary interrupt controller within the HDMI subsystem that maps all HDMI peripheral IRQs into a single upstream IRQ line. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli --- V6: No Change V5: Increase size to 4KB to match the ref manual V2: Add my (Adam) s-o-b and re-order position under AIPS4 --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index c9bcb6641de7..18bfa7d9aa7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1927,6 +1927,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { "hdcp", "hrv"; #power-domain-cells =3D <1>; }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible =3D "fsl,imx-irqsteer"; + reg =3D <0x32fc2000 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + fsl,channel =3D <1>; + fsl,num-irqs =3D <64>; + clocks =3D <&clk IMX8MP_CLK_HDMI_APB>; + clock-names =3D "ipg"; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; 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charset="utf-8" From: Lucas Stach This adds the DT nodes for all the peripherals that make up the HDMI display pipeline. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli Tested-by: Marco Felsch --- V6: Make LCDIF3 disabled by default V5: No change V3: Re-ordered the HDMI parts to properly come after irqstree_hdmi inside AIPS4. Change size of LCDIF3 and PVI to match TRM sizes of 4KB. V2: I took this from Lucas' original submission with the following: Removed extra clock from HDMI-TX since it is now part of the power domain Added interrupt-parent to PVI Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx Added ports to HDMI-tx --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 95 +++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 18bfa7d9aa7f..637b0265b0f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1940,6 +1940,101 @@ irqsteer_hdmi: interrupt-controller@32fc2000 { clock-names =3D "ipg"; power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible =3D "fsl,imx8mp-hdmi-pvi"; + reg =3D <0x32fc4000 0x1000>; + interrupt-parent =3D <&irqsteer_hdmi>; + interrupts =3D <12>; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint =3D <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg =3D <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint =3D <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible =3D "fsl,imx8mp-lcdif"; + reg =3D <0x32fc6000 0x1000>; + interrupt-parent =3D <&irqsteer_hdmi>; + interrupts =3D <8>; + clocks =3D <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names =3D "pix", "axi", "disp_axi"; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + status =3D "disabled"; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint =3D <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible =3D "fsl,imx8mp-hdmi-tx"; + reg =3D <0x32fd8000 0x7eff>; + interrupt-parent =3D <&irqsteer_hdmi>; + interrupts =3D <0>; + clocks =3D <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names =3D "iahb", "isfr", "cec", "pix"; + assigned-clocks =3D <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_266M>; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width =3D <1>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint =3D <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg =3D <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible =3D "fsl,imx8mp-hdmi-phy"; + reg =3D <0x32fdff00 0x100>; + clocks =3D <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names =3D "apb", "ref"; + assigned-clocks =3D <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents =3D <&clk IMX8MP_CLK_24M>; + power-domains =3D <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; }; =20 pcie: pcie@33800000 { --=20 2.43.0 From nobody Sat Feb 7 17:19:47 2026 Received: from mail-io1-f41.google.com (mail-io1-f41.google.com [209.85.166.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 848501369A7; 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Mon, 26 Feb 2024 15:45:49 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9c95:d061:819a:2ab2]) by smtp.gmail.com with ESMTPSA id c25-20020a023319000000b004741cf1e95esm1545317jae.11.2024.02.26.15.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Feb 2024 15:45:49 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Adam Ford , Luca Ceresoli , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , Lucas Stach , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V6 6/6] arm64: defconfig: Enable DRM_IMX8MP_DW_HDMI_BRIDGE as module Date: Mon, 26 Feb 2024 17:45:17 -0600 Message-ID: <20240226234532.80114-7-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240226234532.80114-1-aford173@gmail.com> References: <20240226234532.80114-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The i.MX8M Plus has support for an HDMI transmitter. The video is genereated by lcdif3, routed to the hdmi parallel video interface, then fed to a DW HDMI bridge to support up to 4K video output. Signed-off-by: Adam Ford Reviewed-by: Luca Ceresoli Tested-by: Luca Ceresoli --- V6: No Change V5: Added Review and tested-by from Luca No functional change since V1 --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 34681284043f..ee644d27652b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -887,6 +887,7 @@ CONFIG_DRM_ANALOGIX_ANX7625=3Dm CONFIG_DRM_I2C_ADV7511=3Dm CONFIG_DRM_I2C_ADV7511_AUDIO=3Dy CONFIG_DRM_CDNS_MHDP8546=3Dm +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=3Dm CONFIG_DRM_DW_HDMI_AHB_AUDIO=3Dm CONFIG_DRM_DW_HDMI_CEC=3Dm CONFIG_DRM_IMX_DCSS=3Dm --=20 2.43.0