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Peter Anvin" Subject: [RFC PATCH 69/73] x86/pvm: Implement mmu related PVOPS Date: Mon, 26 Feb 2024 22:36:26 +0800 Message-Id: <20240226143630.33643-70-jiangshanlai@gmail.com> X-Mailer: git-send-email 2.19.1.6.gb485710b In-Reply-To: <20240226143630.33643-1-jiangshanlai@gmail.com> References: <20240226143630.33643-1-jiangshanlai@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lai Jiangshan CR2 is passed directly in the event entry, allowing it to be read directly in PVOPS. Additionally, write_cr3() for context switch needs to notify the hypervisor in its PVOPS. For performance reasons, TLB-related PVOPS utilize hypercalls. Signed-off-by: Lai Jiangshan Signed-off-by: Hou Wenlong --- arch/x86/kernel/pvm.c | 56 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/x86/kernel/pvm.c b/arch/x86/kernel/pvm.c index b4522947374d..1dc2c0fb7daa 100644 --- a/arch/x86/kernel/pvm.c +++ b/arch/x86/kernel/pvm.c @@ -21,6 +21,7 @@ #include =20 DEFINE_PER_CPU_PAGE_ALIGNED(struct pvm_vcpu_struct, pvm_vcpu_struct); +static DEFINE_PER_CPU(unsigned long, pvm_guest_cr3); =20 unsigned long pvm_range_start __initdata; unsigned long pvm_range_end __initdata; @@ -153,6 +154,52 @@ static noinstr void pvm_safe_halt(void) pvm_hypercall0(PVM_HC_IRQ_HALT); } =20 +static noinstr unsigned long pvm_read_cr2(void) +{ + return this_cpu_read(pvm_vcpu_struct.cr2); +} + +static noinstr void pvm_write_cr2(unsigned long cr2) +{ + native_write_cr2(cr2); + this_cpu_write(pvm_vcpu_struct.cr2, cr2); +} + +static unsigned long pvm_read_cr3(void) +{ + return this_cpu_read(pvm_guest_cr3); +} + +static unsigned long pvm_user_pgd(unsigned long pgd) +{ + return pgd | BIT(PTI_PGTABLE_SWITCH_BIT) | BIT(X86_CR3_PTI_PCID_USER_BIT); +} + +static void pvm_write_cr3(unsigned long val) +{ + /* Convert CR3_NO_FLUSH bit to hypercall flags. */ + unsigned long flags =3D ~val >> 63; + unsigned long pgd =3D val & ~X86_CR3_PCID_NOFLUSH; + + this_cpu_write(pvm_guest_cr3, pgd); + pvm_hypercall3(PVM_HC_LOAD_PGTBL, flags, pgd, pvm_user_pgd(pgd)); +} + +static void pvm_flush_tlb_user(void) +{ + pvm_hypercall0(PVM_HC_TLB_FLUSH_CURRENT); +} + +static void pvm_flush_tlb_kernel(void) +{ + pvm_hypercall0(PVM_HC_TLB_FLUSH); +} + +static void pvm_flush_tlb_one_user(unsigned long addr) +{ + pvm_hypercall1(PVM_HC_TLB_INVLPG, addr); +} + void __init pvm_early_event(struct pt_regs *regs) { int vector =3D regs->orig_ax >> 32; @@ -397,6 +444,15 @@ void __init pvm_early_setup(void) pv_ops.irq.irq_enable =3D __PV_IS_CALLEE_SAVE(pvm_irq_enable); pv_ops.irq.safe_halt =3D pvm_safe_halt; =20 + this_cpu_write(pvm_guest_cr3, __native_read_cr3()); + pv_ops.mmu.read_cr2 =3D __PV_IS_CALLEE_SAVE(pvm_read_cr2); + pv_ops.mmu.write_cr2 =3D pvm_write_cr2; + pv_ops.mmu.read_cr3 =3D pvm_read_cr3; + pv_ops.mmu.write_cr3 =3D pvm_write_cr3; + pv_ops.mmu.flush_tlb_user =3D pvm_flush_tlb_user; + pv_ops.mmu.flush_tlb_kernel =3D pvm_flush_tlb_kernel; + pv_ops.mmu.flush_tlb_one_user =3D pvm_flush_tlb_one_user; + wrmsrl(MSR_PVM_VCPU_STRUCT, __pa(this_cpu_ptr(&pvm_vcpu_struct))); wrmsrl(MSR_PVM_EVENT_ENTRY, (unsigned long)(void *)pvm_early_kernel_event= _entry - 256); wrmsrl(MSR_PVM_SUPERVISOR_REDZONE, PVM_SUPERVISOR_REDZONE_SIZE); --=20 2.19.1.6.gb485710b