From nobody Sun Feb 8 05:42:40 2026 Received: from mail.tecon.ru (mail.tecon.ru [82.112.190.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B17C5731A for ; Mon, 26 Feb 2024 09:29:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=82.112.190.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708939793; cv=none; b=oTXBraGrUfqucpIuS9NBVFmuolhqj50FTqLNyl3HRFhFEhPdA3yadjYhrIZj08J2vJuX0Q54A979O76WTYmoL4Cn1NZ2l+R8bgrqu9ep3hNk5vGL6ggh5+jr2q1MboR+ulki7fSeMLA2i/+LZ9j6Nhf+KZr3EA1Jg38t+xU40bY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708939793; c=relaxed/simple; bh=gYtBtcr/egSZXz7QFAh1aw4h4I+YrruWBeItmKKyOGI=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=YICLj1cb0/0C4sYh6YiWKD8yLR75xOEfdvu/Qs4aFT0yAKDqHbZ/X9S2GGcuWDQF7DXnc19cwFzMozEK3gjTMDwuF9C476tsITH4c+2h7i0PTgr60+JdabHj8isaIZ7aR54cAsqbZ5AJVnfQfBPLlYOVLDKPKtsFSIYmxTB8Wc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=tecon.ru; spf=pass smtp.mailfrom=tecon.ru; arc=none smtp.client-ip=82.112.190.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=tecon.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tecon.ru From: Dmitry Dunaev To: CC: , Dmitry Dunaev , Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , , Subject: [PATCH] mtd: spi-nor: Add Puya Semiconductor chips driver Date: Mon, 26 Feb 2024 12:23:10 +0300 Message-ID: <20240226092312.1834584-1-dunaev@tecon.ru> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a SPI NOR manufacturer driver for Puya Semiconductor chips Signed-off-by: Dmitry Dunaev --- drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/puya.c | 64 ++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 drivers/mtd/spi-nor/puya.c diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 5e68468b72fc..3e22039d0432 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -10,6 +10,7 @@ spi-nor-objs +=3D intel.o spi-nor-objs +=3D issi.o spi-nor-objs +=3D macronix.o spi-nor-objs +=3D micron-st.o +spi-nor-objs +=3D puya.o spi-nor-objs +=3D spansion.o spi-nor-objs +=3D sst.o spi-nor-objs +=3D winbond.o diff --git a/drivers/mtd/spi-nor/puya.c b/drivers/mtd/spi-nor/puya.c new file mode 100644 index 000000000000..2198a9ed7101 --- /dev/null +++ b/drivers/mtd/spi-nor/puya.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Tecon MT LLC. + */ + +#include + +#include "core.h" + +/* Puya Semiconductor (Shanghai) Co., Ltd */ +static const struct flash_info puya_nor_parts[] =3D { + { + .id =3D SNOR_ID(0x85, 0x60, 0x10), + .name =3D "p25q05h", + .size =3D SZ_64K, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x11), + .name =3D "p25q10h", + .size =3D SZ_128K, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x12), + .name =3D "p25q20h", + .size =3D SZ_256K, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x13), + .name =3D "p25q40h", + .size =3D SZ_512K, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x14), + .name =3D "p25q80h", + .size =3D SZ_1M, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x15), + .name =3D "p25q16h", + .size =3D SZ_2M, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x16), + .name =3D "p25q32h", + .size =3D SZ_4M, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x17), + .name =3D "p25q64h", + .size =3D SZ_8M, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id =3D SNOR_ID(0x85, 0x60, 0x18), + .name =3D "p25q128h", + .size =3D SZ_8M, + .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + } +}; + +const struct spi_nor_manufacturer spi_nor_puya =3D { + .name =3D "puya", + .parts =3D puya_nor_parts, + .nparts =3D ARRAY_SIZE(puya_nor_parts), +}; --=20 2.34.1