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[2001:14ba:a00e:a300:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id u19-20020a2e8553000000b002d11ef66881sm713092ljj.91.2024.02.25.18.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 18:28:00 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 26 Feb 2024 04:27:59 +0200 Subject: [PATCH v4 1/3] drm/msm/dpu: make "vblank timeout" more useful Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240226-fd-dpu-debug-timeout-v4-1-51eec83dde23@linaro.org> References: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> In-Reply-To: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Steev Klimaszewski , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1113; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=u/LLMAwCactui0InH0azxw69mOb5zZdT0MKFe0dxyYY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl2/cv3wmpf4E4iBAzHWRmMIm2xXfZ9nq0MLbMk UhPkkONCbSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZdv3LwAKCRCLPIo+Aiko 1cuxB/9yyz8H/zy2dEohWWy29s9WbXojtz4t+WYhhbEzbRHqJkpqoSL92QjfIFdLuv/iJWazADD tuZyzZgMYyO1Qqlod5lZXLlm7WoelkQGBZzk3xoFSpQWM16HypNWEmxwkgaqyGfos3Alp+L9T4t weBlSTgaKeo2WlkB48Rzmk8FRuaPyoQymxyixCFUUb1hy4RF4+XCm0U3wZ8H9d3bdobv4Vu76gG IplHCwPOr5aNPomk0hJuxBB6hxHgHPUB9cAuFxKwp+iu6zSXJXUsiLwzFU+9L2hLEffhsycs3aF r/Nz9q77g0+W4klVprofqOqI38IMGl7grLFd2vfRAJfyntSP X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A We have several reports of vblank timeout messages. However after some debugging it was found that there might be different causes to that. To allow us to identify the DPU block that gets stuck, include the actual CTL_FLUSH value into the timeout message. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 2aa72b578764..6058706f03e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -480,7 +480,7 @@ static int dpu_encoder_phys_vid_wait_for_commit_done( (hw_ctl->ops.get_flush_register(hw_ctl) =3D=3D 0), msecs_to_jiffies(50)); if (ret <=3D 0) { - DPU_ERROR("vblank timeout\n"); + DPU_ERROR("vblank timeout: %x\n", hw_ctl->ops.get_flush_register(hw_ctl)= ); return -ETIMEDOUT; } =20 --=20 2.39.2 From nobody Sat Feb 7 15:59:53 2026 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76C53179B5 for ; Mon, 26 Feb 2024 02:28:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708914486; cv=none; b=sDavs/0t2kuUfNCQerMlyVFJzmQ3wD/GvfpWPPsxiIrCbB4ROIRu+ZsG4o9qGTCdLtHbDg6MVZiZdfsdMDj2X5IgYErB3VVwKGjVHa6CtGvkLIqgEkWyUMwOMyZlAzh1wkVbmJjO/9KdWUf5VeIRTa+LnXr8y9blGndxuMr6Js8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708914486; c=relaxed/simple; bh=T/nDwtWkZJz2c5DNMYBy+x3YSHr3nDrORy9I9wO68cg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B6h1o9ruw5L6GRfH75oB8TXixNkfb1oFgqVYE0ORGAi8DYreQXSkQboB7MGwXu7Ud3nn8ygyBatOg7b2srbW00BrunKM03y9aLbYZNEP8hYgyVhDipdvzfFORoNofYhh4GPJMiA96hh5mGhIlf4Nrprdbn9mqwvTY9r/4qSPPmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=u+ORK5Q+; arc=none smtp.client-ip=209.85.208.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="u+ORK5Q+" Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-2d22b8c6e0dso25681791fa.2 for ; Sun, 25 Feb 2024 18:28:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708914482; x=1709519282; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tV02SgjOyPaysYl2sk5YoJSWDm5/B3zf/otAVWITiRM=; b=u+ORK5Q+b+eOvY9sZrnn11LUf7yauQ90E26ri4+kXP3lSmrDlOMrW5oevU0WFM3lr+ Tx+f4rPYjdnHrxSujvM8wts35rZu79n70QQnw3pUQhDRMruABkxiZbuAk09U9evme/Pr C4av3dxkIlqrjtCrz2h/Io5CDDUd61b+OqnX7F7qok55K9ODQagG71+9Q/NfgURP+nXW SQSvhiITw+akEBGdvXwSlznZrxqks9bAgl/T8JbZE3sgj2ubTs1W53ZbFe/b4ymvFcQ9 XEZ005oy5MiUUH9K4tAV4VNVupWnwk5Z+9mMpFNAxZ4DoIS5/dxi1BsCM3iZ2vPqAU5e sPBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708914482; x=1709519282; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tV02SgjOyPaysYl2sk5YoJSWDm5/B3zf/otAVWITiRM=; b=lqVcuC9xoE8aXrxM8zSkIWhrk0yY28RDIeH/qcD2pLtJ+xDZ/PELmB53Hv+blrmpjA qHf7n4rvurzVUoScuYW0R8LZiFqwe7rwA5C0lGeZJ87J5PsH2kirEdbkIlGasSSMb4Nd 9N5f1oywaBW7bZ1UPQ1H3fR0EXfqI8DNsdIfUpiSp44XDb8UOj/H7xPTbT7m1ZXpEH4r fSA/CBjpihlZKQ7Pp+pZQro5Oas7+MlO4JkU5reLD4Xal8LROQXWlas50BkvB9xSpJVt 8vBuvaCaylK0zozy9NBE4ZIQQ/3jWMvzid9baLxmxxrhI1X0gcnURznIevPHzA2gz0Fw KHdQ== X-Forwarded-Encrypted: i=1; AJvYcCWsW8c9vwOi6JGAtNq+blY395WDn110OG3XZaxqPXatPuA61ggcgmlPYujN4NW8dfC01Wdi+O9HlF8Xw3lFhFN6OQCPK5PzADXd0llU X-Gm-Message-State: AOJu0Yx94jlZ0Hc+2a7+BfH8AJrdmLl3Tb0debbi2SHLvWRtRTiGisOH LmsWcvkuqwnnFHrF4d0jQY/+Q+IVENhkqnd+wNnqQxELNjqWxaY/5u4eluDopl6Eiq94d38xlxH / X-Google-Smtp-Source: AGHT+IFOoWt/q3O+WMLjwYsFSVJyoWl3OvQCuKY1bopjNqMXAkX3KKekU+txt2kLjF1/Ozr5oKd67A== X-Received: by 2002:a2e:7d09:0:b0:2d2:40d7:9a55 with SMTP id y9-20020a2e7d09000000b002d240d79a55mr3148011ljc.4.1708914482720; Sun, 25 Feb 2024 18:28:02 -0800 (PST) Received: from umbar.lan (dzyjmhybhls-s--zn36gy-3.rev.dnainternet.fi. [2001:14ba:a00e:a300:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id u19-20020a2e8553000000b002d11ef66881sm713092ljj.91.2024.02.25.18.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 18:28:01 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 26 Feb 2024 04:28:00 +0200 Subject: [PATCH v4 2/3] drm/msm/dpu: split dpu_encoder_wait_for_event into two functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240226-fd-dpu-debug-timeout-v4-2-51eec83dde23@linaro.org> References: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> In-Reply-To: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Steev Klimaszewski , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7035; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=T/nDwtWkZJz2c5DNMYBy+x3YSHr3nDrORy9I9wO68cg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl2/cvHa9Gq7SAR1+xB/8u/bpTCuKYCMf7BYQGF HzOBt4WNsaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZdv3LwAKCRCLPIo+Aiko 1VwwB/9j8v/rw9GsVqw0b0HfZ/eATkxlPA1WzAOSnqcDMjew1j+NOw1xQHiYxBDSRp5WjOhcCL9 E7Lok1h6uqF2Ob852mParQ5Fs4+6wMe5St6yZC3525Ktww7mNlYF8lLo6oCGWu1qG7gglJLD3MW iBunufpYen3vSFNDm6tiRnnp6s8xbi30Jp+XpJrBDHviAto9H5Zyl4U+3FicG4L1YGiyFQxEggA 82wF4q1gsXWswWAHQXEDAOXeZaZ499e1j/Ve0DlkvgklguqoV1nM9SRITIwoZvaZKg3ajSVPXtN 12KNcJOXyoXosKcGD+TvB43iBKKIOmKATF+Bxh7J5R/Z+EbD X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Stop multiplexing several events via the dpu_encoder_wait_for_event() function. Split it into two distinct functions two allow separate handling of those events. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 70 +++++++++++++++++++++----= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 ++------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/msm_drv.h | 10 ----- 4 files changed, 55 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 194dbb08331d..c99c7fd770f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1282,7 +1282,7 @@ static void dpu_encoder_virt_atomic_disable(struct dr= m_encoder *drm_enc, trace_dpu_enc_disable(DRMID(drm_enc)); =20 /* wait for idle */ - dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); + dpu_encoder_wait_for_tx_complete(drm_enc); =20 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); =20 @@ -2402,10 +2402,18 @@ struct drm_encoder *dpu_encoder_init(struct drm_dev= ice *dev, return &dpu_enc->base; } =20 -int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, - enum msm_event_wait event) +/** + * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending = state + * @drm_enc: encoder pointer + * + * Wait for hardware to have flushed the current pending changes to hardwa= re at + * a vblank or CTL_START. Physical encoders will map this differently depe= nding + * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START. + * + * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise + */ +int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) { - int (*fn_wait)(struct dpu_encoder_phys *phys_enc) =3D NULL; struct dpu_encoder_virt *dpu_enc =3D NULL; int i, ret =3D 0; =20 @@ -2419,23 +2427,47 @@ int dpu_encoder_wait_for_event(struct drm_encoder *= drm_enc, for (i =3D 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys =3D dpu_enc->phys_encs[i]; =20 - switch (event) { - case MSM_ENC_COMMIT_DONE: - fn_wait =3D phys->ops.wait_for_commit_done; - break; - case MSM_ENC_TX_COMPLETE: - fn_wait =3D phys->ops.wait_for_tx_complete; - break; - default: - DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", - event); - return -EINVAL; + if (phys->ops.wait_for_commit_done) { + DPU_ATRACE_BEGIN("wait_for_commit_done"); + ret =3D phys->ops.wait_for_commit_done(phys); + DPU_ATRACE_END("wait_for_commit_done"); + if (ret) + return ret; } + } + + return ret; +} + +/** + * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixel= s to panel + * @drm_enc: encoder pointer + * + * Wait for the hardware to transfer all the pixels to the panel. Physical + * encoders will map this differently depending on the type: vid mode -> v= sync_irq, + * cmd mode -> pp_done. + * + * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise + */ +int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc =3D NULL; + int i, ret =3D 0; + + if (!drm_enc) { + DPU_ERROR("invalid encoder\n"); + return -EINVAL; + } + dpu_enc =3D to_dpu_encoder_virt(drm_enc); + DPU_DEBUG_ENC(dpu_enc, "\n"); + + for (i =3D 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys =3D dpu_enc->phys_encs[i]; =20 - if (fn_wait) { - DPU_ATRACE_BEGIN("wait_for_completion_event"); - ret =3D fn_wait(phys); - DPU_ATRACE_END("wait_for_completion_event"); + if (phys->ops.wait_for_tx_complete) { + DPU_ATRACE_BEGIN("wait_for_tx_complete"); + ret =3D phys->ops.wait_for_tx_complete(phys); + DPU_ATRACE_END("wait_for_tx_complete"); if (ret) return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.h index fe6b1d312a74..0c928d1876e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -93,25 +93,9 @@ void dpu_encoder_kickoff(struct drm_encoder *encoder); */ int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_ti= me); =20 -/** - * dpu_encoder_wait_for_event - Waits for encoder events - * @encoder: encoder pointer - * @event: event to wait for - * MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pe= nding - * frames to hardware at a vblank or ctl_start - * Encoders will map this differently depending on = the - * panel type. - * vid mode -> vsync_irq - * cmd mode -> ctl_start - * MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels= to - * the panel. Encoders will map this differently - * depending on the panel type. - * vid mode -> vsync_irq - * cmd mode -> pp_done - * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise - */ -int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder, - enum msm_event_wait event); +int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder); + +int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder); =20 /* * dpu_encoder_get_intf_mode - get interface mode of the given encoder diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index d6412395bacc..26b5e54031d9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -476,7 +476,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms= *kms, * mode panels. This may be a no-op for command mode panels. */ trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); - ret =3D dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); + ret =3D dpu_encoder_wait_for_commit_done(encoder); if (ret && ret !=3D -EWOULDBLOCK) { DPU_ERROR("wait for commit done returned %d\n", ret); break; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 762e13e2df74..91cf57f72321 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -74,16 +74,6 @@ enum msm_dsi_controller { #define MSM_GPU_MAX_RINGS 4 #define MAX_H_TILES_PER_DISPLAY 2 =20 -/** - * enum msm_event_wait - type of HW events to wait for - * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW - * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel - */ -enum msm_event_wait { - MSM_ENC_COMMIT_DONE =3D 0, - MSM_ENC_TX_COMPLETE, -}; - /** * struct msm_display_topology - defines a display topology pipeline * @num_lm: number of layer mixers used --=20 2.39.2 From nobody Sat Feb 7 15:59:53 2026 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F9361A5AC for ; Mon, 26 Feb 2024 02:28:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708914487; cv=none; b=j9NHaTeyCq5iQIDtXLkIrKKAjNvZ/9K24S1rxGH3j6Bpv9q9t0RhvSPZcKObQrMvXS9hng8r48AoHbeU8BpFNNd2Z920e2TfILy05RzB5dcapl/ix5qMNapXvYfJ0IrLnmZtOgpH+veDjYaKM2EWsyo3jJa9W1XCRgYoOvJCxMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708914487; c=relaxed/simple; bh=DcJkg8xY9yU1wn7LtAuvfIPSDQOSJ+nJ+ORj2FrKvhg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NdxR6MsPfIidDPSfV8YowTvnKJjgrJFd0e6nrI+5Gj3C6Xzuo3Y1GlxnjKjOf3e9rJxNrcrmNGylVnJoOa0e8MflHcIPoSYIoZ00siXiaLcKt+chrh+FL2s3nw0P0UzWz0ZLVXQUAnJGzfIuzbQBs8B3x4vX6T7Fc09u9WnlQb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EMhWeRLm; arc=none smtp.client-ip=209.85.208.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EMhWeRLm" Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-2d275e63590so29227601fa.2 for ; Sun, 25 Feb 2024 18:28:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708914483; x=1709519283; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2zrSUS1oI8t8ANu34PzPLXDrLfaANT7YZx3X0xgYm0k=; b=EMhWeRLm0/qjVkQ6WDTRX3ga3b/2qroeBUli8Wpl+Yipu9ObMBb9ISi3/pxmYIW1hb asb91rSPGQ2To33MZLcizTwFocbg52x2KrtnX84KLeMifn2ZHNSzCkUHQK1kUiHlS0+W OUsuPdLjUTJYSrC9VKlcf20RykR/3bYH7bVw7pc4WjjHB5yf5a72w2JAGmNzayAaDD70 CND8Qc3ZEGHBn6+GFg0UJL4psMKz1WQ5mU15wWyeXvhIW/xPNOt+yQ5ksxcTsSFnooYj KqvlRfcjUUy43AUKO/mn2YNestwWiCbhKY2TMh7uc/xFZRWuhSE+z28+qHdRTM5cVVoJ 3ZKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708914483; x=1709519283; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2zrSUS1oI8t8ANu34PzPLXDrLfaANT7YZx3X0xgYm0k=; b=oCEV1jxwKcGUw8/K3Obdck1jjh3jGhooiEgZMzaEH5q+6yD5ktXfKxtmlenJqQLw3o I5W05URf62BmC10nHGQS59g2FMD4775SP/UugSqC6vrvDXK86uFMB7aMr3P/M1xh8fVr s7k++qcicZwTOu0l9A+Eglftgqw+eJ6wXzeBTKmAJLVfhu5Q/MPGiViM7gGvuy5z4UAt 18Sd0lFzbWxcp02UWc8OB1CztbooGrzBcZPEKOZqdtqTa0dugf1hiP0qE3K65tiuN3UW BeJJY2mmvkDoufsQJ3WWaJECmhgoZ/YNKIlETiGB0RMOKSFEOrkjXSnxg0yCXSCaLuK7 jAaA== X-Forwarded-Encrypted: i=1; AJvYcCXmR71MUmAYN3WrzHFaDULX9ZO1k/NHrq83f2/E0iK2COX9Y/bQSv1EYOTh7eva0qG51V20qTsQ0O3VrxMAZO4kl0pzfCB3mwAnoqWx X-Gm-Message-State: AOJu0YwYhd7FNw/EL4mOuMld6Gig1yY337F4aVU0AkDDK6PSClmelGCC Hj0/eLE882D5rea0VwtGu5VM+GiXZzkKspSXE+RKiCEVjJgaPqtVsYmmfh6nNc0= X-Google-Smtp-Source: AGHT+IFefIdbhKnjJWT9odB7e2g6A6Qc+KZ3uR9VQXjUuUyxkrMxksYwTJufk3CxDVrfoe1de/bzVQ== X-Received: by 2002:a2e:8ec5:0:b0:2d2:3820:fb4f with SMTP id e5-20020a2e8ec5000000b002d23820fb4fmr2920818ljl.12.1708914483696; Sun, 25 Feb 2024 18:28:03 -0800 (PST) Received: from umbar.lan (dzyjmhybhls-s--zn36gy-3.rev.dnainternet.fi. [2001:14ba:a00e:a300:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id u19-20020a2e8553000000b002d11ef66881sm713092ljj.91.2024.02.25.18.28.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 18:28:02 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 26 Feb 2024 04:28:01 +0200 Subject: [PATCH v4 3/3] drm/msm/dpu: capture snapshot on the first commit_done timeout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240226-fd-dpu-debug-timeout-v4-3-51eec83dde23@linaro.org> References: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> In-Reply-To: <20240226-fd-dpu-debug-timeout-v4-0-51eec83dde23@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Steev Klimaszewski , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2187; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=DcJkg8xY9yU1wn7LtAuvfIPSDQOSJ+nJ+ORj2FrKvhg=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+rt7/oaDYu8RNoPts+ZddbZcfsC6eypMzb3mR1w/7Pvs Ilev7RRJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmskaV/X9y3YNSk7+/8w1W 3k3ge/RaK+Z1dUKrak9sw5z6AGvZsu/veVIYS0tnyPGsbQn9zFe81oF9y6/pC7fZWCwTXvHs6rM zk5jm23h+cVgTUdrp31ac26J6r51n0/sJd02dqiT+Jrbxz7yRo7nPJHO/1dar+kt+C9VtOzi7Mj qfOXd9opRLvIurnZTjktlim/Vapp2+uidq7uZb1fH3L2vwbgrq0X5YNrO1faLI3c5yw3u73vF2B HS5C/pJvS8xvFB9tuY5a8fz+D/fnXy07AOWeIrcq0vltRLXNzvNHz3BstBPz8j1r+FLh4bU+jvl SeGT7P/sl/ZdLuj6anHp6fO3QhWrhXZE+sbvmRBv6GEGAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In order to debug commit_done timeouts, capture the devcoredump state when the first timeout occurs after the encoder has been enabled. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index c99c7fd770f6..c45edcde7ebc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -126,6 +126,8 @@ enum dpu_enc_rc_states { * @base: drm_encoder base class for registration with DRM * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes * @enabled: True if the encoder is active, protected by enc_lock + * @commit_done_timedout: True if there has been a timeout on commit after + * enabling the encoder. * @num_phys_encs: Actual number of physical encoders contained. * @phys_encs: Container of physical encoders managed. * @cur_master: Pointer to the current master in this mode. Optimization @@ -172,6 +174,7 @@ struct dpu_encoder_virt { spinlock_t enc_spinlock; =20 bool enabled; + bool commit_done_timedout; =20 unsigned int num_phys_encs; struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; @@ -1226,6 +1229,8 @@ static void dpu_encoder_virt_atomic_enable(struct drm= _encoder *drm_enc, else if (disp_info->intf_type =3D=3D INTF_DSI) dpu_enc->wide_bus_en =3D msm_dsi_wide_bus_enabled(priv->dsi[index]); =20 + dpu_enc->commit_done_timedout =3D false; + mutex_lock(&dpu_enc->enc_lock); cur_mode =3D &dpu_enc->base.crtc->state->adjusted_mode; =20 @@ -2431,6 +2436,10 @@ int dpu_encoder_wait_for_commit_done(struct drm_enco= der *drm_enc) DPU_ATRACE_BEGIN("wait_for_commit_done"); ret =3D phys->ops.wait_for_commit_done(phys); DPU_ATRACE_END("wait_for_commit_done"); + if (ret =3D=3D -ETIMEDOUT && !dpu_enc->commit_done_timedout) { + dpu_enc->commit_done_timedout =3D true; + msm_disp_snapshot_state(drm_enc->dev); + } if (ret) return ret; } --=20 2.39.2