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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240226-audio-i350-v1-8-4fa1cea1667f@baylibre.com> References: <20240226-audio-i350-v1-0-4fa1cea1667f@baylibre.com> In-Reply-To: <20240226-audio-i350-v1-0-4fa1cea1667f@baylibre.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Lee Jones , Flora Fu , Jaroslav Kysela , Takashi Iwai , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Catalin Marinas , Will Deacon Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14289; i=amergnat@baylibre.com; h=from:subject:message-id; bh=WhYTUc5nyLor7cp1cySzYWqCVaRGz/+mjJw6xD9dCo0=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBl3JncI9fvx+/egkjArf7CY8inuUTtBgKzEp47N8ZO 3IPFHNCJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZdyZ3AAKCRArRkmdfjHURSV/D/ 0chIIqI6FUHeI7rRyihvR4ao/+dJLrwRvRzV1gWduyCMyDnOnG9QMAxzkX83YhMAt7d+r+HlnAR61G TpbHsY7gZjSLhmfmRqeoQzZjWtlU05XmVKei9kqXU5DHUqCssQKgF7xcKqY+Fc5RIbvpNAu2Uriu6P PtA74cu9Uec9CzGpzv/RpzqZN5tTNw1YoVCxMlH7TqL2WcLw00vHeXrjsUOdVTSKzTnMfZSoT46dVy RibkVryYVmmTHlirWYr26IXaJ4qXjQxJAOuTFgY4tQ9bYA17Fw8P9Glo+aR8Aa2eoUWAmsWy6YvLPI 5KTPJc2dNcXcVe7qNzNi2Tb0+CInKcQkvCHoo37+48fIdUrF1ZCTMBwOu+x2bFvHsIPJK9Ijv+wDXK j23azVQnMnqT5//fRCBcFvZkF3j9XwROqh0h1BvDNMTlSfqmQRzzBLQQrJyNpIs+30CSMudqAHzlS8 Ud+z0CIRayTz++KjLE0d8zZU4THFoLJ8fstDuK0ZheuTJjS/6XQUn3NRgq77t8Ws523/Mtbra70MvU Xl7QKbp+q6kRqCb/9FKWPpMS8sUAXAENgXdjhfFbNJjCDgJ3lVXsJxCvn5p4dX4F7C8Mz81Xtb1caU 7wFCOam22CxUM1+2Sts1vWXfpjOFUQBHIQwGJMhRcFHK0Q7JfR13ehzBxXqw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Add Digital Micro Device Audio Interface support for MT8365 SoC. Signed-off-by: Alexandre Mergnat --- sound/soc/mediatek/mt8365/mt8365-dai-dmic.c | 475 ++++++++++++++++++++++++= ++++ 1 file changed, 475 insertions(+) diff --git a/sound/soc/mediatek/mt8365/mt8365-dai-dmic.c b/sound/soc/mediat= ek/mt8365/mt8365-dai-dmic.c new file mode 100644 index 000000000000..1e59f456b7c9 --- /dev/null +++ b/sound/soc/mediatek/mt8365/mt8365-dai-dmic.c @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek 8365 ALSA SoC Audio DAI DMIC Control + * + * Copyright (c) 2024 MediaTek Inc. + * Authors: Jia Zeng + * Alexandre Mergnat + */ + +#include +#include +#include +#include "mt8365-afe-clk.h" +#include "mt8365-afe-common.h" + +struct mt8365_dmic_data { + bool two_wire_mode; + unsigned int clk_phase_sel_ch1; + unsigned int clk_phase_sel_ch2; + bool iir_on; + unsigned int irr_mode; + unsigned int dmic_mode; + unsigned int dmic_channel; +}; + +/* DAI Drivers */ + +static void audio_dmic_adda_enable(struct mtk_base_afe *afe) +{ + mt8365_dai_enable_adda_on(afe); + regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0, + AFE_ADDA_UL_DL_DMIC_CLKDIV_ON, AFE_ADDA_UL_DL_DMIC_CLKDIV_ON); +} + +static void audio_dmic_adda_disable(struct mtk_base_afe *afe) +{ + regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0, + AFE_ADDA_UL_DL_DMIC_CLKDIV_ON, ~AFE_ADDA_UL_DL_DMIC_CLKDIV_ON); + mt8365_dai_disable_adda_on(afe); +} + +static void mt8365_dai_enable_dmic(struct mtk_base_afe *afe, + struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_dmic_data *dmic_data =3D afe_priv->dai_priv[MT8365_AFE_IO_D= MIC]; + unsigned int val_mask; + + /* val and mask will be always same to enable */ + val_mask =3D DMIC_TOP_CON_CH1_ON | + DMIC_TOP_CON_CH2_ON | + DMIC_TOP_CON_SRC_ON; + + switch (dmic_data->dmic_channel) { + case 8: + fallthrough; + case 7: + regmap_update_bits(afe->regmap, AFE_DMIC3_UL_SRC_CON0, + val_mask, val_mask); + fallthrough; + case 6: + fallthrough; + case 5: + regmap_update_bits(afe->regmap, AFE_DMIC2_UL_SRC_CON0, + val_mask, val_mask); + fallthrough; + case 4: + fallthrough; + case 3: + regmap_update_bits(afe->regmap, AFE_DMIC1_UL_SRC_CON0, + val_mask, val_mask); + fallthrough; + case 2: + fallthrough; + case 1: + regmap_update_bits(afe->regmap, AFE_DMIC0_UL_SRC_CON0, + val_mask, val_mask); + break; + default: + break; + } +} + +static void mt8365_dai_disable_dmic(struct mtk_base_afe *afe, + struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_dmic_data *dmic_data =3D afe_priv->dai_priv[MT8365_AFE_IO_D= MIC]; + unsigned int val, mask; + + dev_info(afe->dev, "%s dmic_channel %d\n", + __func__, dmic_data->dmic_channel); + + mask =3D DMIC_TOP_CON_CH1_ON | + DMIC_TOP_CON_CH2_ON | + DMIC_TOP_CON_SRC_ON | + DMIC_TOP_CON_SDM3_LEVEL_MODE; + + /* CH1, CH1 and ARC =3D 0 */ + val =3D DMIC_TOP_CON_SDM3_DE_SELECT; + + switch (dmic_data->dmic_channel) { + case 8: + fallthrough; + case 7: + regmap_update_bits(afe->regmap, AFE_DMIC3_UL_SRC_CON0, + mask, val); + + fallthrough; + case 6: + fallthrough; + case 5: + regmap_update_bits(afe->regmap, AFE_DMIC2_UL_SRC_CON0, + mask, val); + fallthrough; + case 4: + case 3: + regmap_update_bits(afe->regmap, AFE_DMIC1_UL_SRC_CON0, + mask, val); + fallthrough; + case 2: + fallthrough; + case 1: + regmap_update_bits(afe->regmap, AFE_DMIC0_UL_SRC_CON0, + mask, val); + regmap_update_bits(afe->regmap, AFE_DMIC0_UL_SRC_CON0, + DMIC_TOP_CON_CH2_ON, 0); + regmap_update_bits(afe->regmap, AFE_DMIC0_UL_SRC_CON0, + DMIC_TOP_CON_SRC_ON, 0); + regmap_update_bits(afe->regmap, AFE_DMIC0_UL_SRC_CON0, + DMIC_TOP_CON_SDM3_LEVEL_MODE, + DMIC_TOP_CON_SDM3_DE_SELECT); + break; + default: + break; + } +} + +static const struct reg_sequence mt8365_afe_dmic_iir_coeff_reg_defaults[] = =3D { + { AFE_DMIC0_IIR_COEF_02_01, 0x00000000 }, + { AFE_DMIC0_IIR_COEF_04_03, 0x00003FB8 }, + { AFE_DMIC0_IIR_COEF_06_05, 0x3FB80000 }, + { AFE_DMIC0_IIR_COEF_08_07, 0x3FB80000 }, + { AFE_DMIC0_IIR_COEF_10_09, 0x0000C048 }, + { AFE_DMIC1_IIR_COEF_02_01, 0x00000000 }, + { AFE_DMIC1_IIR_COEF_04_03, 0x00003FB8 }, + { AFE_DMIC1_IIR_COEF_06_05, 0x3FB80000 }, + { AFE_DMIC1_IIR_COEF_08_07, 0x3FB80000 }, + { AFE_DMIC1_IIR_COEF_10_09, 0x0000C048 }, + { AFE_DMIC2_IIR_COEF_02_01, 0x00000000 }, + { AFE_DMIC2_IIR_COEF_04_03, 0x00003FB8 }, + { AFE_DMIC2_IIR_COEF_06_05, 0x3FB80000 }, + { AFE_DMIC2_IIR_COEF_08_07, 0x3FB80000 }, + { AFE_DMIC2_IIR_COEF_10_09, 0x0000C048 }, + { AFE_DMIC3_IIR_COEF_02_01, 0x00000000 }, + { AFE_DMIC3_IIR_COEF_04_03, 0x00003FB8 }, + { AFE_DMIC3_IIR_COEF_06_05, 0x3FB80000 }, + { AFE_DMIC3_IIR_COEF_08_07, 0x3FB80000 }, + { AFE_DMIC3_IIR_COEF_10_09, 0x0000C048 }, +}; + +static int mt8365_dai_load_dmic_iir_coeff_table(struct mtk_base_afe *afe) +{ + return regmap_multi_reg_write(afe->regmap, + mt8365_afe_dmic_iir_coeff_reg_defaults, + ARRAY_SIZE(mt8365_afe_dmic_iir_coeff_reg_defaults)); +} + +static int mt8365_dai_configure_dmic(struct mtk_base_afe *afe, + struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_dmic_data *dmic_data =3D afe_priv->dai_priv[MT8365_AFE_IO_D= MIC]; + bool two_wire_mode =3D dmic_data->two_wire_mode; + unsigned int clk_phase_sel_ch1 =3D dmic_data->clk_phase_sel_ch1; + unsigned int clk_phase_sel_ch2 =3D dmic_data->clk_phase_sel_ch2; + bool iir_on =3D dmic_data->iir_on; + unsigned int irr_mode =3D dmic_data->irr_mode; + unsigned int dmic_mode =3D dmic_data->dmic_mode; + unsigned int val =3D 0; + unsigned int channels =3D dai->channels; + unsigned int rate =3D dai->rate; + + dmic_data->dmic_channel =3D channels; + + dev_info(afe->dev, "%s dmic_channel %d dmic_rate %d dmic_mode %d\n", + __func__, dmic_data->dmic_channel, rate, dmic_mode); + + val |=3D DMIC_TOP_CON_SDM3_LEVEL_MODE; + + if (dmic_mode > DMIC_MODE_1P625M) + val |=3D DMIC_TOP_CON_LOW_POWER_MODE(dmic_mode); + else { + val |=3D DMIC_TOP_CON_LOW_POWER_MODE(0) | + FIELD_PREP(DMIC_TOP_CON_INPUT_MODE, dmic_mode); + } + + if (two_wire_mode) { + val |=3D DMIC_TOP_CON_TWO_WIRE_MODE; + } else { + val |=3D FIELD_PREP(DMIC_TOP_CON_CK_PHASE_SEL_CH1, clk_phase_sel_ch1); + val |=3D FIELD_PREP(DMIC_TOP_CON_CK_PHASE_SEL_CH2, clk_phase_sel_ch2); + } + + switch (rate) { + case 48000: + val |=3D DMIC_TOP_CON_VOICE_MODE_48K; + break; + case 32000: + val |=3D DMIC_TOP_CON_VOICE_MODE_32K; + break; + case 16000: + val |=3D DMIC_TOP_CON_VOICE_MODE_16K; + break; + case 8000: + val |=3D DMIC_TOP_CON_VOICE_MODE_8K; + break; + default: + return -EINVAL; + } + + if (iir_on) { + if (irr_mode =3D=3D IIR_MODE0) + mt8365_dai_load_dmic_iir_coeff_table(afe); /* SW mode */ + val |=3D FIELD_PREP(DMIC_TOP_CON_IIR_MODE, irr_mode); + val |=3D DMIC_TOP_CON_IIR_ON; + } + + switch (dmic_data->dmic_channel) { + case 8: + fallthrough; + case 7: + regmap_update_bits(afe->regmap, AFE_DMIC3_UL_SRC_CON0, + DMIC_TOP_CON_CONFIG_MASK, val); + fallthrough; + case 6: + fallthrough; + case 5: + regmap_update_bits(afe->regmap, AFE_DMIC2_UL_SRC_CON0, + DMIC_TOP_CON_CONFIG_MASK, val); + fallthrough; + case 4: + fallthrough; + case 3: + regmap_update_bits(afe->regmap, AFE_DMIC1_UL_SRC_CON0, + DMIC_TOP_CON_CONFIG_MASK, val); + fallthrough; + case 2: + fallthrough; + case 1: + regmap_update_bits(afe->regmap, AFE_DMIC0_UL_SRC_CON0, + DMIC_TOP_CON_CONFIG_MASK, val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mt8365_dai_dmic_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe =3D snd_soc_dai_get_drvdata(dai); + + mt8365_afe_enable_main_clk(afe); + + mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC0_ADC); + mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC1_ADC); + mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC2_ADC); + mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC3_ADC); + + audio_dmic_adda_enable(afe); + + return 0; +} + +static void mt8365_dai_dmic_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe =3D snd_soc_dai_get_drvdata(dai); + + mt8365_dai_disable_dmic(afe, substream, dai); + audio_dmic_adda_disable(afe); + /* HW Request delay 125ms before CG off */ + udelay(125); + mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC3_ADC); + mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC2_ADC); + mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC1_ADC); + mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC0_ADC); + + mt8365_afe_disable_main_clk(afe); +} + +static int mt8365_dai_dmic_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe =3D snd_soc_dai_get_drvdata(dai); + + mt8365_dai_configure_dmic(afe, substream, dai); + mt8365_dai_enable_dmic(afe, substream, dai); + + return 0; +} + +static const struct snd_soc_dai_ops mt8365_afe_dmic_ops =3D { + .startup =3D mt8365_dai_dmic_startup, + .shutdown =3D mt8365_dai_dmic_shutdown, + .prepare =3D mt8365_dai_dmic_prepare, +}; + +static struct snd_soc_dai_driver mtk_dai_dmic_driver[] =3D { + { + .name =3D "DMIC", + .id =3D MT8365_AFE_IO_DMIC, + .capture =3D { + .stream_name =3D "DMIC Capture", + .channels_min =3D 1, + .channels_max =3D 8, + .rates =3D SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_32000 | + SNDRV_PCM_RATE_48000, + .formats =3D SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .ops =3D &mt8365_afe_dmic_ops, + } +}; + +/* DAI Controls */ + +static int mt8365_afe_dmic_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *cmpnt =3D snd_soc_kcontrol_component(kcontrol); + struct mtk_base_afe *afe =3D snd_soc_component_get_drvdata(cmpnt); + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_dmic_data *dmic_data =3D afe_priv->dai_priv[MT8365_AFE_IO_D= MIC]; + + ucontrol->value.integer.value[0] =3D dmic_data->dmic_mode; + + return 0; +} + +static int mt8365_afe_dmic_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *cmpnt =3D snd_soc_kcontrol_component(kcontrol); + struct mtk_base_afe *afe =3D snd_soc_component_get_drvdata(cmpnt); + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_dmic_data *dmic_data =3D afe_priv->dai_priv[MT8365_AFE_IO_D= MIC]; + + unsigned int val =3D ucontrol->value.integer.value[0]; + + if (dmic_data->dmic_mode =3D=3D val) + return 0; + + dmic_data->dmic_mode =3D ucontrol->value.integer.value[0]; + + return 0; +} + +static const char *const dmic_mode_func[] =3D { + ENUM_TO_STR(DMIC_MODE_3P25M), + ENUM_TO_STR(DMIC_MODE_1P625M), + ENUM_TO_STR(DMIC_MODE_812P5K), + ENUM_TO_STR(DMIC_MODE_406P25K), +}; + +static const struct soc_enum mt8365_afe_soc_enum =3D + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dmic_mode_func), dmic_mode_func); + +static const struct snd_kcontrol_new mtk_dai_dmic_controls[] =3D { + SOC_ENUM_EXT("DMIC_Mode_Select", + mt8365_afe_soc_enum, + mt8365_afe_dmic_mode_get, + mt8365_afe_dmic_mode_put), +}; + +/* DAI widget */ + +static const struct snd_soc_dapm_widget mtk_dai_dmic_widgets[] =3D { + SND_SOC_DAPM_INPUT("DMIC In"), +}; + +/* DAI route */ + +static const struct snd_soc_dapm_route mtk_dai_dmic_routes[] =3D { + {"I14", NULL, "DMIC Capture"}, + {"I15", NULL, "DMIC Capture"}, + {"I16", NULL, "DMIC Capture"}, + {"I17", NULL, "DMIC Capture"}, + {"I18", NULL, "DMIC Capture"}, + {"I19", NULL, "DMIC Capture"}, + {"I20", NULL, "DMIC Capture"}, + {"I21", NULL, "DMIC Capture"}, + {"DMIC Capture", NULL, "DMIC In"}, +}; + + +static int init_dmic_priv_data(struct mtk_base_afe *afe) +{ + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_dmic_data *dmic_priv; + struct device_node *np =3D afe->dev->of_node; + unsigned int temps[4]; + int ret; + + dmic_priv =3D devm_kzalloc(afe->dev, sizeof(struct mt8365_dmic_data), + GFP_KERNEL); + if (!dmic_priv) + return -ENOMEM; + + ret =3D of_property_read_u32_array(np, "mediatek,dmic-mode", + &temps[0], + 1); + if (ret =3D=3D 0) + dmic_priv->dmic_mode =3D temps[0]; + + dmic_priv->two_wire_mode =3D of_property_read_bool(np, + "mediatek,dmic-two-wire-mode"); + + ret =3D of_property_read_u32_array(np, "mediatek,dmic-clk-phases", + &temps[0], + 2); + if (ret =3D=3D 0) { + dmic_priv->clk_phase_sel_ch1 =3D temps[0]; + dmic_priv->clk_phase_sel_ch2 =3D temps[1]; + } else if (!dmic_priv->two_wire_mode) { + dmic_priv->clk_phase_sel_ch1 =3D 0; + dmic_priv->clk_phase_sel_ch2 =3D 4; + } + + dmic_priv->iir_on =3D of_property_read_bool(np, + "mediatek,dmic-iir-on"); + + if (dmic_priv->iir_on) { + ret =3D of_property_read_u32_array(np, "mediatek,dmic-irr-mode", + &temps[0], + 1); + if (ret =3D=3D 0) + dmic_priv->irr_mode =3D temps[0]; + } + + afe_priv->dai_priv[MT8365_AFE_IO_DMIC] =3D dmic_priv; + return 0; +} + +int mt8365_dai_dmic_register(struct mtk_base_afe *afe) +{ + struct mtk_base_afe_dai *dai; + + dev_dbg(afe->dev, "%s()\n", __func__); + + dai =3D devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); + + dai->dai_drivers =3D mtk_dai_dmic_driver; + dai->num_dai_drivers =3D ARRAY_SIZE(mtk_dai_dmic_driver); + dai->controls =3D mtk_dai_dmic_controls; + dai->num_controls =3D ARRAY_SIZE(mtk_dai_dmic_controls); + dai->dapm_widgets =3D mtk_dai_dmic_widgets; + dai->num_dapm_widgets =3D ARRAY_SIZE(mtk_dai_dmic_widgets); + dai->dapm_routes =3D mtk_dai_dmic_routes; + dai->num_dapm_routes =3D ARRAY_SIZE(mtk_dai_dmic_routes); + + return init_dmic_priv_data(afe); +} --=20 2.25.1