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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240226-audio-i350-v1-7-4fa1cea1667f@baylibre.com> References: <20240226-audio-i350-v1-0-4fa1cea1667f@baylibre.com> In-Reply-To: <20240226-audio-i350-v1-0-4fa1cea1667f@baylibre.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Lee Jones , Flora Fu , Jaroslav Kysela , Takashi Iwai , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Catalin Marinas , Will Deacon Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10467; i=amergnat@baylibre.com; h=from:subject:message-id; bh=NV3JBMyLyLRM7d7PcxPRxCiSiQIWtQdVIaekkHxK2hY=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBl3JncV38WxFFu/20pcu97irstVIJVDajaJ6Eggs4i XOdi3OaJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZdyZ3AAKCRArRkmdfjHURYLuD/ 49SHgxcbWIDeTcAqWf9SY6DcUAj+f2qzB/K1foe3gRdco1XMSaKUdBYjrc7LlcbJI6TVS02t3rZdzm QvOZUR7Ghkk19khwfCioTFPGtRfYlZOnFghmoSyJgWi90L9Po2HsOZu8ku1u5bFJuz6L1oL7Lq2Kum g+bx4XCoXp4nmYxUNhyWiCN4My6kG79WXTLAyOM9CMpfd+krAHCzQhhlEFFdcH8UZcPxF34MD8erbP RgBCcW4O1rzGs0efrBffBSFqViiP/sykqiUe2KM8ZWI5DqGf9rcG1fhopLo+0Byp8EWNcxh2zEH/xK 2ktwj7x4Z5PVfderKt+brLkBCY8oR22NG8lXwrOHE0WgRGxjk+M3YPJ4HiRpW8dPN4Uj1swKWyAgg7 OYuWT13L7nlGtIhguvPJwH7YJMSWywyraCsWkkBqjVULBUe2lUFA6jWQ/Hj7lc5ix1ZoA4GgtBVJWu ftu7O6amAb5+MLguIr6A1Zs1lNZncU0O17IiQMuek3NiV6clBjB5YyB/6o3owy4z8aC/+pbLb8Ebg9 O5A6suVtXyj8cVHPydscSjzxNMzjf8BPDzgNAlh8h3jSrCg/iokyWcewfdf7QM327lsq25rTbbPMS4 jpu6xKSrKOnz+m33CxFeuW/BKw9Jaw2c/8qEerpbHOOggZtiNJV5krdy20ww== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Add ADDA Device Audio Interface support for MT8365 SoC. Signed-off-by: Alexandre Mergnat --- sound/soc/mediatek/mt8365/mt8365-dai-adda.c | 355 ++++++++++++++++++++++++= ++++ 1 file changed, 355 insertions(+) diff --git a/sound/soc/mediatek/mt8365/mt8365-dai-adda.c b/sound/soc/mediat= ek/mt8365/mt8365-dai-adda.c new file mode 100644 index 000000000000..798b749c0cc5 --- /dev/null +++ b/sound/soc/mediatek/mt8365/mt8365-dai-adda.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Mediatek 8365 ALSA SoC Audio DAI ADDA Control + * + * Copyright (c) 2024 MediaTek Inc. + * Authors: Jia Zeng + * Alexandre Mergnat + */ + +#include +#include +#include +#include "mt8365-afe-clk.h" +#include "mt8365-afe-common.h" + +static int adda_afe_on_ref_cnt; + +/* DAI Drivers */ + +static int mt8365_dai_set_adda_out(struct mtk_base_afe *afe, unsigned int = rate) +{ + unsigned int val =3D 0; + + switch (rate) { + case 8000: + val |=3D (0 << 28) | AFE_ADDA_DL_VOICE_DATA; + break; + case 11025: + val |=3D 1 << 28; + break; + case 12000: + val |=3D 2 << 28; + break; + case 16000: + val |=3D (3 << 28) | AFE_ADDA_DL_VOICE_DATA; + break; + case 22050: + val |=3D 4 << 28; + break; + case 24000: + val |=3D 5 << 28; + break; + case 32000: + val |=3D 6 << 28; + break; + case 44100: + val |=3D 7 << 28; + break; + case 48000: + val |=3D 8 << 28; + break; + default: + return -EINVAL; + } + + val |=3D AFE_ADDA_DL_8X_UPSAMPLE | + AFE_ADDA_DL_MUTE_OFF_CH1 | + AFE_ADDA_DL_MUTE_OFF_CH2 | + AFE_ADDA_DL_DEGRADE_GAIN; + + regmap_update_bits(afe->regmap, AFE_ADDA_PREDIS_CON0, 0xffffffff, 0); + regmap_update_bits(afe->regmap, AFE_ADDA_PREDIS_CON1, 0xffffffff, 0); + regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, 0xffffffff, val); + /* SA suggest apply -0.3db to audio/speech path */ + regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON1, + 0xffffffff, 0xf74f0000); + /* SA suggest use default value for sdm */ + regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, + 0xffffffff, 0x0700701e); + + return 0; +} + +static int mt8365_dai_set_adda_in(struct mtk_base_afe *afe, unsigned int r= ate) +{ + unsigned int val =3D 0; + + switch (rate) { + case 8000: + val |=3D (0 << 17); + break; + case 16000: + val |=3D (1 << 17); + break; + case 32000: + val |=3D (2 << 17); + break; + case 48000: + val |=3D (3 << 17); + break; + default: + return -EINVAL; + } + + regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 0x000e0000, val); + /* Using Internal ADC */ + regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x0); + + return 0; +} + +int mt8365_dai_enable_adda_on(struct mtk_base_afe *afe) +{ + unsigned long flags; + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + + spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); + + adda_afe_on_ref_cnt++; + if (adda_afe_on_ref_cnt =3D=3D 1) + regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0, + AFE_ADDA_UL_DL_ADDA_AFE_ON, AFE_ADDA_UL_DL_ADDA_AFE_ON); + + spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); + + return 0; +} + +int mt8365_dai_disable_adda_on(struct mtk_base_afe *afe) +{ + unsigned long flags; + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + + spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); + + adda_afe_on_ref_cnt--; + if (adda_afe_on_ref_cnt =3D=3D 0) + regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0, + AFE_ADDA_UL_DL_ADDA_AFE_ON, ~AFE_ADDA_UL_DL_ADDA_AFE_ON); + else if (adda_afe_on_ref_cnt < 0) + adda_afe_on_ref_cnt =3D 0; + + spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); + + return 0; +} + +static void mt8365_dai_set_adda_out_enable(struct mtk_base_afe *afe, + bool enable) +{ + regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, 0x1, enable); + + if (enable) + mt8365_dai_enable_adda_on(afe); + else + mt8365_dai_disable_adda_on(afe); +} + +static void mt8365_dai_set_adda_in_enable(struct mtk_base_afe *afe, + bool enable) +{ + if (enable) { + regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 0x1, 0x1); + mt8365_dai_enable_adda_on(afe); + /* enable aud_pad_top fifo */ + regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, + 0xffffffff, 0x31); + } else { + /* disable aud_pad_top fifo */ + regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, + 0xffffffff, 0x30); + regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 0x1, 0x0); + /* de suggest disable ADDA_UL_SRC at least wait 125us */ + udelay(150); + mt8365_dai_disable_adda_on(afe); + } +} + +static int mt8365_dai_int_adda_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe =3D snd_soc_dai_get_drvdata(dai); + unsigned int stream =3D substream->stream; + + mt8365_afe_enable_main_clk(afe); + + if (stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DAC); + mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DAC_PREDIS); + } else if (stream =3D=3D SNDRV_PCM_STREAM_CAPTURE) { + mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_ADC); + } + + return 0; +} + +static void mt8365_dai_int_adda_shutdown(struct snd_pcm_substream *substre= am, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe =3D snd_soc_dai_get_drvdata(dai); + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_be_dai_data *be =3D + &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE]; + unsigned int stream =3D substream->stream; + + if (be->prepared[stream]) { + if (stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + mt8365_dai_set_adda_out_enable(afe, false); + mt8365_afe_set_i2s_out_enable(afe, false); + } else + mt8365_dai_set_adda_in_enable(afe, false); + + be->prepared[stream] =3D false; + } + + if (stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DAC_PREDIS); + mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DAC); + } else if (stream =3D=3D SNDRV_PCM_STREAM_CAPTURE) { + mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_ADC); + } + + mt8365_afe_disable_main_clk(afe); +} + +static int mt8365_dai_int_adda_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe =3D snd_soc_dai_get_drvdata(dai); + struct mt8365_afe_private *afe_priv =3D afe->platform_priv; + struct mt8365_be_dai_data *be =3D + &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE]; + const unsigned int rate =3D substream->runtime->rate; + const unsigned int stream =3D substream->stream; + const int bit_width =3D snd_pcm_format_width(substream->runtime->format); + int ret; + + dev_info(afe->dev, "%s '%s' rate =3D %u\n", __func__, + snd_pcm_stream_str(substream), rate); + + if (be->prepared[stream]) { + dev_info(afe->dev, "%s '%s' prepared already\n", + __func__, snd_pcm_stream_str(substream)); + return 0; + } + + if (stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + ret =3D mt8365_dai_set_adda_out(afe, rate); + if (ret) + return ret; + + ret =3D mt8365_afe_set_i2s_out(afe, rate, bit_width); + if (ret) + return ret; + + mt8365_dai_set_adda_out_enable(afe, true); + mt8365_afe_set_i2s_out_enable(afe, true); + } else { + ret =3D mt8365_dai_set_adda_in(afe, rate); + if (ret) + return ret; + + mt8365_dai_set_adda_in_enable(afe, true); + } + + be->prepared[stream] =3D true; + + return 0; +} + +static const struct snd_soc_dai_ops mt8365_afe_int_adda_ops =3D { + .startup =3D mt8365_dai_int_adda_startup, + .shutdown =3D mt8365_dai_int_adda_shutdown, + .prepare =3D mt8365_dai_int_adda_prepare, +}; + +static struct snd_soc_dai_driver mtk_dai_adda_driver[] =3D { + { + .name =3D "INT ADDA", + .id =3D MT8365_AFE_IO_INT_ADDA, + .playback =3D { + .stream_name =3D "INT ADDA Playback", + .channels_min =3D 1, + .channels_max =3D 2, + .rates =3D SNDRV_PCM_RATE_8000_48000, + .formats =3D SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture =3D { + .stream_name =3D "INT ADDA Capture", + .channels_min =3D 1, + .channels_max =3D 2, + .rates =3D SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_32000 | + SNDRV_PCM_RATE_48000, + .formats =3D SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + }, + .ops =3D &mt8365_afe_int_adda_ops, + } +}; + +/* DAI Controls */ + +static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] =3D { + SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3, + 10, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] =3D { + SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4, + 11, 1, 0), +}; + +static const struct snd_kcontrol_new int_adda_o03_o04_enable_ctl =3D + SOC_DAPM_SINGLE_VIRT("Switch", 1); + +/* DAI widget */ + +static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] =3D { + SND_SOC_DAPM_SWITCH("INT ADDA O03_O04", SND_SOC_NOPM, 0, 0, + &int_adda_o03_o04_enable_ctl), + /* inter-connections */ + SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0, + mtk_adda_dl_ch1_mix, + ARRAY_SIZE(mtk_adda_dl_ch1_mix)), + SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0, + mtk_adda_dl_ch2_mix, + ARRAY_SIZE(mtk_adda_dl_ch2_mix)), +}; + +/* DAI route */ + +static const struct snd_soc_dapm_route mtk_dai_adda_routes[] =3D { + {"INT ADDA O03_O04", "Switch", "O03"}, + {"INT ADDA O03_O04", "Switch", "O04"}, + {"INT ADDA Playback", NULL, "INT ADDA O03_O04"}, + {"INT ADDA Playback", NULL, "ADDA_DL_CH1"}, + {"INT ADDA Playback", NULL, "ADDA_DL_CH2"}, + {"AIN Mux", "INT ADC", "INT ADDA Capture"}, + {"ADDA_DL_CH1", "GAIN1_OUT_CH1", "Hostless FM DL"}, + {"ADDA_DL_CH2", "GAIN1_OUT_CH2", "Hostless FM DL"}, +}; + +int mt8365_dai_adda_register(struct mtk_base_afe *afe) +{ + struct mtk_base_afe_dai *dai; + + dev_dbg(afe->dev, "%s()\n", __func__); + + dai =3D devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); + + dai->dai_drivers =3D mtk_dai_adda_driver; + dai->num_dai_drivers =3D ARRAY_SIZE(mtk_dai_adda_driver); + dai->dapm_widgets =3D mtk_dai_adda_widgets; + dai->num_dapm_widgets =3D ARRAY_SIZE(mtk_dai_adda_widgets); + dai->dapm_routes =3D mtk_dai_adda_routes; + dai->num_dapm_routes =3D ARRAY_SIZE(mtk_dai_adda_routes); + + return 0; +} --=20 2.25.1