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Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hix5hd2.c | 85 ++++++++++++++++++----------- 1 file changed, 52 insertions(+), 33 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/cl= k-hix5hd2.c index 64bdd3f05725..0a3f1320d0d5 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -4,13 +4,17 @@ * Copyright (c) 2014 Hisilicon Limited. */ =20 -#include #include + #include #include +#include +#include +#include + #include "clk.h" =20 -static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = =3D { +static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] =3D { { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, }, { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, }, @@ -43,19 +47,19 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_= clks[] __initdata =3D { { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, }, }; =20 -static const char *const sfc_mux_p[] __initconst =3D { +static const char *const sfc_mux_p[] =3D { "24m", "150m", "200m", "100m", "75m", }; static u32 sfc_mux_table[] =3D {0, 4, 5, 6, 7}; =20 -static const char *const sdio_mux_p[] __initconst =3D { +static const char *const sdio_mux_p[] =3D { "75m", "100m", "50m", "15m", }; static u32 sdio_mux_table[] =3D {0, 1, 2, 3}; =20 -static const char *const fephy_mux_p[] __initconst =3D { "25m", "125m"}; +static const char *const fephy_mux_p[] =3D { "25m", "125m"}; static u32 fephy_mux_table[] =3D {0, 1}; =20 =20 -static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata =3D { +static struct hisi_mux_clock hix5hd2_mux_clks[] =3D { { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p), CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, }, { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), @@ -67,7 +71,7 @@ static struct hisi_mux_clock hix5hd2_mux_clks[] __initdat= a =3D { CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, }, }; =20 -static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata =3D { +static struct hisi_gate_clock hix5hd2_gate_clks[] =3D { /* sfc */ { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux", CLK_SET_RATE_PARENT, 0x5c, 0, 0, }, @@ -153,7 +157,7 @@ struct hix5hd2_clk_complex { u32 phy_rst_mask; }; =20 -static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata =3D { +static struct hix5hd2_complex_clock hix5hd2_complex_clks[] =3D { {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK, 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER}, {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK, @@ -249,21 +253,22 @@ static const struct clk_ops clk_complex_ops =3D { .disable =3D clk_complex_disable, }; =20 -static void __init -hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, +static int +hix5hd2_clk_register_complex(struct device *dev, const void *clocks, size_= t num, struct hisi_clock_data *data) { + const struct hix5hd2_complex_clock *clks =3D clocks; void __iomem *base =3D data->base; int i; =20 - for (i =3D 0; i < nums; i++) { + for (i =3D 0; i < num; i++) { struct hix5hd2_clk_complex *p_clk; struct clk *clk; struct clk_init_data init; =20 p_clk =3D kzalloc(sizeof(*p_clk), GFP_KERNEL); if (!p_clk) - return; + return -ENOMEM; =20 init.name =3D clks[i].name; if (clks[i].type =3D=3D TYPE_ETHER) @@ -289,31 +294,45 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_c= lock *clks, int nums, kfree(p_clk); pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(p_clk); } =20 data->clk_data.clks[clks[i].id] =3D clk; } -} =20 -static void __init hix5hd2_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HIX5HD2_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks, - ARRAY_SIZE(hix5hd2_fixed_rate_clks), - clk_data); - hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), - clk_data); - hisi_clk_register_gate(hix5hd2_gate_clks, - ARRAY_SIZE(hix5hd2_gate_clks), clk_data); - hix5hd2_clk_register_complex(hix5hd2_complex_clks, - ARRAY_SIZE(hix5hd2_complex_clks), - clk_data); + return 0; } =20 -CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init); +static const struct hisi_clocks hix5hd2_clks =3D { + .nr =3D HIX5HD2_NR_CLKS, + .fixed_rate_clks =3D hix5hd2_fixed_rate_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hix5hd2_fixed_rate_clks), + .mux_clks =3D hix5hd2_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hix5hd2_mux_clks), + .gate_clks =3D hix5hd2_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hix5hd2_gate_clks), + .customized_clks =3D hix5hd2_complex_clks, + .customized_clks_num =3D ARRAY_SIZE(hix5hd2_complex_clks), + .clk_register_customized =3D hix5hd2_clk_register_complex, +}; + +static const struct of_device_id hix5hd2_clk_match_table[] =3D { + { .compatible =3D "hisilicon,hix5hd2-clock", + .data =3D &hix5hd2_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hix5hd2_clk_match_table); + +static struct platform_driver hix5hd2_clk_driver =3D { + .probe =3D hisi_clk_probe, + .remove_new =3D hisi_clk_remove, + .driver =3D { + .name =3D "hix5hd2-clock", + .of_match_table =3D hix5hd2_clk_match_table, + }, +}; + +module_platform_driver(hix5hd2_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hix5hd2 Clock Driver"); --=20 2.43.0