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That simplifies the signature of exynos_register_cpu_clock() and makes it easier to add more fields to struct samsung_cpu_clock later. This style follows the example of samsung_clk_register_pll(). No functional change. Signed-off-by: Sam Protsenko --- Changes in v3: - none Changes in v2: - none drivers/clk/samsung/clk-cpu.c | 46 +++++++++++++++++------------------ 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 6412fd2580e0..7b6fd331a7ec 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -432,16 +432,19 @@ static int exynos5433_cpuclk_notifier_cb(struct notif= ier_block *nb, =20 /* helper function to register a CPU clock */ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *c= tx, - unsigned int lookup_id, const char *name, - const struct clk_hw *parent, const struct clk_hw *alt_parent, - unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg, - unsigned long num_cfgs, unsigned long flags) + const struct samsung_cpu_clock *clk_data) { + const struct clk_hw *parent, *alt_parent; + struct clk_hw **hws; struct exynos_cpuclk *cpuclk; struct clk_init_data init; const char *parent_name; + unsigned int num_cfgs; int ret =3D 0; =20 + hws =3D ctx->clk_data.hws; + parent =3D hws[clk_data->parent_id]; + alt_parent =3D hws[clk_data->alt_parent_id]; if (IS_ERR(parent) || IS_ERR(alt_parent)) { pr_err("%s: invalid parent clock(s)\n", __func__); return -EINVAL; @@ -453,7 +456,7 @@ static int __init exynos_register_cpu_clock(struct sams= ung_clk_provider *ctx, =20 parent_name =3D clk_hw_get_name(parent); =20 - init.name =3D name; + init.name =3D clk_data->name; init.flags =3D CLK_SET_RATE_PARENT; init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -461,10 +464,10 @@ static int __init exynos_register_cpu_clock(struct sa= msung_clk_provider *ctx, =20 cpuclk->alt_parent =3D alt_parent; cpuclk->hw.init =3D &init; - cpuclk->ctrl_base =3D ctx->reg_base + offset; + cpuclk->ctrl_base =3D ctx->reg_base + clk_data->offset; cpuclk->lock =3D &ctx->lock; - cpuclk->flags =3D flags; - if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) + cpuclk->flags =3D clk_data->flags; + if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) cpuclk->clk_nb.notifier_call =3D exynos5433_cpuclk_notifier_cb; else cpuclk->clk_nb.notifier_call =3D exynos_cpuclk_notifier_cb; @@ -472,11 +475,16 @@ static int __init exynos_register_cpu_clock(struct sa= msung_clk_provider *ctx, ret =3D clk_notifier_register(parent->clk, &cpuclk->clk_nb); if (ret) { pr_err("%s: failed to register clock notifier for %s\n", - __func__, name); + __func__, clk_data->name); goto free_cpuclk; } =20 - cpuclk->cfg =3D kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL); + /* Find count of configuration rates in cfg */ + for (num_cfgs =3D 0; clk_data->cfg[num_cfgs].prate !=3D 0; ) + num_cfgs++; + + cpuclk->cfg =3D kmemdup(clk_data->cfg, sizeof(*clk_data->cfg) * num_cfgs, + GFP_KERNEL); if (!cpuclk->cfg) { ret =3D -ENOMEM; goto unregister_clk_nb; @@ -484,11 +492,12 @@ static int __init exynos_register_cpu_clock(struct sa= msung_clk_provider *ctx, =20 ret =3D clk_hw_register(NULL, &cpuclk->hw); if (ret) { - pr_err("%s: could not register cpuclk %s\n", __func__, name); + pr_err("%s: could not register cpuclk %s\n", __func__, + clk_data->name); goto free_cpuclk_data; } =20 - samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id); + samsung_clk_add_lookup(ctx, &cpuclk->hw, clk_data->id); return 0; =20 free_cpuclk_data: @@ -504,16 +513,7 @@ void __init samsung_clk_register_cpu(struct samsung_cl= k_provider *ctx, const struct samsung_cpu_clock *list, unsigned int nr_clk) { unsigned int idx; - unsigned int num_cfgs; - struct clk_hw **hws =3D ctx->clk_data.hws; =20 - for (idx =3D 0; idx < nr_clk; idx++, list++) { - /* find count of configuration rates in cfg */ - for (num_cfgs =3D 0; list->cfg[num_cfgs].prate !=3D 0; ) - num_cfgs++; - - exynos_register_cpu_clock(ctx, list->id, list->name, - hws[list->parent_id], hws[list->alt_parent_id], - list->offset, list->cfg, num_cfgs, list->flags); - } + for (idx =3D 0; idx < nr_clk; idx++) + exynos_register_cpu_clock(ctx, &list[idx]); } --=20 2.39.2