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However there is no justification for this: * If the codec needs MCLK for its operation, mclk-fs is expected to be set according to the codec requirements. * If the codec does not need MCLK the minimum is 2 * SCLK, because this is minimum the divider between SCLK and MCLK can do. Multiplying by 4 may cause problems because the PLL limit may be reached sooner than it should, so use 2x instead. Fixes: d60e4f1e4be5 ("ASoC: meson: add tdm interface driver") Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-tdm-interface.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-= interface.c index 1c3d433cefd2..cd5168e826df 100644 --- a/sound/soc/meson/axg-tdm-interface.c +++ b/sound/soc/meson/axg-tdm-interface.c @@ -264,8 +264,8 @@ static int axg_tdm_iface_set_sclk(struct snd_soc_dai *d= ai, srate =3D iface->slots * iface->slot_width * params_rate(params); =20 if (!iface->mclk_rate) { - /* If no specific mclk is requested, default to bit clock * 4 */ - clk_set_rate(iface->mclk, 4 * srate); + /* If no specific mclk is requested, default to bit clock * 2 */ + clk_set_rate(iface->mclk, 2 * srate); } else { /* Check if we can actually get the bit clock from mclk */ if (iface->mclk_rate % srate) { --=20 2.43.0 From nobody Sun Feb 8 06:04:52 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12BA413BAC2 for ; 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charset="utf-8" According to Amlogic datasheets for the SoCs supported by this driver, the maximum bit clock rate is 100MHz. The tdm interface allows the rates listed by the DAI driver, regardless of the number slots or their width. However, these will impact the bit clock rate. Hitting the 100MHz limit is very unlikely for most use cases but it is possible. For example with 32 slots / 32 bits wide, the maximum rate is no longer 384kHz but ~96kHz. Add the constraint accordingly if the component is not already active. If it is active, the rate is already constrained by the first stream rate. Fixes: d60e4f1e4be5 ("ASoC: meson: add tdm interface driver") Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-tdm-interface.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-= interface.c index cd5168e826df..2cedbce73837 100644 --- a/sound/soc/meson/axg-tdm-interface.c +++ b/sound/soc/meson/axg-tdm-interface.c @@ -12,6 +12,9 @@ =20 #include "axg-tdm.h" =20 +/* Maximum bit clock frequency according the datasheets */ +#define MAX_SCLK 100000000 /* Hz */ + enum { TDM_IFACE_PAD, TDM_IFACE_LOOPBACK, @@ -153,19 +156,27 @@ static int axg_tdm_iface_startup(struct snd_pcm_subst= ream *substream, return -EINVAL; } =20 - /* Apply component wide rate symmetry */ if (snd_soc_component_active(dai->component)) { + /* Apply component wide rate symmetry */ ret =3D snd_pcm_hw_constraint_single(substream->runtime, SNDRV_PCM_HW_PARAM_RATE, iface->rate); - if (ret < 0) { - dev_err(dai->dev, - "can't set iface rate constraint\n"); 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Fri, 23 Feb 2024 09:51:23 -0800 (PST) From: Jerome Brunet To: Mark Brown , Liam Girdwood Cc: Jerome Brunet , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH 3/6] ASoC: meson: axg-tdm-interface: update error format error traces Date: Fri, 23 Feb 2024 18:51:09 +0100 Message-ID: <20240223175116.2005407-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223175116.2005407-1-jbrunet@baylibre.com> References: <20240223175116.2005407-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ASoC stopped using CBS_CFS and CBM_CFM a few years ago but the traces in the amlogic tdm interface driver did not follow. Update this to match the new format names Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-tdm-interface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-= interface.c index 2cedbce73837..bf708717635b 100644 --- a/sound/soc/meson/axg-tdm-interface.c +++ b/sound/soc/meson/axg-tdm-interface.c @@ -133,7 +133,7 @@ static int axg_tdm_iface_set_fmt(struct snd_soc_dai *da= i, unsigned int fmt) =20 case SND_SOC_DAIFMT_BP_FC: case SND_SOC_DAIFMT_BC_FP: - dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n"); + dev_err(dai->dev, "only BP_FP and BC_FC are supported\n"); fallthrough; default: return -EINVAL; --=20 2.43.0 From nobody Sun Feb 8 06:04:52 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96B6B133985 for ; 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charset="utf-8" Use maximum width between 2 edges to setup spdifin thresholds and detect the input sample rate. This comes from Amlogic SDK and seems to be marginally more reliable than minimum width. This is done to align with a future eARC support. No issue was reported with minimum width so far, this is considered to be an update so no Fixes tag is set. Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-spdifin.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/meson/axg-spdifin.c b/sound/soc/meson/axg-spdifin.c index bc2f2849ecfb..e721f579321e 100644 --- a/sound/soc/meson/axg-spdifin.c +++ b/sound/soc/meson/axg-spdifin.c @@ -179,9 +179,9 @@ static int axg_spdifin_sample_mode_config(struct snd_so= c_dai *dai, SPDIFIN_CTRL1_BASE_TIMER, FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000)); =20 - /* Threshold based on the minimum width between two edges */ + /* Threshold based on the maximum width between two edges */ regmap_update_bits(priv->map, SPDIFIN_CTRL0, - SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL); + SPDIFIN_CTRL0_WIDTH_SEL, 0); =20 /* Calculate the last timer which has no threshold */ t_next =3D axg_spdifin_mode_timer(priv, i, rate); @@ -199,7 +199,7 @@ static int axg_spdifin_sample_mode_config(struct snd_so= c_dai *dai, axg_spdifin_write_timer(priv->map, i, t); =20 /* Set the threshold value */ - axg_spdifin_write_threshold(priv->map, i, t + t_next); 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Fri, 23 Feb 2024 09:51:25 -0800 (PST) From: Jerome Brunet To: Mark Brown , Liam Girdwood Cc: Jerome Brunet , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH 5/6] ASoC: meson: axg-fifo: take continuous rates Date: Fri, 23 Feb 2024 18:51:11 +0100 Message-ID: <20240223175116.2005407-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223175116.2005407-1-jbrunet@baylibre.com> References: <20240223175116.2005407-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The rate of the stream does not matter for the fifos of the axg family. Fifos will just push or pull data to/from the DDR according to consumption or production of the downstream element, which is the DPCM backend. Drop the rate list and allow continuous rates. The lower and upper rate are set according what is known to work with the different backends This allows the PDM input backend to also use continuous rates. Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-fifo.h | 2 -- sound/soc/meson/axg-frddr.c | 8 ++++++-- sound/soc/meson/axg-toddr.c | 8 ++++++-- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h index df528e8cb7c9..a14c31eb06d8 100644 --- a/sound/soc/meson/axg-fifo.h +++ b/sound/soc/meson/axg-fifo.h @@ -21,8 +21,6 @@ struct snd_soc_dai_driver; struct snd_soc_pcm_runtime; =20 #define AXG_FIFO_CH_MAX 128 -#define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \ - SNDRV_PCM_RATE_8000_384000) #define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S20_LE | \ diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c index 8c166a5f338c..98140f449eb3 100644 --- a/sound/soc/meson/axg-frddr.c +++ b/sound/soc/meson/axg-frddr.c @@ -109,7 +109,9 @@ static struct snd_soc_dai_driver axg_frddr_dai_drv =3D { .stream_name =3D "Playback", .channels_min =3D 1, .channels_max =3D AXG_FIFO_CH_MAX, - .rates =3D AXG_FIFO_RATES, + .rates =3D SNDRV_PCM_RATE_CONTINUOUS, + .rate_min =3D 5515, + .rate_max =3D 384000, .formats =3D AXG_FIFO_FORMATS, }, .ops =3D &axg_frddr_ops, @@ -184,7 +186,9 @@ static struct snd_soc_dai_driver g12a_frddr_dai_drv =3D= { .stream_name =3D "Playback", .channels_min =3D 1, .channels_max =3D AXG_FIFO_CH_MAX, - .rates =3D AXG_FIFO_RATES, + .rates =3D SNDRV_PCM_RATE_CONTINUOUS, + .rate_min =3D 5515, + .rate_max =3D 384000, .formats =3D AXG_FIFO_FORMATS, }, .ops =3D &g12a_frddr_ops, diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c index 1a0be177b8fe..32ee45cce7f8 100644 --- a/sound/soc/meson/axg-toddr.c +++ b/sound/soc/meson/axg-toddr.c @@ -131,7 +131,9 @@ static struct snd_soc_dai_driver axg_toddr_dai_drv =3D { .stream_name =3D "Capture", .channels_min =3D 1, .channels_max =3D AXG_FIFO_CH_MAX, - .rates =3D AXG_FIFO_RATES, + .rates =3D SNDRV_PCM_RATE_CONTINUOUS, + .rate_min =3D 5515, + .rate_max =3D 384000, .formats =3D AXG_FIFO_FORMATS, }, .ops =3D &axg_toddr_ops, @@ -226,7 +228,9 @@ static struct snd_soc_dai_driver g12a_toddr_dai_drv =3D= { .stream_name =3D "Capture", .channels_min =3D 1, .channels_max =3D AXG_FIFO_CH_MAX, - .rates =3D AXG_FIFO_RATES, + .rates =3D SNDRV_PCM_RATE_CONTINUOUS, + .rate_min =3D 5515, + .rate_max =3D 384000, .formats =3D AXG_FIFO_FORMATS, }, .ops =3D &g12a_toddr_ops, --=20 2.43.0 From nobody Sun Feb 8 06:04:52 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FA82142626 for ; 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Fri, 23 Feb 2024 09:51:26 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:e8a0:25a6:d4ec:a7ff]) by smtp.googlemail.com with ESMTPSA id bo10-20020a056000068a00b0033cddadde6esm3711524wrb.80.2024.02.23.09.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Feb 2024 09:51:26 -0800 (PST) From: Jerome Brunet To: Mark Brown , Liam Girdwood Cc: Jerome Brunet , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH 6/6] ASoC: meson: axg-fifo: use FIELD helpers Date: Fri, 23 Feb 2024 18:51:12 +0100 Message-ID: <20240223175116.2005407-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240223175116.2005407-1-jbrunet@baylibre.com> References: <20240223175116.2005407-1-jbrunet@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use FIELD_GET() and FIELD_PREP() helpers instead of doing it manually. Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-fifo.c | 24 ++++++++++++------------ sound/soc/meson/axg-fifo.h | 12 +++++------- sound/soc/meson/axg-frddr.c | 4 ++-- sound/soc/meson/axg-toddr.c | 21 +++++++++------------ 4 files changed, 28 insertions(+), 33 deletions(-) diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c index 65541fdb0038..597fd39e6e48 100644 --- a/sound/soc/meson/axg-fifo.c +++ b/sound/soc/meson/axg-fifo.c @@ -145,8 +145,8 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *co= mponent, /* Enable irq if necessary */ irq_en =3D runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT; regmap_update_bits(fifo->map, FIFO_CTRL0, - CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), - CTRL0_INT_EN(irq_en)); + CTRL0_INT_EN, + FIELD_PREP(CTRL0_INT_EN, irq_en)); =20 return 0; } @@ -176,9 +176,9 @@ int axg_fifo_pcm_hw_free(struct snd_soc_component *comp= onent, { struct axg_fifo *fifo =3D axg_fifo_data(ss); =20 - /* Disable the block count irq */ + /* Disable irqs */ regmap_update_bits(fifo->map, FIFO_CTRL0, - CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0); + CTRL0_INT_EN, 0); =20 return 0; } @@ -187,13 +187,13 @@ EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free); static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask) { regmap_update_bits(fifo->map, FIFO_CTRL1, - CTRL1_INT_CLR(FIFO_INT_MASK), - CTRL1_INT_CLR(mask)); + CTRL1_INT_CLR, + FIELD_PREP(CTRL1_INT_CLR, mask)); =20 /* Clear must also be cleared */ regmap_update_bits(fifo->map, FIFO_CTRL1, - CTRL1_INT_CLR(FIFO_INT_MASK), - 0); + CTRL1_INT_CLR, + FIELD_PREP(CTRL1_INT_CLR, 0)); } =20 static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) @@ -204,7 +204,7 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void= *dev_id) =20 regmap_read(fifo->map, FIFO_STATUS1, &status); =20 - status =3D STATUS1_INT_STS(status) & FIFO_INT_MASK; + status =3D FIELD_GET(STATUS1_INT_STS, status); if (status & FIFO_INT_COUNT_REPEAT) snd_pcm_period_elapsed(ss); else @@ -254,15 +254,15 @@ int axg_fifo_pcm_open(struct snd_soc_component *compo= nent, =20 /* Setup status2 so it reports the memory pointer */ regmap_update_bits(fifo->map, FIFO_CTRL1, - CTRL1_STATUS2_SEL_MASK, - CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ)); + CTRL1_STATUS2_SEL, + FIELD_PREP(CTRL1_STATUS2_SEL, STATUS2_SEL_DDR_READ)); =20 /* Make sure the dma is initially disabled */ __dma_enable(fifo, false); =20 /* Disable irqs until params are ready */ regmap_update_bits(fifo->map, FIFO_CTRL0, - CTRL0_INT_EN(FIFO_INT_MASK), 0); + CTRL0_INT_EN, 0); =20 /* Clear any pending interrupt */ axg_fifo_ack_irq(fifo, FIFO_INT_MASK); diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h index a14c31eb06d8..4c48c0a08481 100644 --- a/sound/soc/meson/axg-fifo.h +++ b/sound/soc/meson/axg-fifo.h @@ -40,21 +40,19 @@ struct snd_soc_pcm_runtime; =20 #define FIFO_CTRL0 0x00 #define CTRL0_DMA_EN BIT(31) -#define CTRL0_INT_EN(x) ((x) << 16) +#define CTRL0_INT_EN GENMASK(23, 16) #define CTRL0_SEL_MASK GENMASK(2, 0) #define CTRL0_SEL_SHIFT 0 #define FIFO_CTRL1 0x04 -#define CTRL1_INT_CLR(x) ((x) << 0) -#define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) -#define CTRL1_STATUS2_SEL(x) ((x) << 8) +#define CTRL1_INT_CLR GENMASK(7, 0) +#define CTRL1_STATUS2_SEL GENMASK(11, 8) #define STATUS2_SEL_DDR_READ 0 -#define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) -#define CTRL1_FRDDR_DEPTH(x) ((x) << 24) +#define CTRL1_FRDDR_DEPTH GENMASK(31, 24) #define FIFO_START_ADDR 0x08 #define FIFO_FINISH_ADDR 0x0c #define FIFO_INT_ADDR 0x10 #define FIFO_STATUS1 0x14 -#define STATUS1_INT_STS(x) ((x) << 0) +#define STATUS1_INT_STS GENMASK(7, 0) #define FIFO_STATUS2 0x18 #define FIFO_INIT_ADDR 0x24 #define FIFO_CTRL2 0x28 diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c index 98140f449eb3..97ca0ea5faa5 100644 --- a/sound/soc/meson/axg-frddr.c +++ b/sound/soc/meson/axg-frddr.c @@ -59,8 +59,8 @@ static int axg_frddr_dai_hw_params(struct snd_pcm_substre= am *substream, /* Trim the FIFO depth if the period is small to improve latency */ depth =3D min(period, fifo->depth); val =3D (depth / AXG_FIFO_BURST) - 1; - regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, - CTRL1_FRDDR_DEPTH(val)); + regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH, + FIELD_PREP(CTRL1_FRDDR_DEPTH, val)); =20 return 0; } diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c index 32ee45cce7f8..5b08b4e841ad 100644 --- a/sound/soc/meson/axg-toddr.c +++ b/sound/soc/meson/axg-toddr.c @@ -19,12 +19,9 @@ #define CTRL0_TODDR_EXT_SIGNED BIT(29) #define CTRL0_TODDR_PP_MODE BIT(28) #define CTRL0_TODDR_SYNC_CH BIT(27) -#define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13) -#define CTRL0_TODDR_TYPE(x) ((x) << 13) -#define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8) -#define CTRL0_TODDR_MSB_POS(x) ((x) << 8) -#define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3) -#define CTRL0_TODDR_LSB_POS(x) ((x) << 3) +#define CTRL0_TODDR_TYPE GENMASK(15, 13) +#define CTRL0_TODDR_MSB_POS GENMASK(12, 8) +#define CTRL0_TODDR_LSB_POS GENMASK(7, 3) #define CTRL1_TODDR_FORCE_FINISH BIT(25) #define CTRL1_SEL_SHIFT 28 =20 @@ -76,12 +73,12 @@ static int axg_toddr_dai_hw_params(struct snd_pcm_subst= ream *substream, width =3D params_width(params); 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