From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 402DD186A; Fri, 23 Feb 2024 17:23:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708708997; cv=none; b=f/AfU4g2vvYNUyF9ovOAJiZYUoE/I8IB/p7IguQnpeePRO1q9pl5QaZIHHshntvTyeGxKX78RHo3PJiXMFD0TF8LWz20gmPQPxYBzod7F7pFdvuL3YUYMNdAicNphMN4XuDN5203QxjXSWRrwHVCVS7KQcwHYy9QXDtREdqXSTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708708997; c=relaxed/simple; bh=N3JiGSIuHPDoA9DuIr7Vrwk1kYjucAxaD+67rAGm5Lw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=roOngCr34mAmAeFKfIsBZqVZ/YKk6KAO5ijR+utUS4ej3e7tbdZLfNCwBwzLp3SM9YUJnSXAzJ8m3Snr6lRIGir/mEgIpT1Ck9as19wz23HpjCK/b9bdQRHxTEySrttGQhbbPCF4Heemn+GYLiFtezY21xRjjkzI6sXHclnHQQ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Xh136TwB; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Xh136TwB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708708996; x=1740244996; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N3JiGSIuHPDoA9DuIr7Vrwk1kYjucAxaD+67rAGm5Lw=; b=Xh136TwBENiFRm4Q27ncYrZNQf6033W3YrgMaJnh8OwdB0QEIayWf59C Xzn9euZjmDe3ywIQZe3cjuMNmvQF8ODz4ZdqXi3wfsBX5O1HrJ4TT4z7n jebrdi932F/QVt0Zgq3tI+6tfSFxKmY8kJDjW6KpB60IAebQf0OhobjNo PVSOJdmnYb5ZO2Apy0OCx2i0oJv52J+tECD/GtaWIohqyrmfQOyVeuF3H A9f1kS4I4Poi2T24Njhtl/9S9YmpgnSqdsnwEeEH1FNV+fqL2jbXU5CHZ IMMgwn1oVNxl6Po3Bl9JXMC9esr4F3lTwWY+QkPMwVfILeJ+lkB2azZET g==; X-CSE-ConnectionGUID: aMpctv24Qgyd0lLqchzPeA== X-CSE-MsgGUID: FQ6J8jJpQr+9AOQUIOPwGw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="247481201" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:23:14 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:22:50 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:22:45 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: , Rob Herring Subject: [PATCH v4 01/39] dt-bindings: net: cdns,macb: add sam9x7 ethernet interface Date: Fri, 23 Feb 2024 22:52:28 +0530 Message-ID: <20240223172228.671553-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for sam9x7 ethernet interface. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- Changes in v4: - Changed the fallback compatible as const as per the comment. --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documen= tation/devicetree/bindings/net/cdns,macb.yaml index bf8894a0257e..2c71e2cf3a2f 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -59,6 +59,11 @@ properties: - cdns,gem # Generic - cdns,macb # Generic =20 + - items: + - enum: + - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethern= et interface + - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ether= net interface + reg: minItems: 1 items: --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C0B6128822; Fri, 23 Feb 2024 17:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708708996; cv=none; b=Y/fnYJQBhx6cy4Co270mf5jGxmp3qXw+4XBHwLj0AbEqT3u1Z1gLbKBCVb2MJlp7SeVBzKMlIdOPawKbTC+xqbJDiIs6QT9QuMWy5q75OZ+e/BDPCMg0qsNYaxihSD2pC+4PfupbVqE7epWFl9n1iOCGgGo1+lxnGDIzeQfNvWc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708708996; c=relaxed/simple; bh=zhJKSICRTYexG6zbU9ZUtOoY1TWprSXwSg3wxv01iHg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DHTDOclmAEyXXGQOycK1zQu196b252HwnnhrzozeCVhS/1go9tr1Oluf20RBmnXyXr9tf7Eco3rOSYqVCD1550rOu+aAeSDnvXI3JbOtjvIhEqa0NYPpO3ueiiOg5jA7g5F6v9Rs137fbevUS3t18Ia6z+60sVPVmNyxhV7liqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=kCjRTno8; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="kCjRTno8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708708995; x=1740244995; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zhJKSICRTYexG6zbU9ZUtOoY1TWprSXwSg3wxv01iHg=; b=kCjRTno8J6iRukPElO3mBkVzsMlbOIiSUnnLh95ZBJ2SNL7aRPDdexs9 wQrYSR53BjvjKlQNwjgHhsJvtRMMlL/2ZGHBFGEAhLlf8VtML2z9p7s8E vaJOb67ljKab09wLxnfR8HmTr5LjgStA5y6ctqDadsrv9bZI4b/aPG6z/ uA+OrV/NIYFzPqWvDFbhfPeX55zS+Kvu9bGTT6XF6iyUbX8oGJ4pmi5Cr 3LNy/GVwkYY3bsI8x4fmLFHhijBGvav6t2tDCcf24hNZ4tkmlnJYWyloL LK0C8IAJ2XOPg2UcmMCkMZaIAhcIbNrHbuSEMugKO7Bof1ukoePfPEjCk A==; X-CSE-ConnectionGUID: kPA6bSjXSWenHIaSylMDKA== X-CSE-MsgGUID: +HLrebGIS6efKqwJlXHSAw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="184009330" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:23:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:23:09 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:23:05 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v4 02/39] dt-bindings: atmel-sysreg: add sam9x7 Date: Fri, 23 Feb 2024 22:52:50 +0530 Message-ID: <20240223172250.671606-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RAM controller & SFR DT bindings. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Changes in v4: - Updated Acked-by tag --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Docu= mentation/devicetree/bindings/arm/atmel-sysregs.txt index 67a66bf74895..1339298203c6 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -11,7 +11,8 @@ PIT Timer required properties: shared across all System Controller members. =20 PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" +- compatible: Should be "microchip,sam9x60-pit64b" or + "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b" - reg: Should contain registers location and length - interrupts: Should contain interrupt for PIT64B timer - clocks: Should contain the available clock sources for PIT64B timer. @@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", "microchip,sam9x60-ddramc", - "microchip,sama7g5-uddrc" + "microchip,sama7g5-uddrc", + "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc". - reg: Should contain registers location and length =20 Examples: @@ -63,6 +65,7 @@ required properties: "atmel,-sfrbu", "syscon" can be "sama5d3", "sama5d4" or "sama5d2". It also can be "microchip,sam9x60-sfr", "syscon". + It also can be "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon". - reg: Should contain registers location and length =20 sfr@f0038000 { --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FAFC823A1; Fri, 23 Feb 2024 17:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709056; cv=none; b=sg6ql+jfKZhlttpChWo0OUDJ35MqKwUmmFadO+F258IerYOqxcr5PQlu3oS7l/X94cIZc43w8HgcBTARURNZj1xY3KFGZwJGy+XeCi1PYN3S90EmJuUMaRGmE2pMaiEsMtNF1wDthiXMfh0H/Pv35Ap9pFbq0jpoQONLWBAaT84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709056; c=relaxed/simple; bh=wnWXsy8zY6VRlAbrWYh9V7zguQIGEAQdCsEXb2Ur2W4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YXdoXT4cZPBad+6p0K48HTCHW2ihYFjv5gxNHqk9sSrNUUB55kcpb/vkUSk+4yrh1t7KdMQf1Wc2OyqMu/W7xBTG3leieTLBUXvd0crFvy3bbOfGcVAqx26plSr1OADVOqN+doaZLbQyvx8gDId7amb1PSkvf5AD9E/eLzk7tuI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=GerLm7Fi; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GerLm7Fi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709054; x=1740245054; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wnWXsy8zY6VRlAbrWYh9V7zguQIGEAQdCsEXb2Ur2W4=; b=GerLm7FiaaVVr/1cYD19q8eEe8MJqCjfZLlIzha9Ei7DDnKKEDWr961t 334wXWQipjtb6ZtnQyF5ktHubrlS5g3PW9jj1D2Rp00nPN4mkagFFcYjv XJE7VxyVTkFpI/CPbG0uiyCvMr7ukBZ5m33o7Uy7/o7Kz5gvTomGmPlKR FbdDLE9Ck0Vq6+cjYix6/NjrbJwwK7+vXqTs9po9c2+t0aBSriEqwBcEZ uzq/6VPMHKInYCYz33Ft4aT+hC69yVFj0abuQQ9wSbs1EbESIqD9XISWd qTft6P2v4R44YzV5lBY5mICGoxVFnmDswbmxZiPC01cO0w0n/Bbx4afcc Q==; X-CSE-ConnectionGUID: iohkZhWBQkWaq7QUPmZNTw== X-CSE-MsgGUID: W6oFT/8mTwCJ6jlDgdbggQ== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="18276013" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:24:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:23:58 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:23:52 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , CC: , Rob Herring Subject: [PATCH v4 03/39] dt-bindings: crypto: add sam9x7 in Atmel AES Date: Fri, 23 Feb 2024 22:53:10 +0530 Message-ID: <20240223172310.671661-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for atmel AES. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Tudor Ambarus --- Changes in v4: - Updated Acked-by tag --- .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes= .yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml index 0b7383b3106b..7dc0748444fd 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -12,7 +12,11 @@ maintainers: =20 properties: compatible: - const: atmel,at91sam9g46-aes + oneOf: + - const: atmel,at91sam9g46-aes + - items: + - const: microchip,sam9x7-aes + - const: atmel,at91sam9g46-aes =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E039112EBFD; Fri, 23 Feb 2024 17:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709126; cv=none; b=np5lM7Idt2OTkg0DQCECD8H7cu0Zzv9t0Gb5zMNB9Oi250LY2vtVczVlkqLyXsbUVEuChsvusvi8KZ6rhw4Zq6gtRdRNrfIS/bzGjTvThMCcEPNaNh7m3vbvsVrOurNbkK1CRht+cEuqR1KQaN6b1f9NVsdGyyHBmdFNMHqNwuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709126; c=relaxed/simple; bh=5r33dar4uXTcIxiLo2EE3ZhpnzHXGBgTGDLgfEfSrvg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Tp4XpqMTa1A1d1oNU1qbvlMgq8OROqkh+kNK3YQu06rpnwqwURIYAM5iLbZpCIoS7cpkiV3CFd4xP9PXUnaZWg+5QfvVCelNap+81pB3XNJ0wEpmbHkjjbDNoZJUB/2Pm+m4HTyEjVUIpWK2yUWUWi43A2kElfLfvATCFeJdYRo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=tIckocSj; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="tIckocSj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709114; x=1740245114; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5r33dar4uXTcIxiLo2EE3ZhpnzHXGBgTGDLgfEfSrvg=; b=tIckocSjCuk+2aPLKLj7/0i1K/UQ//m+Yc0JUIxjGz0bUfOyiSsROYUq ThkaN5t2b4DcV/03JLdMfjj44iwyNGKM09/5BUH0GuFSLGKeNMDGV/7Be QxHKXYdEYQ96byGBApbGbNSnKpdJqeWcpocuRsasjctJYCnywFKQAQ6JK 7bk8Dgb1A9R11TfvgrgWtCaZdfzkc7XOSJ+rdxQtxjoMQwtLYlE+Soa1L eRyfGj2ae5qZVWlWDtMtKuuX8U5bMV07MI9f1+PbPh66i4OaEGU4D5sGg G1PTG8vSDTFpAVuKroVfrtvpUglFIVPxIFwop+VCLkKIH28C+BikwISoT Q==; X-CSE-ConnectionGUID: dqFe5GJiTEWg/SG7rQOAsA== X-CSE-MsgGUID: OJqcd/JwSvGUi+SaCzclTA== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="17267159" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:25:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:24:44 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:24:39 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , CC: , Rob Herring Subject: [PATCH v4 04/39] dt-bindings: crypto: add sam9x7 in Atmel SHA Date: Fri, 23 Feb 2024 22:53:58 +0530 Message-ID: <20240223172358.671722-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for atmel SHA. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Tudor Ambarus --- Changes in v4: - Updated Acked-by tag --- .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha= .yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml index ee2ffb034325..d378c53314dd 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -12,7 +12,11 @@ maintainers: =20 properties: compatible: - const: atmel,at91sam9g46-sha + oneOf: + - const: atmel,at91sam9g46-sha + - items: + - const: microchip,sam9x7-sha + - const: atmel,at91sam9g46-sha =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC75312D1F9; Fri, 23 Feb 2024 17:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709130; cv=none; b=moor8x7zImsqylNh98MA03X7mjbvh3n0jWzqz6kpWCrtxO76Zkx98f38OCj5/vzYNsBaca81lpqZMVXKEyWPIJPI0R1ElzZDK9XSmm81hv+D2tmLEP+7asH9qHunXJKMTnORY0H/+l9hRjwy9GLwvnPmhDHH72iOzZXj+AyDJ1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709130; c=relaxed/simple; bh=/hz/8AXXj+ZzSkJYQl0qnE60nI3MGQJXY6qlslTKKp0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bT3yd/dBQS0D9xmhyyiAVUKn+YcWxhHiSi8kTPWL7fC42qH/oHwH3RvGeKFRr8cpiL0cQdf3z8JGIJY3R1rgrPz5DzbFA7jCV5pXjmpu/zeS4C06eC415BLybVffiG5GoOpAh0CUYa57Y7JPRRmaTYGz7Xe0udeQBxlrGCwctKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=yqoXhedy; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="yqoXhedy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709113; x=1740245113; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/hz/8AXXj+ZzSkJYQl0qnE60nI3MGQJXY6qlslTKKp0=; b=yqoXhedyeY9HQD5E3eqc/HXSflSy8Zpg6TyFpCXS01pBo7pTo/mcXHCC bg2VEEFoKfmX4/6l2P6wluV2cSoxe/J+q7GBATkFT4nroP5y3dU/PmQxS J7Y8AvMT4JDFV2mD2LpvqMMUZ9fo/gJsupQcvsHbHrbaN8rqdAQbkDZb/ hvuUaCZkfXJAGhfPdBMBlV8eJYvUbFTYxir2u/4E+O/XYqVE7qnY6Ipn8 nTislpP5fMj9hSD4MXUL0UMH4xOKJtKNwN7TNH11SxEDBmyL2fZlsSn6E uWVBpaRJ8yZAISjMOo4VPLgzBiTuPOEBenOO9nV2FP0zj1/e3Mmc22pSS A==; X-CSE-ConnectionGUID: /5CNF92eR9i+Xpx5LCibjQ== X-CSE-MsgGUID: xtED5/yRT4aDO/oItKs/JA== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="184009396" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:25:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:24:58 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:24:53 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , CC: Subject: [PATCH v4 05/39] dt-bindings: crypto: add sam9x7 in Atmel TDES Date: Fri, 23 Feb 2024 22:54:45 +0530 Message-ID: <20240223172445.671783-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT bindings for atmel TDES. Signed-off-by: Varshini Rajendran Acked-by: Nicolas Ferre Acked-by: Conor Dooley Reviewed-by: Tudor Ambarus --- Changes in v4: - Updated Acked-by tag --- .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tde= s.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.ya= ml index 3d6ed24b1b00..6a441f79efea 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -12,7 +12,11 @@ maintainers: =20 properties: compatible: - const: atmel,at91sam9g46-tdes + oneOf: + - const: atmel,at91sam9g46-tdes + - items: + - const: microchip,sam9x7-tdes + - const: atmel,at91sam9g46-tdes =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 768A61384A3; Fri, 23 Feb 2024 17:25:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709130; cv=none; b=CDB6XhNJykIwtpGDmMk9IDFz9Gm4wG53F0EuWmPkyTnxUL6aUCJR2HoRbQGrYpSM4egsZMI3TMIT8Wy0RQuAVOg2Ev5/n6oidj7boBjakDr1KoErJPSj/uV7eOjQscqC9JJCniEohisxmTiHkSsC1iiDYD0Z+uQqu5haZM6SHNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709130; c=relaxed/simple; bh=ndkSQI5Phz/pugFNXsdTMXAeuRKThwlhw4akLYKlS/k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C9oJm4GNmNGBvNcSs0LcKwhfHACDPmh1R2ZQ/n85kDC9OPDOgWHb16+Z/PQlY3pPr9l2zCWXlCKn+7YvKvmZbpvzNuj7QLx8eOiIyT4cNT1V+lb2VsXIg1AfUUrGdjvm3QNTqSbGuRdoV4jw+Rn6ELJb9kWp3pb+kasZmkg3eMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=tAk4AQFW; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="tAk4AQFW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709113; x=1740245113; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ndkSQI5Phz/pugFNXsdTMXAeuRKThwlhw4akLYKlS/k=; b=tAk4AQFWYhupwAF9vIBjLZw2txGkWJ0ejHv2revyVhEf6Oyl9Qzlhbj6 J/3qyIqWMbIENcNSDkrPOlUM/pvdAWfO8YITeadlA0uB1RNqIpeUWGlvF UotoFuhwe8a1Yuw6Ysc8s3GlpJL6giSNcnjjkCuOnLB2rX0cXqs0FvOzG hdo2v4h5RXych6yVxqT0rkgwsGRv5tuzwuR99bzidKJKn74zZJayLruPh ZokjMzsXihH1VtxWfxFLQweIjBa6tt3MXiEBimYHl60bezjWV+poBrWKi c5tmcBsbUbZLJcVmQrQHijnNnQo4J1v6ObE2g1KC10qSXWCqdAauil/fd w==; X-CSE-ConnectionGUID: v7hxkNo6SBe1d+wSFbAzdA== X-CSE-MsgGUID: 5MMVxV7kRIq6fdV2JxxX+g== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16734401" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:25:10 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:25:08 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:25:04 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v4 06/39] dt-bindings: i2c: at91: Add sam9x7 compatible string Date: Fri, 23 Feb 2024 22:54:59 +0530 Message-ID: <20240223172459.671832-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string for sam9x7. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v4: - Made sam9x7 compatible as an enum with sama7g5 compatible - Removed the sam9x7 compatible from allOf section as it was not needed like pointed out --- Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml b= /Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml index 6adedd3ec399..b1c13bab2472 100644 --- a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml @@ -25,7 +25,9 @@ properties: - atmel,sama5d2-i2c - microchip,sam9x60-i2c - items: - - const: microchip,sama7g5-i2c + - enum: + - microchip,sama7g5-i2c + - microchip,sam9x7-i2c - const: microchip,sam9x60-i2c =20 reg: --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DB651339B6; Fri, 23 Feb 2024 17:26:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709172; cv=none; b=tpdiTPh7f1X5YqrWZDEkorhYQ0XqQ6OQvIpZFE5xGutFM6UG1toXPZeovjArAm/AdfcvGH4o19Nhk2B68i6pI5raP5VUHIkVgTEyUFnVck0Agis8/tBncG0bjYlcUJXZOqE5mMh6pin26VqPsvrNPa7cCcoSgwNtGey+JhnEWYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709172; c=relaxed/simple; bh=kk/UiHsga5gmFS3zENAHY1LBewwoUNLNuFmDepPq+yA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mM0lXo6IDmrGZHkGpy5wOyzLzRqJQW4O51PKG0p/z7weJblVqZaEvcoejA48GUJEKXnOJKP8XP12WZBLrT+WdlO6KIbSV9aFxijhKmlGL/IotfOvvcRzs3hVRwUzIpxgxydVT+O4pD/Rg0zjQ3672BWQNkpdnakV1hqeNTDbZnE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=GU46yDfo; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GU46yDfo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709171; x=1740245171; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kk/UiHsga5gmFS3zENAHY1LBewwoUNLNuFmDepPq+yA=; b=GU46yDfoPS3ajRwVdtMZwnOHdK3gYg+k3Nm8yehRpHOKqAXjtVKEbC8b Sd+pTP565rAzmV0rB75xaE1GONdis/5xX/DpPOJgQM4KBK51xqwVoBBqF f+IQpmhJ/vlmapk0G7h8j2vvcOg7XardxFJJS7W1cUbJWzg9/6JneQSH0 V+ehvT58eu7Kk3OCozX9HrBApDfgu1Etm6T73yKG4W9EMpPll725yHCW0 WIllOmdeZs2KoJwrgo4DA2Y1sNs+x+Mk/kGemQe4lIw5+Zk6kF5FHtSeo YBZuHdfFAIFW+QLeH3K/1cQBQoQ8qo2uYh7iDQ8Pq6XLd3ix9cRYGoVzp w==; X-CSE-ConnectionGUID: Ely1r2TiR4Wv3Obixr7frw== X-CSE-MsgGUID: VI9R6XZzTteN3DbNWpHX6w== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16735838" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:26:10 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:25:19 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:25:15 -0700 From: Varshini Rajendran To: , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v4 07/39] dt-bindings: atmel-ssc: add microchip,sam9x7-ssc Date: Fri, 23 Feb 2024 22:55:09 +0530 Message-ID: <20240223172509.671880-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add microchip,sam9x7-ssc to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Changes in v4: - Updated Acked-by tag --- Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documen= tation/devicetree/bindings/misc/atmel-ssc.txt index f9fb412642fe..894875826de9 100644 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt @@ -2,6 +2,7 @@ =20 Required properties: - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" + or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc" - atmel,at91rm9200-ssc: support pdc transfer - atmel,at91sam9g45-ssc: support dma transfer - reg: Should contain SSC registers location and length --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 327AA143C5F; Fri, 23 Feb 2024 17:25:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709156; cv=none; b=f3Q2lwriYrwYYWgRWgIIYvgLDQ1Nu3yoPWzm4Qtd8N1YYgq0lPvq5N+62lpolFKlPneHyatVTNbFhosjtOF4ouCaphfmwZBvqNB6GggJLmm9XL/poMNFhI/IHz7LRvS+GSUEqboAKO3VRSJoz4xZuMNFU/tDZny/d5hw5JnYj9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709156; c=relaxed/simple; bh=igHDeF92LiyJV6CYdDteCC2bRTjg8rQRg4+bhnAd1mA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EIjqJlVk8cwYlt68oUwFhd5KZmTnOR0Q0qPZXYnz7MiCR4+oW3dPoJHbra++l3tfOBJpcYQcFfL2Gmgc5VqTX8MVav2m3e/MsS+++SBJq6m9p7RSgO1cEwQBCEFp4epBfrAw8kRrpKnXQRl3KfOBxLAgXQYI1hTPA2+wZolC1xQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=wZPnVDIE; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wZPnVDIE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709156; x=1740245156; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=igHDeF92LiyJV6CYdDteCC2bRTjg8rQRg4+bhnAd1mA=; b=wZPnVDIEbrCMeE4jMHHMfaEMJiTtDfzo7uRbchodJR02JmSkgKFAkHmw +aVPLItMkFEEkfkEKgm8nY+izgRsY5Xg6uZWOalCVNjV9lsidUrQz6yTc 6Zf24ivlOo975UiRmuBKb0ZTxx6+3UD55fKl48XeWGzYpnd2dGl0Mf1Dj 7Z2DFuV9nwj1T9ezI6RxXYxmtgrazz/9/DypgfC0ISVNhNXWV2jbdVC6Y yJkmxuJcbTUd47ABc/YmVpoWkgFLuQJ4ittrwNjL7GI+KLEjFVBYxsXhQ zqrs2WedvzJ/okFDkLt5kk/I34dZ+jBdBre49l0v9q1uqoGGxKD6bkCtq Q==; X-CSE-ConnectionGUID: yqAR4j5MT/u3WWYb46nLgA== X-CSE-MsgGUID: BwHaQGmTRgSiNQnK3eo0Rw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="247481342" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:25:55 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:25:30 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:25:25 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , CC: Subject: [PATCH v4 08/39] dt-bindings: atmel-nand: add microchip,sam9x7-pmecc Date: Fri, 23 Feb 2024 22:55:20 +0530 Message-ID: <20240223172520.671940-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add microchip,sam9x7-pmecc to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documen= tation/devicetree/bindings/mtd/atmel-nand.txt index 50645828ac20..4598930851d9 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt @@ -56,6 +56,7 @@ Required properties: "atmel,sama5d4-pmecc" "atmel,sama5d2-pmecc" "microchip,sam9x60-pmecc" + "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" - reg: should contain 2 register ranges. The first one is pointing to the = PMECC block, and the second one to the PMECC_ERRLOC block. =20 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD9C413A867; Fri, 23 Feb 2024 17:25:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709158; cv=none; b=VbF45MLiVFJG10iifuYdMTyf7nJDVrKnDVgpSIdi+lyb6vCQhoXNIFGOJ46veRiV6vhV8Sblvm2NvDT8rlq17he6dHwH5sI98Nq5YybXugtp2laVRB9C7HeR1/yIrJXCUIP3wX6Y2BGODwRton+KZXRjFYXuo6J+prJ74BblAog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709158; c=relaxed/simple; bh=g91B3meQdr4oVLlRU/qSl9oUcfHnjcbSkMBCurrIdyQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L/8BQ6R5DvZzKQVvil7IIeMPQWf6Mi0dTVwA+eJxCsWSUWLJuffoOHFo9BRJANaKpJ4fUmLah7rgjAeeY89CBihpEYN47VOlMnw+xabeGu5bS5SYaJFyVHaWuBWxWT3W4684/vNljDuoUiF+a07od6vqVYtwxaLZMFIV12zQRuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=zZMJ2HuC; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="zZMJ2HuC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709157; x=1740245157; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g91B3meQdr4oVLlRU/qSl9oUcfHnjcbSkMBCurrIdyQ=; b=zZMJ2HuC1AQQASXst/7oYQn0ccrlHR4RQ8a7BUWq62cFnaCu6wnif2rj u/sUxhE6vlH24M3mYYLu6J1TOFDzR3XCtjYOJjAkoGl/vJKP+/v70Bo5b muWnjJtMcammzMrYNSeYn2AH6QH/zeBWnWi3xtkNzXwEBYpXD90+y1Zct 81E5BnQY16d24g8oh6ZUcoRHMjLOyGJ519PrXWl7nfXYSRQZush3OVS4V 327L/+t0eEWNpH0q6vnqIJeW3fNTYxIKhhWaywbcR7CDtQH2f7m4uAz0G 4DuM6GV1RgfXroZ8iVa3EQKrJDuOlBaG1x8NGNykqOAXAK1DBxaaTsgXp Q==; X-CSE-ConnectionGUID: yqAR4j5MT/u3WWYb46nLgA== X-CSE-MsgGUID: RU5l/ePiSym6AdW8F3g4+w== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="247481346" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:25:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:25:39 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:25:35 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v4 09/39] dt-bindings: pinctrl: at91: add sam9x7 Date: Fri, 23 Feb 2024 22:55:31 +0530 Message-ID: <20240223172531.671993-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree binding for SAM9X7 pin controller. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Changes in v4: - Updated Acked-by tag --- .../devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.t= xt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index e8abbdad7b5d..0aa1a53012d6 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -20,6 +20,7 @@ such as pull-up, multi drive, etc. Required properties for iomux controller: - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" + or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can= be configured in this periph mode. All the periph and bank need to be descr= ibe. =20 @@ -120,6 +121,7 @@ Some requirements for using atmel,at91rm9200-pinctrl bi= nding: For each bank the required properties are: - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or "microchip,sam9x60-gpio" + or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-= gpio" - reg: physical base address and length of the controller's registers - interrupts: interrupt outputs from the controller - interrupt-controller: marks the device node as an interrupt controller --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DEDC143C62; Fri, 23 Feb 2024 17:25:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709157; cv=none; b=lahNm4+LgHUItm9SetHRCtLmp0Z990/DNhfc5xrYmOYqaTS4Kkj8M+nmb7ZEvuIB6mLjKlrBahaI6uMQZB7b1XAqZcMqEcwXhhKI5LyGBIpnN4hyTby4hVY4sRgstiuPIUPEZCKbTO37JMMxx2B9vNxDxKk7uNyS4ch0At3HuGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709157; c=relaxed/simple; bh=1pa+nUeiMz0aVLSe9rutUmmIoy3zszoSlnt9C29TgLk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PO9hmHkZA1ax6xEKaIqdNOxRL9A9rnfFwNVbNLYNzToV8v9JCoFd6ia/cnX1NFafp9RvKjAJxdelXYZMTjJO8GO2Aa/WNRFTdmlohdauDZ/idDy93A+PzC/QD3ez84p/xcicN3fcWXO4pKX4/fpzy+eFTJle+JSVGUQFJZVvn5A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ryi3R1uN; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ryi3R1uN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709155; x=1740245155; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1pa+nUeiMz0aVLSe9rutUmmIoy3zszoSlnt9C29TgLk=; b=ryi3R1uNhxUfhSqPpHzb6NvvwTX5AwJLdGASi8UXGZBMGe+MJBymDUuU mY0/b+eCYcgjzmiFgchyXJXgzOTBKD791/v3K3tnouzFoLaF1GAXFaZRI BI4aKhBeMFnbu4LsoHdbfaIYKYYN+5yTpVsSmxzaSvnSC3V8xt83B/p7T ZSc60kQYRs3ykG+fOG9jcer/XmCNQx99qmDyosc7+Btd2QXQivzhLaQ9L SZ2CgrePWyQOUD18W73yoaEhGQN0I/i3aKLwSx9xxYdQewhsX2Kh/S5pX iBjpa0z65sYqvovsYwDxRcYWIAjzZW9yj5BKBj++AN80kda5hxKD8DOq7 Q==; X-CSE-ConnectionGUID: O0kOdwhCRya6tisT8ZRfCw== X-CSE-MsgGUID: Bx/RauiIS1ukR8iK3Ocziw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16735824" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:25:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:25:51 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:25:46 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v4 10/39] dt-bindings: rng: atmel,at91-trng: add sam9x7 TRNG Date: Fri, 23 Feb 2024 22:55:40 +0530 Message-ID: <20240223172540.672044-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatbile for Microchip sam9x7 TRNG. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski --- Changes in v4: - Updated Reviewed-by tag --- Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml b/D= ocumentation/devicetree/bindings/rng/atmel,at91-trng.yaml index 3ce45456d867..b38f8252342e 100644 --- a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml +++ b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml @@ -21,6 +21,10 @@ properties: - enum: - microchip,sama7g5-trng - const: atmel,at91sam9g45-trng + - items: + - enum: + - microchip,sam9x7-trng + - const: microchip,sam9x60-trng =20 clocks: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF8AB12AAE0; Fri, 23 Feb 2024 17:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709198; cv=none; b=av1GFtAWNuf8xHYU6vL0HvGfVGcWredQtNcY5AKQ0k5Z8RcgZvA8VeWtNmP8YZw1c2YcXgEzP5gvuHbREL7GVrmsAss7QwKWk9AevKF35g2ahx45Uw95WFkIKzSxXTZtZhIGCooWLzZY/Mbh3NZKoz3STvQ/VfrvUPsXjKHkAzY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709198; c=relaxed/simple; bh=7D7QN22dZMevSxIgkvWzAcMkdzVrR6HmrNDS9+rfmco=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eJh3lRxafgGBdznqYcweQBz/Xw0DH7kOAxgWqibLI5aA39dTVgZWLVK7jgIj4PDNiu5bKhqOGawZHjX/vcR1KXLdhjjVcRrDCrpMkiDCmCjqFvNMH4ozz5enQkwxWLmz4bepj82Tjc4qciawz09nDQ3kiQDAH/Wt0E2ZYdrXho0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=c6h1r/6r; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="c6h1r/6r" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709197; x=1740245197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7D7QN22dZMevSxIgkvWzAcMkdzVrR6HmrNDS9+rfmco=; b=c6h1r/6rEJ9AcBU7/cOZVnwEIe37o9fZfTSdd5lltN4ADQZ5p6WDtcCa exLVeT+SJZdO4i3mJHsi6qg1WDn4ozXFodRIzHabKT+ehf5w32G3F6LPr /DOgONRSJ/2KW8g7I2EcSnomCfJAjLzlzbsRuMWmMPJuWLvDzkKp7aw6s Vljw19zjifsQQExepI/A6tht5svHlSIdO2b6YBAlrtAzHbvopx4sHdZVT BUh3PZb0x4bTCiUkj+eLwSR2i9N3I/jJvDy3e2OXIrLW6E0cDVXmTi0+G 2m+0rZMv0iGixwAiR9pWDEvhxmy1FV7rFu6WAwJqBsijl3SCYC5N5oTGM g==; X-CSE-ConnectionGUID: +I+FaeeiQtWNdanq9i7vCw== X-CSE-MsgGUID: Usph6H1EQ5SYvZ4cQ2lXHA== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="17267227" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:26:36 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:25:58 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:25:54 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: Subject: [PATCH v4 11/39] dt-bindings: rtt: at91rm9260: add sam9x7 compatible Date: Fri, 23 Feb 2024 22:55:52 +0530 Message-ID: <20240223172552.672094-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible for SAM9X7 RTT. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v4: - Made sam9x7 compatible as an enum with sam9x60 compatible as suggested --- .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.ya= ml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index b80b85c394ac..a7f6c1d1a08a 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -19,7 +19,9 @@ properties: - items: - const: atmel,at91sam9260-rtt - items: - - const: microchip,sam9x60-rtt + - enum: + - microchip,sam9x60-rtt + - microchip,sam9x7-rtt - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FDE712F5B5; Fri, 23 Feb 2024 17:26:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709174; cv=none; b=KE/kqRDwqZMTEv7I69wu2of8BGsSS60Pylc/qd9l1rHw58g2a6J8PobObiZfaeAKIfdKmT3FGVv4weiAnVKQDx1v40Fy1lX1+79SKK3f5906ncrYc69Zs2hSlEtVQLwjyA0wz8YZccKnxOz29e+2w9qrjyt9M5Y/7KXSphhU3i8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709174; c=relaxed/simple; bh=BZJTjqUHwuQlXlsd7x2WfXnXThGZTz45hMZUxsxzH20=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hH5+ZjcTB5YAdxD+XhhsFKR/TD+2BARsuGJM7Bqr4HBjeGedg8qSvM+5GrsrxtUBYnbo4rAMzYb64Cqke7KFJUBa08P092I1iSm+UnMcqDJbU17x2rn5YxQziDnMAUaJVrkO+sZzY+UsDT6k0n9MYEowX5/aU09RsEZc7OPhwjw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=2C9F9l/s; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="2C9F9l/s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709172; x=1740245172; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BZJTjqUHwuQlXlsd7x2WfXnXThGZTz45hMZUxsxzH20=; b=2C9F9l/sKx+IpXU2K7JoS5ggXsuZHhLsLYsugjmNCx85baycCgX8XKiQ vUKhIQLVHzceQGG1fbCBa2BgOsSFcFfK0qUL6rfyIA2i+TPP3+OI0Lg9C nemNzF312XF5Uo3Elh5z5cQG5Gd2/joER1Nx95Hjin+AJqsPAlJXzdwVi 21iuW4H9toZihm3QWOTD6Sx8YGzIsr39vdoDy6GDOHpD/fJMDmZPe3rd6 jgREmh05+NjVSdZ+D2kj35xSndZy/IlFWa0dwmtvaOQfMjcPtVNDSP5cY hMX5KcZQGxAMnQcpzALSYmiYVgTTHKk2zKAAHJkWwD+OEPy3LD/1sqO9a w==; X-CSE-ConnectionGUID: Ely1r2TiR4Wv3Obixr7frw== X-CSE-MsgGUID: M4vXw7loRkeKQ5VN/WOdcQ== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16735843" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:26:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:26:08 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:26:02 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 12/39] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7. Date: Fri, 23 Feb 2024 22:55:59 +0530 Message-ID: <20240223172559.672142-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add sam9x7 compatible to DT bindings documentation. Signed-off-by: Varshini Rajendran --- Changes in v4: - Fixed the wrong addition of compatible - Added further compatibles that are possible correct (as per DT) --- .../devicetree/bindings/serial/atmel,at91-usart.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml= b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 65cb2e5c5eee..30af537e8e81 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -23,11 +23,17 @@ properties: - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart - items: - - const: microchip,sam9x60-usart + - enum: + - microchip,sam9x60-usart + - microchip,sam9x7-usart - const: atmel,at91sam9260-usart - items: - - const: microchip,sam9x60-dbgu - - const: microchip,sam9x60-usart + - enum: + - microchip,sam9x60-dbgu + - microchip,sam9x7-dbgu + - enum: + - microchip,sam9x60-usart + - microchip,sam9x7-usart - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart =20 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 824D812F5B5; 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charset="utf-8" Add sam9x7 compatible to DT bindings documentation. Signed-off-by: Varshini Rajendran --- Changes in v4: - Changed the subject prefix matching the subsystem - Removed unwanted '-items' from the syntax --- .../devicetree/bindings/sound/atmel,sama5d2-classd.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.y= aml b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml index 43d04702ac2d..ae3162fcfe02 100644 --- a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml +++ b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml @@ -18,7 +18,12 @@ description: =20 properties: compatible: - const: atmel,sama5d2-classd + oneOf: + - items: + - const: atmel,sama5d2-classd + - items: + - const: microchip,sam9x7-classd + - const: atmel,sama5d2-classd =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81C4612F379; Fri, 23 Feb 2024 17:26:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709192; cv=none; b=MKYKAPfYp9iBObTQrAF7yCKGKxtmb5a1S4PaKLx5dL8TaY3BcW/FgVh9nU4XCb0TWmbbL75d7zNBuCXoSWukmDH82oa3Q76fdZVRL/yvkjO3FJ7MQjN/LaoW8sLR6yJHC0pQJN4q47CkGkEIY96CoBgQN4LMcLnwDZa2UT2EINA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709192; c=relaxed/simple; bh=mfK3CVg0+fhZh3qQ1M3R9KIJX9QW8WJLAAfA0+fk6+Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=X5qbZRtqNfoiHtK5ce0SVH0sK+OL3VbQqK0wXl4cM9jA57Atezcup2eqqFdf2y81N2lJhpo1YGhM2IQtvpG/C1PaECGhs/Ek8IRTd8JcXmjNInj4NjBbKho5FRXTQ9V7sRNJBFoWHAlh10vMWwgjUC5Y0dzZ4IiYXB5ho1Uax5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=WL20f8zg; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="WL20f8zg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709191; x=1740245191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mfK3CVg0+fhZh3qQ1M3R9KIJX9QW8WJLAAfA0+fk6+Y=; b=WL20f8zg6yqo5aIbPgQQg10smVwZWGBCDz8wRWLy+Bspq0mPhFhiUJsz hZU+uZ8dfx1o3W+3VTBSXYLgCu/dg7c8Q+aG9LLX0V/nKCbX9fTUHmSb6 7dLgXOmXd5ee1AihERkRmVsAqR4OjPeMDr/sHHs5cCzGbmg4eDbPoevnS GQQ000H+Rdp0PLLTlmLKOYfimvdw9S7eApVhunn9W/LaHKX4gV8V6ObPH gLsSFOfK1Z+jAvUsfSj5jOy6UTr1jmc4YoBLpH6EeGTCVOEoJyFuCaCVu qjhKyTaV0Qpx47Qu08yJec+u5IGnuuNOgk3pSUGkDCDgmvS1P2nadM4a3 w==; X-CSE-ConnectionGUID: t18HA6KHT7+gZ8BIMsEZ6A== X-CSE-MsgGUID: HS/vplxHT7qt8E56e2XNrQ== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16734509" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:26:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:26:27 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:26:22 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v4 14/39] dt-bindings: pwm: at91: Add sam9x7 compatible strings list Date: Fri, 23 Feb 2024 22:56:19 +0530 Message-ID: <20240223172619.672262-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible strings list for SAM9X7. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b= /Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml index d84268b59784..96cd6f3c3546 100644 --- a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml @@ -25,6 +25,9 @@ properties: - items: - const: microchip,sama7g5-pwm - const: atmel,sama5d2-pwm + - items: + - const: microchip,sam9x7-pwm + - const: microchip,sam9x60-pwm =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E343312FF8D; Fri, 23 Feb 2024 17:26:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709207; cv=none; b=DEgR4vngauvLFCjuGxHe8x6b0kqCmH56FwcfoaMOVrc4xw+K9YHolwTjEqGbmLa8A5ckuRyCGHI+7eAq63IlFmZ8k5AftwnJshcLSEhR/MeaoU1AlhdvtbCZ7IA6Gfs3YxGJ5wp8tNFnRTl9LKRQzf+hdOVx6jggLdO56/qfPO8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709207; c=relaxed/simple; bh=b6RY3R0zuqGa4j5oeK47mHYhlfqQm9cq85DEmMV48OQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N7icjn4/ucxl539M3DS2WHMbVtUdWheZvD6dYVWnnqlkiRtEtpHoCnGPCKFJ5sJJbmnfkIOJL148iXnt3jUFuWge5vfR0h4kzhZ481wmbDVnyRkEBRIxgTlrea6k0reLH5/1VO2GPneDxcT+rF89WTXdhNffkpHnzMpfL3/MXTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=f2dT9f5T; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="f2dT9f5T" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709206; x=1740245206; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b6RY3R0zuqGa4j5oeK47mHYhlfqQm9cq85DEmMV48OQ=; b=f2dT9f5TMBa8eIxYaeLq1k3vPQlLUCZAijaqp6R6zp5PpjpPmLCHMtN/ 7vIVLmK8uqRptfezv+RtIwWHJLNjmu8EjOY0LX8HkcemGfjw0u0wm3/4U b9/jUzh0rMuPBB0H+idG/TrXTduDuLdRcYjav4JESxzpLVt5qf0+urFTy 2aLHcpApCIwQHVvg+32BjKG8YfwbKcooyd7YE0VR18ILD7xhAanOIP6JW syH9rUch/+MgwP4Dv6M2OaKckfKGPf6ytTPPs8JO0IhvNTOOv/C/I7JDL gngVSdQQPPtiW5bmSpvBW6CnoReoKRRSWP2KdLavSPIM9C3j+2p1VhBEl A==; X-CSE-ConnectionGUID: wf8h5iB/RBWgwQC4yBIXdA== X-CSE-MsgGUID: H52Puku3Tpewb437Nrp6SA== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16734528" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:26:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:26:37 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:26:32 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , CC: Subject: [PATCH v4 15/39] dt-bindings: watchdog: sama5d4-wdt: add compatible for sam9x7-wdt Date: Fri, 23 Feb 2024 22:56:27 +0530 Message-ID: <20240223172627.672316-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible microchip,sam9x7-wdt to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v4: - Removed unnecessary '-items' from the syntax - Changed enum as const as per the comment --- .../bindings/watchdog/atmel,sama5d4-wdt.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.y= aml b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml index 816f85ee2c77..cdf87db36183 100644 --- a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml @@ -14,10 +14,14 @@ allOf: =20 properties: compatible: - enum: - - atmel,sama5d4-wdt - - microchip,sam9x60-wdt - - microchip,sama7g5-wdt + oneOf: + - enum: + - atmel,sama5d4-wdt + - microchip,sam9x60-wdt + - microchip,sama7g5-wdt + - items: + - const: microchip,sam9x7-wdt + - const: microchip,sam9x60-wdt =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48D2712DD86; Fri, 23 Feb 2024 17:27:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709228; cv=none; b=XxpX84VgcX9EnpMtaoOJKYY9C/QACei05dx/2toOrqDFQTwPQ8m/3xOnlKSRSfyP8Q6CJOs2Rw1JI4xNYLw/DT3L6Iwk+/gLddlPI1evwf5o2w/9QCUVDr/63Sux+m5Z1cYTu1uNKnHHh/1/DN0JMIFv2TIVaRyU1+JS8lhtGkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709228; c=relaxed/simple; bh=hA6t0dUmMpp366ADXyoHTsVlJuJfCOs9fFBiMBv3M+4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oy8/nn8WMrMiQ1Ca7Dy0zsuZiGi8uzE/1Cs3HQ0r4CAw/mNjdUP4gB+JYbghX6L/6naBzQMvqQfEL6CJ2wNRtKZj9Ad/h1lyPt3YBX8Mml77MPRE8TvlWpDJShJgHHHteRx6CevX9ncIDaz4B8MG1H8TVsTMDcZ6M0/TH2WTJXE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=sh/bG1Q8; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sh/bG1Q8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709227; x=1740245227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hA6t0dUmMpp366ADXyoHTsVlJuJfCOs9fFBiMBv3M+4=; b=sh/bG1Q8tLE8/pAwY0b9QFMMq7W3hUWGOpTkvzFh8IcLe1DG0MYvOnoT l6k4HrvIu11HWIqZRa+Q3zh/Xim1AoLsYF8M2sRWdLAqPRPsY2ECkZ1Ig Gz57Sq0k3RWrxfRnA0QzAr09POXduFz8/zbyK4BN7EUP9uNkjV4FCdaj6 hAslFH8EuAqs9/31kUki/sl8KXVWfwaJEvLadq7rmWBtGg3hWdUd2bN0O EBS3t94RkjFyKVdIVCUi8GQ0EliVssTu026mKypqA1K36f9xVpE+7s11R ryDhTXHK/nm/MPQ9dP6UJKX+yS121xlDNLc4Y0m0M0fZjIg94D+GlXZPY g==; X-CSE-ConnectionGUID: O9nSenaIQFe/RJGNzUZuEw== X-CSE-MsgGUID: 5IlSLmlrTv6CGNoCqJRYVg== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16735880" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:27:06 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:26:56 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:26:51 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: Subject: [PATCH v4 16/39] spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list Date: Fri, 23 Feb 2024 22:56:38 +0530 Message-ID: <20240223172638.672366-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove microchip,sam9x60-spi compatible from the list as the driver used has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the same compatible as fallback. So removing the microchip,sam9x60-spi compatible from the list since it is not needed. Signed-off-by: Varshini Rajendran Reviewed-by: Tudor Ambarus --- Changes in v4: - Elaborated the explanation in the commit message to justify the patch --- Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yam= l b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index 58367587bfbc..32e7c14033c2 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -22,7 +22,6 @@ properties: - const: atmel,at91rm9200-spi - items: - const: microchip,sam9x7-spi - - const: microchip,sam9x60-spi - const: atmel,at91rm9200-spi =20 reg: --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A27813DB94; Fri, 23 Feb 2024 17:27:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709235; cv=none; b=trEUg4MPcjd4fIoXuZ6SX3MAQDceR07+9zc52jBJUs0nysVZ3SK8cIYUKl2uA3ZPAgWHekxIXz/SuDRaS8cAyUlpjUIsT15Nqy/J7RzBUuyV9iFaOYCDfKaD1kcX8yoVGDOlVvMdevwwRh/s8ZKMoW80wix3odZqgmUpVpK6kpw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709235; c=relaxed/simple; bh=W5BmSshd0oXFwwOasjjhvcfbUwIqu6xmPd/ui1WyGEQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ndD06Nlf0KyMW44iShKk2via0ansYIyK8tyEJ8+guLCsjHuNBh8qsCGCUtRlIllj9D+1OZUsDpvLmNHuAHquA5wq37oapcBFq3bFR4QQFnhv3JkjaWClmJ0eBygD9IeZT02uNtbnLQktffRvcq+z4B4njB8+hlM6SK39ZDIuysU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=RYnC3Tz8; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="RYnC3Tz8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709234; x=1740245234; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=W5BmSshd0oXFwwOasjjhvcfbUwIqu6xmPd/ui1WyGEQ=; b=RYnC3Tz8YMlbxxIqaiqERWZNxpveLsY3yfsrW2EEPrWUaDcuFC1VW+Ga Y4eCPTwYzypQcRwfg9XuIXKELXWyWnJcj5q60+DJY7Hsm9ye2A+zWeASr 3lA7ZuNT+1NHu4KOKA9lp9atON4QDugOX5TkrSO21PagRw/QtwPTaJ3KU 5eFCn4U5ggRtODTFVoOkky4+t7QfsKbixkTPaaBZZVzd0lhQitV9zVHHo 0TGaou0RYpADxNf4QE9Be1CPJH0JbTVBpYSBDyTRMwmkx9+SMDTbDtlAH usXB5uFjSLrUm8hna/GtOiVLProHyJDuqKxkn4Tn2z87GqSXAcrCVGMAS g==; X-CSE-ConnectionGUID: WGdUDJySTO6s5AHkHy7fsA== X-CSE-MsgGUID: kYk6deLtTtCG69UPyi3Npw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="18276155" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:27:13 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:27:04 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:27:00 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: , Conor Dooley Subject: [PATCH v4 17/39] ASoC: dt-bindings: microchip: add sam9x7 Date: Fri, 23 Feb 2024 22:56:57 +0530 Message-ID: <20240223172657.672439-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add sam9x7 compatible in the DT documentation. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v4: - Updated Acked-by tag --- .../bindings/sound/microchip,sama7g5-i2smcc.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2sm= cc.yaml b/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.= yaml index 651f61c7c25a..fb630a184350 100644 --- a/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml @@ -24,9 +24,14 @@ properties: const: 0 =20 compatible: - enum: - - microchip,sam9x60-i2smcc - - microchip,sama7g5-i2smcc + oneOf: + - enum: + - microchip,sam9x60-i2smcc + - microchip,sama7g5-i2smcc + - items: + - enum: + - microchip,sam9x7-i2smcc + - const: microchip,sam9x60-i2smcc =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65C2913DB98 for ; Fri, 23 Feb 2024 17:27:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709236; cv=none; b=Ez1N3Z4Gv0yakR0bmucAeHNFtwu6FoMhQEK7Hex5x0w3kHrGiqqJ2sYgfk/vMjd6SBh+aho6XwULCvFOsRn9ZzdtzrJaMeeHIIYKAwv78hZrJk63VKl9IgLGpCIYvGkuen+C+AZAEGAoRvcJlNBfoe+SJhWFF5JRLYyRG2ItJ60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709236; c=relaxed/simple; bh=vvJunj56YSppCZwvuGVYQ/lD0VzVIdWbYqO/n682iDg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=p936Jg1SdZtxn0x4TiqJNROsADUVUNxKRaam7j5P/oAz++kqhjWzdWy2wa1l9Zo+lvM+5LYJVeramJqqjMULITgR+HuQQssIuauJ2trcXEBPjig9JreYiQYKGQT3Yss5I/tbvRjaHyINHFQYxrcOyNncB5Of9hhu4wxFOU/9Qek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=aU60QDsl; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aU60QDsl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709235; x=1740245235; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vvJunj56YSppCZwvuGVYQ/lD0VzVIdWbYqO/n682iDg=; b=aU60QDslGfDAICmh1NTYkD2Z1wUYK489Sy1Y7VA62KPSPkuwzLZ/xlyn I/iWUwPesuJOfdZuy9i2ZHIcnC6yM9DIvR494l5K+tjkGmEARE5P2UFFB ZyK4EMtgh/bXvLYtJTwkmOXnJIFXaE36f62zxmHvwI19+6KPj/9FXr+44 gBDW/yI2Y/PkJjaXh2aZGX5BqRPpjTp8zqqtOwKYhogQh8xsc0HV4RBDf lx3F+Lkg9BxOQHEMXiN3TPyl1eC3CRdDiau6vQde+g+W1yVHPsTrQzho6 eHKGUW3AkWGyHWkbungymKeFFL12pqReppATmGwyXCbwH3giFlhFUYukg A==; X-CSE-ConnectionGUID: WGdUDJySTO6s5AHkHy7fsA== X-CSE-MsgGUID: gWYSPU5eRWi9MtFedH5gFw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="18276165" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:27:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:27:12 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:27:09 -0700 From: Varshini Rajendran To: , , , , , CC: , Claudiu Beznea Subject: [PATCH v4 18/39] ARM: at91: pm: add support for sam9x7 SoC family Date: Fri, 23 Feb 2024 22:57:05 +0530 Message-ID: <20240223172705.672488-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support and pm init config for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/mach-at91/generic.h | 2 ++ arch/arm/mach-at91/pm.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0c3960a8b3eb..acf0b3c82a30 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -12,6 +12,7 @@ extern void __init at91rm9200_pm_init(void); extern void __init at91sam9_pm_init(void); extern void __init sam9x60_pm_init(void); +extern void __init sam9x7_pm_init(void); extern void __init sama5_pm_init(void); extern void __init sama5d2_pm_init(void); extern void __init sama7_pm_init(void); @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void); static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { } static inline void __init sam9x60_pm_init(void) { } +static inline void __init sam9x7_pm_init(void) { } static inline void __init sama5_pm_init(void) { } static inline void __init sama5d2_pm_init(void) { } static inline void __init sama7_pm_init(void) { } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 345b91dc6627..b81556387aa3 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -233,6 +233,17 @@ static const struct of_device_id sama7g5_ws_ids[] =3D { { /* sentinel */ } }; =20 +static const struct of_device_id sam9x7_ws_ids[] =3D { + { .compatible =3D "microchip,sam9x60-rtc", .data =3D &ws_info[1] }, + { .compatible =3D "atmel,at91rm9200-ohci", .data =3D &ws_info[2] }, + { .compatible =3D "usb-ohci", .data =3D &ws_info[2] }, + { .compatible =3D "atmel,at91sam9g45-ehci", .data =3D &ws_info[2] }, + { .compatible =3D "usb-ehci", .data =3D &ws_info[2] }, + { .compatible =3D "microchip,sam9x60-rtt", .data =3D &ws_info[4] }, + { .compatible =3D "microchip,sam9x7-gem", .data =3D &ws_info[5] }, + { /* sentinel */ } +}; + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -1135,6 +1146,7 @@ static const struct of_device_id gmac_ids[] __initcon= st =3D { { .compatible =3D "atmel,sama5d2-gem" }, { .compatible =3D "atmel,sama5d29-gem" }, { .compatible =3D "microchip,sama7g5-gem" }, + { .compatible =3D "microchip,sam9x7-gem" }, { }, }; =20 @@ -1362,6 +1374,7 @@ static const struct of_device_id atmel_pmc_ids[] __in= itconst =3D { { .compatible =3D "atmel,sama5d2-pmc", .data =3D &pmc_infos[1] }, { .compatible =3D "microchip,sam9x60-pmc", .data =3D &pmc_infos[4] }, { .compatible =3D "microchip,sama7g5-pmc", .data =3D &pmc_infos[5] }, + { .compatible =3D "microchip,sam9x7-pmc", .data =3D &pmc_infos[4] }, { /* sentinel */ }, }; =20 @@ -1499,6 +1512,28 @@ void __init sam9x60_pm_init(void) soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; } =20 +void __init sam9x7_pm_init(void) +{ + static const int modes[] __initconst =3D { + AT91_PM_STANDBY, AT91_PM_ULP0, + }; + + int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAM9X7)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + ret =3D at91_dt_ramc(false); + if (ret) + return; + + at91_pm_init(NULL); + + soc_pm.ws_ids =3D sam9x7_ws_ids; + soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; +} + void __init at91sam9_pm_init(void) { int ret; --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B50DE13F00A for ; Fri, 23 Feb 2024 17:27:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; 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charset="utf-8" Add SoC init config for sam9x7 family. Signed-off-by: Varshini Rajendran --- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm/mach-at91/sam9x7.c diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 794bd12ab0a8..7d8a7bc44e65 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_AT91RM9200) +=3D at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5) +=3D sama5.o sam_secure.o obj-$(CONFIG_SOC_SAMA7) +=3D sama7.o obj-$(CONFIG_SOC_SAMV7) +=3D samv7.o diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c new file mode 100644 index 000000000000..d998fb327860 --- /dev/null +++ b/arch/arm/mach-at91/sam9x7.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Setup code for SAM9X7. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include + +#include +#include + +#include "generic.h" + +static void __init sam9x7_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); 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Fri, 23 Feb 2024 10:27:31 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:27:28 -0700 From: Varshini Rajendran To: , , , , , CC: Claudiu Beznea Subject: [PATCH v4 20/39] ARM: at91: add support in SoC driver for new sam9x7 Date: Fri, 23 Feb 2024 22:57:22 +0530 Message-ID: <20240223172722.672592-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for SAM9X7 SoC in the SoC driver. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v4: - Sorted the entries alphabetically as per comment from Claudiu - Updated EXID Note: Did not remove the Reviewed-by tag since the changes were only cosmetic and did not affect functionality --- drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++ drivers/soc/atmel/soc.h | 9 +++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index cc9a3e107479..cae3452cbc60 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst =3D { AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH, "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif +#ifdef CONFIG_SOC_SAM9X7 + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH, + "sam9x72", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH, + "sam9x70", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 1Gb DDR3L SiP ", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 512Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 128Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 2Gb DDR3L SiP", "sam9x7"), +#endif #ifdef CONFIG_SOC_SAMA5 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 7a9f47ce85fb..fc4157c5f6e3 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 +#define SAM9X7_CIDR_MATCH 0x09750020 #define SAMA7G5_CIDR_MATCH 0x00162100 =20 #define AT91SAM9M11_EXID_MATCH 0x00000001 @@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs); #define SAMA7G54_D2G_EXID_MATCH 0x00000020 #define SAMA7G54_D4G_EXID_MATCH 0x00000028 =20 +#define SAM9X70_EXID_MATCH 0x00000005 +#define SAM9X72_EXID_MATCH 0x00000004 +#define SAM9X75_D1G_EXID_MATCH 0x00000018 +#define SAM9X75_D2G_EXID_MATCH 0x00000020 +#define SAM9X75_D1M_EXID_MATCH 0x00000003 +#define SAM9X75_D5M_EXID_MATCH 0x00000010 +#define SAM9X75_EXID_MATCH 0x00000000 + #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D40612BF0E; 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charset="utf-8" Add bindings for SAM9X7's slow clock controller. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v4: - Added sam9x7 compatible as an enum with sama7g5 compatible as per the review comment --- .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.= yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml index 7be29877e6d2..ab81f0b55ad5 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml @@ -18,7 +18,9 @@ properties: - atmel,sama5d4-sckc - microchip,sam9x60-sckc - items: - - const: microchip,sama7g5-sckc + - enum: + - microchip,sama7g5-sckc + - microchip,sam9x7-sckc - const: microchip,sam9x60-sckc =20 reg: --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CA571493B7; Fri, 23 Feb 2024 17:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709289; cv=none; b=W3RY7/taMwuVLwbjMyIEzQCOkDlRb4LUtmwlmufxvjD4gDvrWIaZohmmHeaI7B87JtbF8p5+NhUXZFnoauAQJWQ6LUVL80N2+3wrV7dyxxKUuVQ0GM75/kMnUWRsbUUq991B1INZkPu+mUZagr+K88GhJf/zbBi16m6Qz1TMw3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709289; c=relaxed/simple; bh=v/5m3gxNBQBjk0zVfGu5YA/YA0U+1V5LTugMoezBWKk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k8X78jYCiPCNnXgfspL4pgfshDIHMuUDqvQtPODG/6mSmh1+iV6AiQY95IxDmhh7a5dn6K2ym/4CAyaTwp70mghkAi5vkdAGCvNQVlC6zHe2Guc07mRgw/Ns4bEpzFTcEULpDXmSTTDL4/kddqZJcULHKV7l1KF/EnudD4IlxWQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=J9Yrq5UH; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="J9Yrq5UH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709287; x=1740245287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v/5m3gxNBQBjk0zVfGu5YA/YA0U+1V5LTugMoezBWKk=; b=J9Yrq5UHM6eo4FVcTDMrv/+OHaep76aBtDSJMpS1PAPa+ug6f9OjVDxN NSTJBoYdWqn3gDOSIwAAV0UwxzheLbQ0q5o7Pst10a6VaP8HB+KMQudN0 Ua95YovUoxfnkJAmg8R5tM8i4vDEcawQSI9izcIQiVxf4ZJozUSzCBXN9 +v4WT5lIlhDYrJUzWVzvEql3QFf+rI4K4vRA/5yfJ6G+9vxtX8GKtQTdg 64bEXLEqtNqhCFXHlWDAbP7BgcjUcAe7PiDN8GcVfRPTrIFD2fJCuEvSK QSoIzYVWBSMhXmkj9FKLEku6i3soBLwHJ6liMiqy691d656bqWWyBFS3v w==; X-CSE-ConnectionGUID: gJ/sK2wtS+eZoePf6d6/6g== X-CSE-MsgGUID: R00U9T/jS7S9AbeocYJ/Mw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="17267306" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:28:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:27:50 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:27:45 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: Subject: [PATCH v4 22/39] dt-bindings: clk: at91: add sam9x7 clock controller Date: Fri, 23 Feb 2024 22:57:41 +0530 Message-ID: <20240223172741.672694-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for SAM9X7's pmc. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v4: - Added the sam9x7 compatible in the allOf section --- .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.y= aml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml index c1bdcd9058ed..eb5cd33ea9aa 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -43,6 +43,7 @@ properties: - atmel,sama5d4-pmc - microchip,sam9x60-pmc - microchip,sama7g5-pmc + - microchip,sam9x7-pmc - const: syscon =20 reg: @@ -89,6 +90,7 @@ allOf: enum: - microchip,sam9x60-pmc - microchip,sama7g5-pmc + - microchip,sam9x7-pmc then: properties: clocks: --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52B9A14038B; Fri, 23 Feb 2024 17:28:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709284; cv=none; b=VM1SuMJKhRs0whE76FDrf1HfVsY2SZmZ/joSx3EK/Yur6O1SutNBhtvlmt3u/BLQFzcsWt5VYxPqkCZbhxRVfFFo65DpUOveZ5lp3OodCop9p1jimZk8aW065Ub6BjA9679XIjpBg5Ob0krkpdx/9KAlDpSzU8PGEP+8onJqka8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709284; c=relaxed/simple; bh=yupO65VLUPyZffIc75hdCj1FpXzK+t+KpMhOK2JtQgw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Xb6Tg6UbsPXtYJJUWPLNeqB0agbuLG+dAP0NCuNicA5g49sghctCRG5qBgiwFyZhcnX8fCydr5E4n/4rY2zOPagJxpw/KmKGS+2U+8UUt+CwuocFAClWaJLZKe6YQDbsD/Fu9ugaFV0vajwRf4tNYOjU7JGkvRmltLUJHKv4zzM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=MH7jswrV; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MH7jswrV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709284; x=1740245284; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=yupO65VLUPyZffIc75hdCj1FpXzK+t+KpMhOK2JtQgw=; b=MH7jswrVEqN7tQc8PPp5bQQ4G3N/lIvp24NOCSpMe+JgRlm+o6FHqXBG qtl5CJVCZQVSeOdi6DcUxZdg6GiokdlYpN5i7fFIrBGH5JqH0Vh15RxEi rWYXqUImk1sWMqxNvpRTxXc9vaDrsyx5fdHQ3b0sTqzOx9nycFbbbwudb nBb1hMhD484DOWziLl1PVnx8sR9sf2aYYHuiY+FbmYxZ6clWCcaz8DynB yhhj70MTr3ViwJoNW0b0CLACnfjGlCiL6KbK+q9T+fi3wsUh7BWOeK8xf XoiW9d4Ew12/MFu14329bwbFfL9e5XNpaBRKPby6NRhcUHnXmpW7nz6L5 g==; X-CSE-ConnectionGUID: WzguBkY0SsGpaivpulpMAQ== X-CSE-MsgGUID: 01HdqTC8RxaYHJnOy1s4/Q== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="247481533" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:28:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:27:57 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:27:53 -0700 From: Varshini Rajendran To: , , , , , , , , , Subject: [PATCH v4 23/39] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Date: Fri, 23 Feb 2024 22:57:50 +0530 Message-ID: <20240223172750.672745-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SAM9X7 SoC family supports different core output frequencies for different PLL IDs. To handle the same in the PLL driver, a separate parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers are aligned to the PLL driver by adding the core output freq range in the PLL characteristics configurations. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------ drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sam9x60.c | 7 +++++++ drivers/clk/at91/sama7g5.c | 7 +++++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index ff65f7b916f0..b0314dfd7393 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -23,9 +23,6 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) =20 -#define FCORE_MIN (600000000) -#define FCORE_MAX (1200000000) - #define PLL_MAX_ID 7 =20 struct sam9x60_pll_core { @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, unsigned long nmul =3D 0; unsigned long nfrac =3D 0; =20 - if (rate < FCORE_MIN || rate > FCORE_MAX) + if (rate < core->characteristics->core_output[0].min || + rate > core->characteristics->core_output[0].max) return -ERANGE; =20 /* @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, } =20 /* Check if resulted rate is a valid. */ - if (tmprate < FCORE_MIN || tmprate > FCORE_MAX) + if (tmprate < core->characteristics->core_output[0].min || + tmprate > core->characteristics->core_output[0].max) return -ERANGE; =20 if (update) { @@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, goto free; } =20 - ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, + ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, + characteristics->core_output[0].min, parent_rate, true); if (ret < 0) { hw =3D ERR_PTR(ret); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0f52e80bcd49..bb9da35198d9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -75,6 +75,7 @@ struct clk_pll_characteristics { struct clk_range input; int num_output; const struct clk_range *output; + const struct clk_range *core_output; u16 *icpll; u8 *out; u8 upll : 1; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index e309cbf3cb9a..db6db9e2073e 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] =3D { { .min =3D 2343750, .max =3D 1200000000 }, }; =20 +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + static const struct clk_pll_characteristics plla_characteristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(plla_outputs), .output =3D plla_outputs, + .core_output =3D core_outputs, }; =20 static const struct clk_range upll_outputs[] =3D { @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characte= ristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(upll_outputs), .output =3D upll_outputs, + .core_output =3D core_outputs, .upll =3D true, }; =20 diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 91b5c6f14819..e6eb5afba93d 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -116,11 +116,17 @@ static const struct clk_range pll_outputs[] =3D { { .min =3D 2343750, .max =3D 1200000000 }, }; =20 +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + /* CPU PLL characteristics. */ static const struct clk_pll_characteristics cpu_pll_characteristics =3D { .input =3D { .min =3D 12000000, .max =3D 50000000 }, .num_output =3D ARRAY_SIZE(cpu_pll_outputs), .output =3D cpu_pll_outputs, + .core_output =3D core_outputs, }; =20 /* PLL characteristics. */ @@ -128,6 +134,7 @@ static const struct clk_pll_characteristics pll_charact= eristics =3D { .input =3D { .min =3D 12000000, .max =3D 50000000 }, .num_output =3D ARRAY_SIZE(pll_outputs), .output =3D pll_outputs, + .core_output =3D core_outputs, }; =20 /* --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CF96140398; 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charset="utf-8" Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and 4 respectively, both have a hardware divider /2. This has to taken into account in the software to obtain the right frequencies. Support for the same is added in the PLL driver. fcorepllack -----> HW Div =3D 2 -+--> fpllack | +--> HW Div =3D 2 ---> fplladiv2ck In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz after the hardware divider and the plladiv2 freq is 400 MHz after the hardware divider (Given that the DIVPMC is 0). Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++---- drivers/clk/at91/pmc.h | 1 + 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index b0314dfd7393..1f80759309c0 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct= clk_hw *hw, { struct sam9x60_pll_core *core =3D to_sam9x60_pll_core(hw); struct sam9x60_frac *frac =3D to_sam9x60_frac(core); + unsigned long freq; =20 - return parent_rate * (frac->mul + 1) + + freq =3D parent_rate * (frac->mul + 1) + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + + if (core->layout->div2) + freq >>=3D 1; + + return freq; } =20 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struc= t clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); } =20 +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate >> 1; +} + static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = =3D { .restore_context =3D sam9x60_div_pll_restore_context, }; =20 +static const struct clk_ops sam9x60_fixed_div_pll_ops =3D { + .prepare =3D sam9x60_div_pll_prepare, + .unprepare =3D sam9x60_div_pll_unprepare, + .is_prepared =3D sam9x60_div_pll_is_prepared, + .recalc_rate =3D sam9x60_fixed_div_pll_recalc_rate, + .round_rate =3D sam9x60_div_pll_round_rate, + .save_context =3D sam9x60_div_pll_save_context, + .restore_context =3D sam9x60_div_pll_restore_context, +}; + struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, @@ -725,10 +747,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, s= pinlock_t *lock, else init.parent_names =3D &parent_name; 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charset="utf-8" Move the mux table init and fill macro function definitions from the sama7g5 pmc driver to the pmc.h header file since they will be used by other SoC's pmc drivers as well like sam9x7. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/pmc.h | 16 ++++++++++++++++ drivers/clk/at91/sama7g5.c | 35 ++++++++++------------------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 91d1c6305d95..4fb29ca111f7 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -121,6 +121,22 @@ struct at91_clk_pms { =20 #define ndck(a, s) (a[s - 1].id + 1) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) + +#define PMC_INIT_TABLE(_table, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) \ + (_table)[_i] =3D _i; \ + } while (0) + +#define PMC_FILL_TABLE(_to, _from, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) { \ + (_to)[_i] =3D (_from)[_i]; \ + } \ + } while (0) + struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsyste= m, unsigned int nperiph, unsigned int ngck, unsigned int npck); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index e6eb5afba93d..6706d1305baa 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -16,21 +16,6 @@ =20 #include "pmc.h" =20 -#define SAMA7G5_INIT_TABLE(_table, _count) \ - do { \ - u8 _i; \ - for (_i =3D 0; _i < (_count); _i++) \ - (_table)[_i] =3D _i; \ - } while (0) - -#define SAMA7G5_FILL_TABLE(_to, _from, _count) \ - do { \ - u8 _i; \ - for (_i =3D 0; _i < (_count); _i++) { \ - (_to)[_i] =3D (_from)[_i]; \ - } \ - } while (0) - static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); @@ -1119,17 +1104,17 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) if (!mux_table) goto err_free; =20 - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, - sama7g5_mckx[i].ep_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, + sama7g5_mckx[i].ep_count); for (j =3D 0; j < sama7g5_mckx[i].ep_count; j++) { u8 pll_id =3D sama7g5_mckx[i].ep[j].pll_id; u8 pll_compid =3D sama7g5_mckx[i].ep[j].pll_compid; =20 tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; } - SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_mckx[i].ep_count); + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, + sama7g5_mckx[i].ep_count); =20 hw =3D at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, num_parents, NULL, parent_hws, mux_table, @@ -1215,17 +1200,17 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) if (!mux_table) goto err_free; =20 - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, - sama7g5_gck[i].pp_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, + sama7g5_gck[i].pp_count); for (j =3D 0; j < sama7g5_gck[i].pp_count; j++) { u8 pll_id =3D sama7g5_gck[i].pp[j].pll_id; u8 pll_compid =3D sama7g5_gck[i].pp[j].pll_compid; =20 tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; } - SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_gck[i].pp_count); + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, + sama7g5_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 023A312DD85; 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charset="utf-8" Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT for sam9x7 SoC family. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- include/dt-bindings/clock/at91.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/a= t91.h index 3e3972a814c1..6ede88c3992d 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -38,6 +38,10 @@ #define PMC_CPU (PMC_MAIN + 9) #define PMC_MCK1 (PMC_MAIN + 10) =20 +/* SAM9X7 */ +#define PMC_PLLADIV2 (PMC_MAIN + 11) +#define PMC_LVDSPLL (PMC_MAIN + 12) + #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB13613328D; Fri, 23 Feb 2024 17:29:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709354; cv=none; b=m8t8tH47GaWbqUhWq3Nqn7nhr/SjfLNJKeg8pOAB6muKi6Z4e10cr3JqiWaP9J3GVQLAUZq3BLjFt6cjrMgk3o4g3PfiS1xizltQwaZa8qTUdufELTFP5vTojfEo520GvkMQDSrKRQaJRYlF7Ll5zPiZlDDe7bn3hHMjkqpnmDA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709354; c=relaxed/simple; bh=qUjC9nN9kQ1T5M7faTRpAo+kExIIM7FluBdFFo3d07M=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cI8/SGbQcxdwCM4+uAJXuP0HO9UuzsGZaeYjRAg6HYupXnbsgoIj9jrTmRUMYxNLj4rkD1biW/WPgYQZfY/WypWMiaSFFs6LpGK4WLFpn4Py6Tup0mS4/SON+4B6fImyuXpwzcNMQpUCBiyGiYZ/8Pz+AVZxKNPfvzWE/HiuX9U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=1Pe1k/s6; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="1Pe1k/s6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709352; x=1740245352; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=qUjC9nN9kQ1T5M7faTRpAo+kExIIM7FluBdFFo3d07M=; b=1Pe1k/s6TdMGj/ahLfdLcvbFCUOGPYBLOFMmhr7RON3FTL/OvJ9IU4MQ vc5BYaQHETT6gi1bEEs11wNHyJCNhUKkrpu9Wa+t/eNBjJWNWE03gWp7W /AUyEgl0tuhs+eBpGQRAozZREQHxXh1ZIXx7s9JVHWaBBZsFNWR3RMQym 00p9QoxpHVv2SANl3QW60KYWJlJiT3Z6ZQTndlHr+Zm19xM8Pv4x3qvBF Lflxpmyxo/RaQ5bmzlQ1LLyFEnSfVPqBLDjFpf5DiptanZEqgCjBe9CaQ dN9BksPtbSA9XmlLCiXBoiS//+5vv7Cfule+OMJl2/KcE524+lLf+s868 A==; X-CSE-ConnectionGUID: nX+aFf6zR2a6Qs8N2xdKug== X-CSE-MsgGUID: E2gJ9OhwQiaslw2mQrOxpw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="18276335" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:29:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:28:54 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:28:51 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v4 27/39] clk: at91: sam9x7: add sam9x7 pmc driver Date: Fri, 23 Feb 2024 22:58:31 +0530 Message-ID: <20240223172831.672953-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a driver for the PMC clocks of sam9x7 Soc family. Signed-off-by: Varshini Rajendran --- Changes in v4: - Changed variable name alloc_mem to clk_mux_buffer to be more suggestive - Changed description of @f structure member appropriately --- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 947 insertions(+) create mode 100644 drivers/clk/at91/sam9x7.c diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 89061b85e7d2..8e3684ba2c74 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9260.o at91sam9rl.= o at91sam9x5.o dt-compat. obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9g45.o dt-compat.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9n12.o at91sam9x5.o dt-compat.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5D3) +=3D sama5d3.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D4) +=3D sama5d4.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D2) +=3D sama5d2.o dt-compat.o diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c new file mode 100644 index 000000000000..d03387d2e35a --- /dev/null +++ b/drivers/clk/at91/sam9x7.c @@ -0,0 +1,946 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAM9X7 PMC code. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + * + */ +#include +#include +#include +#include + +#include + +#include "pmc.h" + +static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(mck_lock); + +/** + * enum pll_ids - PLL clocks identifiers + * @PLL_ID_PLLA: PLLA identifier + * @PLL_ID_UPLL: UPLL identifier + * @PLL_ID_AUDIO: Audio PLL identifier + * @PLL_ID_LVDS: LVDS PLL identifier + * @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier + * @PLL_ID_MAX: Max PLL Identifier + */ +enum pll_ids { + PLL_ID_PLLA, + PLL_ID_UPLL, + PLL_ID_AUDIO, + PLL_ID_LVDS, + PLL_ID_PLLA_DIV2, + PLL_ID_MAX, +}; + +/** + * enum pll_type - PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +static const struct clk_master_characteristics mck_characteristics =3D { + .output =3D { .min =3D 32000000, .max =3D 266666667 }, + .divisors =3D { 1, 2, 4, 3, 5}, + .have_div3_pres =3D 1, +}; + +static const struct clk_master_layout sam9x7_master_layout =3D { + .mask =3D 0x373, + .pres_shift =3D 4, + .offset =3D 0x28, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range plla_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +static const struct clk_range upll_core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + +static const struct clk_range lvdspll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +/* Fractional PLL output range. */ +static const struct clk_range plla_outputs[] =3D { + { .min =3D 732421, .max =3D 800000000 }, +}; + +static const struct clk_range upll_outputs[] =3D { + { .min =3D 300000000, .max =3D 600000000 }, +}; + +static const struct clk_range lvdspll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_outputs[] =3D { + { .min =3D 366210, .max =3D 400000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics plla_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plla_outputs), + .output =3D plla_outputs, + .core_output =3D plla_core_outputs, +}; + +static const struct clk_pll_characteristics upll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(upll_outputs), + .output =3D upll_outputs, + .core_output =3D upll_core_outputs, + .upll =3D true, +}; + +static const struct clk_pll_characteristics lvdspll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(lvdspll_outputs), + .output =3D lvdspll_outputs, + .core_output =3D lvdspll_core_outputs, +}; + +static const struct clk_pll_characteristics audiopll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(audiopll_outputs), + .output =3D audiopll_outputs, + .core_output =3D audiopll_core_outputs, +}; + +static const struct clk_pll_characteristics plladiv2_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plladiv2_outputs), + .output =3D plladiv2_outputs, + .core_output =3D plladiv2_core_outputs, +}; + +/* Layout for fractional PLL ID PLLA. */ +static const struct clk_pll_layout plla_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, + .div2 =3D 1, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, +}; + +/* Layout for DIV PLLs. */ +static const struct clk_pll_layout pll_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, +}; + +/* Layout for DIV PLL ID PLLADIV2. */ +static const struct clk_pll_layout plladiv2_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, + .div2 =3D 1, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_divio_layout =3D { + .div_mask =3D GENMASK(19, 12), + .endiv_mask =3D BIT(30), + .div_shift =3D 12, + .endiv_shift =3D 30, +}; + +/* + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: pll characteristics + * @f: clock flags + * @eid: export index in sam9x7->chws[] array + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + const struct clk_pll_characteristics *c; + unsigned long f; + u8 eid; +} sam9x7_plls[][PLL_ID_MAX] =3D { + [PLL_ID_PLLA] =3D { + { + .n =3D "plla_fracck", + .p =3D "mainck", + .l =3D &plla_frac_layout, + .t =3D PLL_TYPE_FRAC, + /* + * This feeds plla_divpmcck which feeds CPU. It should + * not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plla_characteristics, + }, + + { + .n =3D "plla_divpmcck", + .p =3D "plla_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .eid =3D PMC_PLLACK, + .c =3D &plla_characteristics, + }, + }, + + [PLL_ID_UPLL] =3D { + { + .n =3D "upll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .t =3D PLL_TYPE_FRAC, + .f =3D CLK_SET_RATE_GATE, + .c =3D &upll_characteristics, + }, + + { + .n =3D "upll_divpmcck", + .p =3D "upll_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .eid =3D PMC_UTMI, + .c =3D &upll_characteristics, + }, + }, + + [PLL_ID_AUDIO] =3D { + { + .n =3D "audiopll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &audiopll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "audiopll_divpmcck", + .p =3D "audiopll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .eid =3D PMC_AUDIOPMCPLL, + .t =3D PLL_TYPE_DIV, + }, + + { + .n =3D "audiopll_diviock", + .p =3D "audiopll_fracck", + .l =3D &pll_divio_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .eid =3D PMC_AUDIOIOPLL, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_LVDS] =3D { + { + .n =3D "lvdspll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &lvdspll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "lvdspll_divpmcck", + .p =3D "lvdspll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &lvdspll_characteristics, + .eid =3D PMC_LVDSPLL, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_PLLA_DIV2] =3D { + { + .n =3D "plla_div2pmcck", + .p =3D "plla_fracck", + .l =3D &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plladiv2_characteristics, + .eid =3D PMC_PLLADIV2, + .t =3D PLL_TYPE_DIV, + }, + }, +}; + +static const struct clk_programmable_layout sam9x7_programmable_layout =3D= { + .pres_mask =3D 0xff, + .pres_shift =3D 8, + .css_mask =3D 0x1f, + .have_slck_mck =3D 0, + .is_pres_direct =3D 1, +}; + +static const struct clk_pcr_layout sam9x7_pcr_layout =3D { + .offset =3D 0x88, + .cmd =3D BIT(31), + .gckcss_mask =3D GENMASK(12, 8), + .pid_mask =3D GENMASK(6, 0), +}; + +static const struct { + char *n; + char *p; + u8 id; + unsigned long flags; +} sam9x7_systemck[] =3D { + /* + * ddrck feeds DDR controller and is enabled by bootloader thus we need + * to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, + { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, + { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, + { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, +}; + +/* + * Peripheral clocks description + * @n: clock name + * @f: clock flags + * @id: peripheral id + */ +static const struct { + char *n; + unsigned long f; + u8 id; +} sam9x7_periphck[] =3D { + { .n =3D "pioA_clk", .id =3D 2, }, + { .n =3D "pioB_clk", .id =3D 3, }, + { .n =3D "pioC_clk", .id =3D 4, }, + { .n =3D "flex0_clk", .id =3D 5, }, + { .n =3D "flex1_clk", .id =3D 6, }, + { .n =3D "flex2_clk", .id =3D 7, }, + { .n =3D "flex3_clk", .id =3D 8, }, + { .n =3D "flex6_clk", .id =3D 9, }, + { .n =3D "flex7_clk", .id =3D 10, }, + { .n =3D "flex8_clk", .id =3D 11, }, + { .n =3D "sdmmc0_clk", .id =3D 12, }, + { .n =3D "flex4_clk", .id =3D 13, }, + { .n =3D "flex5_clk", .id =3D 14, }, + { .n =3D "flex9_clk", .id =3D 15, }, + { .n =3D "flex10_clk", .id =3D 16, }, + { .n =3D "tcb0_clk", .id =3D 17, }, + { .n =3D "pwm_clk", .id =3D 18, }, + { .n =3D "adc_clk", .id =3D 19, }, + { .n =3D "dma0_clk", .id =3D 20, }, + { .n =3D "uhphs_clk", .id =3D 22, }, + { .n =3D "udphs_clk", .id =3D 23, }, + { .n =3D "macb0_clk", .id =3D 24, }, + { .n =3D "lcd_clk", .id =3D 25, }, + { .n =3D "sdmmc1_clk", .id =3D 26, }, + { .n =3D "ssc_clk", .id =3D 28, }, + { .n =3D "can0_clk", .id =3D 29, }, + { .n =3D "can1_clk", .id =3D 30, }, + { .n =3D "flex11_clk", .id =3D 32, }, + { .n =3D "flex12_clk", .id =3D 33, }, + { .n =3D "i2s_clk", .id =3D 34, }, + { .n =3D "qspi_clk", .id =3D 35, }, + { .n =3D "gfx2d_clk", .id =3D 36, }, + { .n =3D "pit64b0_clk", .id =3D 37, }, + { .n =3D "trng_clk", .id =3D 38, }, + { .n =3D "aes_clk", .id =3D 39, }, + { .n =3D "tdes_clk", .id =3D 40, }, + { .n =3D "sha_clk", .id =3D 41, }, + { .n =3D "classd_clk", .id =3D 42, }, + { .n =3D "isi_clk", .id =3D 43, }, + { .n =3D "pioD_clk", .id =3D 44, }, + { .n =3D "tcb1_clk", .id =3D 45, }, + { .n =3D "dbgu_clk", .id =3D 47, }, + /* + * mpddr_clk feeds DDR controller and is enabled by bootloader thus we + * need to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "mpddr_clk", .id =3D 49, .f =3D CLK_IS_CRITICAL }, + { .n =3D "csi2dc_clk", .id =3D 52, }, + { .n =3D "csi4l_clk", .id =3D 53, }, + { .n =3D "dsi4l_clk", .id =3D 54, }, + { .n =3D "lvdsc_clk", .id =3D 56, }, + { .n =3D "pit64b1_clk", .id =3D 58, }, + { .n =3D "puf_clk", .id =3D 59, }, + { .n =3D "gmactsu_clk", .id =3D 67, }, +}; + +/* + * Generic clock description + * @n: clock name + * @pp: PLL parents + * @pp_mux_table: PLL parents mux table + * @r: clock output range + * @pp_chg_id: id in parent array of changeable PLL parent + * @pp_count: PLL parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *pp[8]; + const char pp_mux_table[8]; + struct clk_range r; + int pp_chg_id; + u8 pp_count; + u8 id; +} sam9x7_gck[] =3D { + { + .n =3D "flex0_gclk", + .id =3D 5, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex1_gclk", + .id =3D 6, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex2_gclk", + .id =3D 7, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex3_gclk", + .id =3D 8, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex6_gclk", + .id =3D 9, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex7_gclk", + .id =3D 10, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex8_gclk", + .id =3D 11, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc0_gclk", + .id =3D 12, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex4_gclk", + .id =3D 13, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex5_gclk", + .id =3D 14, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex9_gclk", + .id =3D 15, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex10_gclk", + .id =3D 16, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb0_gclk", + .id =3D 17, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "adc_gclk", + .id =3D 19, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "lcd_gclk", + .id =3D 25, + .r =3D { .max =3D 75000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc1_gclk", + .id =3D 26, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan0_gclk", + .id =3D 29, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan1_gclk", + .id =3D 30, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex11_gclk", + .id =3D 32, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex12_gclk", + .id =3D 33, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "i2s_gclk", + .id =3D 34, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "qspi_gclk", + .id =3D 35, + .r =3D { .max =3D 20000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b0_gclk", + .id =3D 37, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "classd_gclk", + .id =3D 42, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb1_gclk", + .id =3D 45, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "dbgu_gclk", + .id =3D 47, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mipiphy_gclk", + .id =3D 55, + .r =3D { .max =3D 27000000 }, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b1_gclk", + .id =3D 58, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "gmac_gclk", + .id =3D 67, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, +}; + +static void __init sam9x7_pmc_setup(struct device_node *np) +{ + struct clk_range range =3D CLK_RANGE(0, 0); + const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct pmc_data *sam9x7_pmc; + const char *parent_names[9]; + void **clk_mux_buffer =3D NULL; + int clk_mux_buffer_size =3D 0; + struct clk_hw *main_osc_hw; + struct regmap *regmap; + struct clk_hw *hw; + int i, j; + + i =3D of_property_match_string(np, "clock-names", "td_slck"); + if (i < 0) + return; + + td_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "md_slck"); + if (i < 0) + return; + + md_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name =3D of_clk_get_parent_name(np, i); + + regmap =3D device_node_to_regmap(np); + if (IS_ERR(regmap)) + return; + + sam9x7_pmc =3D pmc_data_allocate(PMC_LVDSPLL + 1, + nck(sam9x7_systemck), + nck(sam9x7_periphck), + nck(sam9x7_gck), 8); + if (!sam9x7_pmc) + return; + + clk_mux_buffer =3D kmalloc(sizeof(void *) * + (ARRAY_SIZE(sam9x7_gck)), + GFP_KERNEL); + if (!clk_mux_buffer) + goto err_free; + + hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); + if (IS_ERR(hw)) + goto err_free; + main_osc_hw =3D hw; + + parent_names[0] =3D "main_rc_osc"; + parent_names[1] =3D "main_osc"; + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MAIN] =3D hw; + + for (i =3D 0; i < PLL_ID_MAX; i++) { + for (j =3D 0; j < 3; j++) { + struct clk_hw *parent_hw; + + if (!sam9x7_plls[i][j].n) + continue; + + switch (sam9x7_plls[i][j].t) { + case PLL_TYPE_FRAC: + if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; + else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) + parent_hw =3D main_osc_hw; + else + parent_hw =3D __clk_get_hw(of_clk_get_by_name + (np, sam9x7_plls[i][j].p)); + + hw =3D sam9x60_clk_register_frac_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, + parent_hw, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f); + break; + + case PLL_TYPE_DIV: + hw =3D sam9x60_clk_register_div_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, NULL, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f, 0); + break; + + default: + continue; + } + + if (IS_ERR(hw)) + goto err_free; + + if (sam9x7_plls[i][j].eid) + sam9x7_pmc->chws[sam9x7_plls[i][j].eid] =3D hw; + } + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D "mainck"; + parent_names[2] =3D "plla_divpmcck"; + parent_names[3] =3D "upll_divpmcck"; + hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MCK] =3D hw; + + parent_names[0] =3D "plla_divpmcck"; + parent_names[1] =3D "upll_divpmcck"; + parent_names[2] =3D "main_osc"; + hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + parent_names[4] =3D "plla_divpmcck"; + parent_names[5] =3D "upll_divpmcck"; + parent_names[6] =3D "audiopll_divpmcck"; + for (i =3D 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw =3D at91_clk_register_programmable(regmap, name, + parent_names, NULL, 7, i, + &sam9x7_programmable_layout, + NULL); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->pchws[i] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { + hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, + sam9x7_systemck[i].p, NULL, + sam9x7_systemck[i].id, + sam9x7_systemck[i].flags); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->shws[sam9x7_systemck[i].id] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_periphck); i++) { + hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_periphck[i].n, + "masterck_div", NULL, + sam9x7_periphck[i].id, + &range, INT_MIN, + sam9x7_periphck[i].f); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { + u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; + u32 *mux_table; + + mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), + GFP_KERNEL); + if (!mux_table) + goto err_free; + + PMC_INIT_TABLE(mux_table, 4); + PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, + sam9x7_gck[i].pp_count); + PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, + sam9x7_gck[i].pp_count); + + hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_gck[i].n, + parent_names, NULL, mux_table, + num_parents, + sam9x7_gck[i].id, + &sam9x7_gck[i].r, + sam9x7_gck[i].pp_chg_id); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->ghws[sam9x7_gck[i].id] =3D hw; + clk_mux_buffer[clk_mux_buffer_size++] =3D mux_table; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); + kfree(clk_mux_buffer); + + return; + +err_free: + if (clk_mux_buffer) { + for (i =3D 0; i < clk_mux_buffer_size; i++) + kfree(clk_mux_buffer[i]); + kfree(clk_mux_buffer); + } + kfree(sam9x7_pmc); +} + +/* Some clks are used for a clocksource */ +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup); --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com 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cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:29:04 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:29:00 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v4 28/39] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Date: Fri, 23 Feb 2024 22:58:55 +0530 Message-ID: <20240223172855.673003-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 SoC family. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Changes in v4: - Updated Acked-by tag. --- .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,a= ic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.t= xt index 7079d44bf3ba..5fb9366c94a1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Should be: - "atmel,-aic" where can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - - "microchip,-aic" where can be "sam9x60" + - "microchip,-aic" where can be "sam9x60" or "sam9x7" =20 - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. It shoul= d be 3. --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8619F1420B3; Fri, 23 Feb 2024 17:29:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709363; cv=none; b=cVDoHJLMqEbNkaJYiKo5cGVnQQcV94OuXrwoWYJnYxw6E1HKCmuMj+KRg82ct/ZLWsBC4GhKN2sDWd7hlDroW3I3z1V2UMG9MclMrYsKh+AgNGkunvhnyuM4iT+g4+wZcARU7tbvGqyC4DOYbFLGR8mbdL8OGGqq1KgihzS/wdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709363; c=relaxed/simple; bh=032mMVSQqEKqmJWHEH/kd/ajYLY2Zrh+cOXnnpQqiKQ=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JqZFrADTjl8M4Yq2h4vEngS7eqZ10RV3GcKOfwObV8k1UFZapdvBrL8rB0IYwbX20nU3kEIgXkgNtlKbkikdv48lyP1wUkvIyFMtdLd2TLFDRAepPGdMk3HDOQbbSJPwCltSPN2qrLeO8u+HZb9ap2DBzoISoMAMwn6exVoTr1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=C0w9IwhP; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="C0w9IwhP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709362; x=1740245362; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=032mMVSQqEKqmJWHEH/kd/ajYLY2Zrh+cOXnnpQqiKQ=; b=C0w9IwhP1dEjGcfci+1ijL4HhXC3xCZVAi2cdQHmJ9U4yVJIVZ/wxITM nbyLSKTtuGdf5kXFOdL+aOJHbPAL/Wl/WDKXbquC/Qm7Z6W68IJds1EEN dtFMxFcAbqpCHMCyVEjBfdYUHjq+8LRCJ163pq0ElcgJNoxxNbgt26XSc qxt8307R+Ij2YDU1eT+4eBaE9OPQD3kXwu3iA9oSOkE0KT8CgwwcVlo8T W+t557TPFlxDRowQvA6C2sy4xNaKzrEPa1B3lyjWY6wMIOGdjbSUcdaO3 tDk5AQyClKzEyFxCP1LuDPBLyR1/mZQ8sGhN+Vzc83A8ORP8dsHrYAAqW g==; X-CSE-ConnectionGUID: UUhv/eVbQlm9nBTg2b0S7g== X-CSE-MsgGUID: rc+ohozORYusiT9RdenFHA== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16734688" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:29:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:29:19 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:29:14 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , Subject: [PATCH v4 29/39] irqchip/atmel-aic5: Add support to get nirqs from DT for sam9x60 & sam9x7 Date: Fri, 23 Feb 2024 22:59:05 +0530 Message-ID: <20240223172905.673053-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to get number of IRQs from the respective DT node for sam9x60 and sam9x7 devices. Since only this factor differs between the two SoCs, this patch adds support for the same. Adapt the sam9x60 dtsi accordingly. Signed-off-by: Varshini Rajendran --- Changes in v4: - Changed the implementation to fetch the NIRQs from DT as per the comment to avoid introducing a new compatible when this is the only difference between the SoCs related to this IP. --- arch/arm/boot/dts/microchip/sam9x60.dtsi | 1 + drivers/irqchip/irq-atmel-aic5.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/m= icrochip/sam9x60.dtsi index 73d570a17269..e405f68c9f54 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 { interrupt-controller; reg =3D <0xfffff100 0x100>; atmel,external-irqs =3D <31>; + microchip,nr-irqs =3D <50>; }; =20 dbgu: serial@fffff200 { diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-a= ic5.c index 145535bd7560..5d96ad8860d3 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -398,11 +398,16 @@ static int __init sama5d4_aic5_of_init(struct device_= node *node, } IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init); 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23 Feb 2024 10:29:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:29:36 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:29:32 -0700 From: Varshini Rajendran To: , , , , , , CC: , Sebastian Reichel Subject: [PATCH v4 30/39] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Date: Fri, 23 Feb 2024 22:59:20 +0530 Message-ID: <20240223172920.673110-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use sam9x7 pmc's compatible to lookup for in the SHDWC driver. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel --- Changes in v4: - Updated Acked-by tag --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset= /at91-sama5d2_shdwc.c index 959ce0dbe91d..2121d7e74e12 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] =3D { { .compatible =3D "atmel,sama5d2-pmc" }, { .compatible =3D "microchip,sam9x60-pmc" }, { .compatible =3D "microchip,sama7g5-pmc" }, + { .compatible =3D "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; =20 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84FC3143C70; Fri, 23 Feb 2024 17:30:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709441; cv=none; b=q9KDmqjU7hRH866Gf0ChWxo1vEv5dMI2tq2a50JTs2WTi3yjHnpXRzZ7AJSm4w1F/oLNes+55VBYYIjF4RC7Lcas9C+UUxqrev/lvVl5g/esikm9R2oDILjKJbBwq9uXt2CQX/Fw6UR/m5KM7zIfcxsV+PtpQCstgan9I83JAfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709441; c=relaxed/simple; bh=6yaUy0u5t4Wc+0M4Ut142hhEuqrEttKdZznrVqg+kFw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lK6R1NDWJ0zpRwD/nuMUkXqdsWyDboUYqMfbMKKGqNT2R62P6a+VOZ7HBdnq21r9Wo1qTae4S7f0AC6UMvP1JXrXfK/+S3vrPFjdjcWXzVZYHPd9eWe7o27s9yqJ/wh1CFv9DsqJG5RVmuXwtVylGzl8JJb22IcD6Xta0U8UIm8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=rd/t4PIc; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="rd/t4PIc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709440; x=1740245440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6yaUy0u5t4Wc+0M4Ut142hhEuqrEttKdZznrVqg+kFw=; b=rd/t4PIcljgpLxnMvDsyfDQZlTrjjnZP3CHan+SqZtU0G5jykf8bIMSA F6nwNx/BdDQ9nH2Fl70lwfJDn09Q8L9Q0O2PLgaAANb6acY34XGPbPmHP 2P2Ue4lVkmovQHQaElAEbRZdZ3vSWarCztT5gILc0mjfu+9Ys2GURh/sP 2McCxLunqCN56xSpxTv5eyEXQB3PE0aaI+iGMhbxQhRqod1miv3VJFJfQ 7/0aOK9c20uVmNeHYk96TMgYnqHYl2REkOyboXxxIPYsHHgoCU5nxK9ep +8w7nTB9GWZS5b7S6nOJW3Yl98RPD/spQvJDklD1Eb2ts3dFDNM3JEc2x Q==; X-CSE-ConnectionGUID: f6QG3EKtShO/OUe1NBSJ1w== X-CSE-MsgGUID: N5ToapxpR32c7ZiEAmLKug== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="184009734" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:30:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:30:09 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:30:07 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel Subject: [PATCH v4 31/39] power: reset: at91-reset: add reset support for sam9x7 SoC Date: Fri, 23 Feb 2024 22:59:37 +0530 Message-ID: <20240223172937.673163-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power reset support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel --- Changes in v4: - Updated Acked-by tag --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index fece990af4a7..e3ebebc1f80d 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF config POWER_RESET_AT91_RESET tristate "Atmel AT91 reset driver" depends on ARCH_AT91 - default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports restart for Atmel AT91SAM9 and SAMA5 SoCs --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62A8C12E1FC; Fri, 23 Feb 2024 17:30:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709425; cv=none; b=akoQnnC37qyC+tWk0beiaX9aJFxXPmZN+myURQ8x/iCcEl2a2LBZ3zsO0220jv7K/eBcRPK0az9JseA/gmGTuZTkxDYI5qaPCrezhVri/DQEhkyGhSEnyALas+yS/v2x/ZaPrIz9vMyhzgHY0oe9oO59c1cQnlhe5BSRWYiaii8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709425; c=relaxed/simple; bh=+klO3bbOdffwzhA8ixlhjvL2TDFPdKbuHLwQA3504FQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ne37Vrg8HsZKc+2K1lw8D8ygIGjCRrdTxZUQbHXMH/qMvE2CDkaSl7kTtXG9LGj04+K578f/h463cHAp4KtW+ozE8hBTKDrGG00N3pykeNiCLKGk8txjZKCP4tkEiizlI24HQm5BNkrJ73ucugi7peQE9CIhYsbRcWVNre3wCuo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=NcoGF6YI; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="NcoGF6YI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709424; x=1740245424; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+klO3bbOdffwzhA8ixlhjvL2TDFPdKbuHLwQA3504FQ=; b=NcoGF6YIhjzbSwc2KexW0EnnL9oksoVZAStGbJJj0maluxFOsGUaOpFG RrOvWOQ9gEub66k+vHXk0IoBIHogpsIdltjIHxpEXpahfMVrAuNgmzeEx JipQwxAIgzb9TsmAyMO3CKk/xBGQft55TWFZTptYP0WNXqCpo2+4429wk 8QL+QpkZS6LbUdM69BCW+lcCiI/dnVfD0BIIMNlRvWZkmlVjVodr7CZ09 npbes+oQFgWuBKGt2GjIen7OWybOfC7KPaSLyrXB252BYuLFDMBa9B6+Z rUmSjNQS5/nRn8xYtTz2xSRJ/2ziRG/Rm8+tEiJ/zuYZoCyQD1QZmnFxN w==; X-CSE-ConnectionGUID: QbP5QoTlTPilSlYKCz5csw== X-CSE-MsgGUID: zcpPtxk2RJugE+TTZD4nVQ== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="17267448" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:30:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:30:15 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:30:12 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel Subject: [PATCH v4 32/39] power: reset: at91-reset: add sdhwc support for sam9x7 SoC Date: Fri, 23 Feb 2024 23:00:10 +0530 Message-ID: <20240223173010.673231-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel --- Changes in v4: - Updated Acked-by tag --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index e3ebebc1f80d..dafb0126f683 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET config POWER_RESET_AT91_SAMA5D2_SHDWC tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" depends on ARCH_AT91 - default SOC_SAM9X60 || SOC_SAMA5 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports the alternate shutdown controller for some Atmel SAMA5 SoCs. It is present for example on SAMA5D2 SoC. --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21D461420B9; Fri, 23 Feb 2024 17:30:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709427; cv=none; b=sPi6GT97PkDNWqUYannIcYWxIwGFgsYEqmdpHXj7DJOTF9qfrxf+Y29P7N1uQjg60DF5BgOoFw0gl2UivZ6nFG0w/QzlIfqyNfJ/k2WUHZXCRcbPFmlIkbVcSrnoIdMZhTkGjE5n5+pZljVWAxzcIKaBYFCTuybJRGWx89uDkiY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709427; c=relaxed/simple; bh=Xx2zZ9i9EIHbEar9eU5E/skr6kuP4647DfkLBbEDqwM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=II3189OXia9yYmiu22324IA0n1pQ+0aDcc/w0bebw6CQloCQeinPkfKhoYpk0NSzwAq/rDLeFF1vD7Ce3N+teJADa7Bo4ou67bwKa6GetEdgYdwdFNf3rLX1cXYjZmacg9nCjulLru7cpPeI5ZS84LZCcNPEgtDd0nnFghB9uuY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=syyMWUX5; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="syyMWUX5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709426; x=1740245426; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xx2zZ9i9EIHbEar9eU5E/skr6kuP4647DfkLBbEDqwM=; b=syyMWUX51eCR8k+I/moTPXBRNrJeoblqG5SUP6Etd4lYE2F+8v6ftbv8 VbVjEeQFbq1Vwjws0+FMg0KAf38z6buix1EcqO8XbuqvrwADBpFM0ZBIo jiFN1hx8bgobNeCXAvRdNEWzq23pVV1wIm5vNqIfiSNhziLRSS50QlGCd cDQeoUozI9bx/0qIq/y0BWT13YH8J4o9i140BICm0PZ4umbFr3A1/bXiU Li0OcZIoc4b67t+UPR0nGbOYb5OsC348ab6n/1vzF1tsU1yD1r5gwb0z5 0fnbokAlOCQu57uXHufTbsZ94WvM555xeuAxus0YcQRkaOujlfQomyRrL g==; X-CSE-ConnectionGUID: QbP5QoTlTPilSlYKCz5csw== X-CSE-MsgGUID: l142dJI0QKOIJtky/VH7FQ== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="17267453" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:30:24 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:30:22 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:30:18 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v4 33/39] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 Date: Fri, 23 Feb 2024 23:00:15 +0530 Message-ID: <20240223173015.673281-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for SAM9X7 reset controller. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Philipp Zabel --- Changes in v4: - Updated Acked-by and Reviewed-by tags. --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-rese= t.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.ya= ml index 98465d26949e..c3b33bbc7319 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -26,6 +26,10 @@ properties: - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc =20 reg: minItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC8C012D77A; Fri, 23 Feb 2024 17:30:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709441; cv=none; b=dH1K3vM+JsUJr/VabW7TmnKNJ7CXJhl7+W7tjbQmoXWEmOOXPzehHo/46Maefw307HE1vgpURVU6TVgmYGeWhbO2NKYDRuacYg1i7UuXnMIqAkjmYLcPL1/iDKK5XTl650Me+i/L5OaV5fPAK8HbqjHagWuvKHPwmKnqmzcThRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709441; c=relaxed/simple; bh=cYlBxp5NBE+Wc9M1WxlfVZ7eP5k9B5chPb5kAuyh3Jw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FRZy90D9CZTKRmaZnSIWURQ5beMo+vFKcsFqJs6x1+XiCM7bxqkeSVmjFdhgPscoDQ3NFL1vQTU6bUaIdlwcoDwcVobRodvUw1zquFEvfnyyNk0UZ6Mw/tL3yu8luPegVKfuMgsNuT+EVGg/pFayXnt1iEePX3VkpWC/ukdB3gI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=wujqctl4; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wujqctl4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709440; x=1740245440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cYlBxp5NBE+Wc9M1WxlfVZ7eP5k9B5chPb5kAuyh3Jw=; b=wujqctl4vpWtSJxoOTElla16lhYfwV6A1GFM6se1eIqVbr8WiST1X9nD n5OZNAgmnqsiWRj5x6Ju10fai+CpI702VLpfB9ZHbzazamM4Jk9qFrssZ HN9cDNSUWYaDYsY0+i3SMEdOw4jAt3tiC0APygqMLlduJ8cVg9gpVvfUj bJ06cA7gLtTid+LwtpXPMk+p7YgRkCPoJ0usXh7pmpqQXgcGJV7qBhZUo cvHJOymSfOdH2hjsW+Ogkp4qtAcKxTpBMe12eF3kaDTt3E01r0kFknGUP hD1/c367ext5TPNWO/jTh/DGIF8Ks19uw2a84/Yl5yZrLMGNZyaD0DZU3 g==; X-CSE-ConnectionGUID: WsimkxkcQRiUq4IidYZ/ag== X-CSE-MsgGUID: h1jsnocJSfSFWYgiuCMAJA== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16734771" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:30:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:30:34 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:30:29 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: , Krzysztof Kozlowski , Sebastian Reichel Subject: [PATCH v4 34/39] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7 Date: Fri, 23 Feb 2024 23:00:23 +0530 Message-ID: <20240223173023.673336-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller DT bindings. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Sebastian Reichel --- Changes in v4: - Updated Acked-by and Reviewed-by tags --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-sh= dwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdw= c.yaml index 8c58e12cdb60..0735ceb7c103 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -22,6 +22,9 @@ properties: - enum: - atmel,sama5d2-shdwc - microchip,sam9x60-shdwc + - items: + - const: microchip,sam9x7-shdwc + - const: microchip,sam9x60-shdwc =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C07C41E503 for ; Fri, 23 Feb 2024 17:31:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709462; cv=none; b=dhF7PcbM7alzwVysdQOsVatuaSjJYuIFDH6WWAwv6GNjN3fLM6KOD06ja/78svIOqAQrFq/COg/sylUhpjeeg/al3xOSkDbmHKbA6upHU+jHELl+Us6HQ9L5D3KOIUh/XxdU/hXPlW2Et6WbCqxt680et9eKoEHv7N4WAl7+/oQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709462; c=relaxed/simple; bh=t9dKh9T4aJJEvoGpdURGgQeg5Pzq3ZcMhMvCMwkgFxs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Evv1Fx6OE9zxNcB6xV9wrdLXyHSNYd3WYGnBab6pTqSiEimAZPZqr3Cvqne0djxJGS4FxFWZ4Hm7Mvcn1AUtIXwUrK0eYl2jX2BuUqIoihSglTZryjCosFezp0ZftxqrfSrORRDP9Fm5HpC3FH21XVFP3jwTaAoid5NmTVR0GHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=cUiKWfYJ; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="cUiKWfYJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709460; x=1740245460; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t9dKh9T4aJJEvoGpdURGgQeg5Pzq3ZcMhMvCMwkgFxs=; b=cUiKWfYJZdwJ7yGDX4FW/4Tp+GA+zJarBdvrp6CkQaxaYLjwZHhHrqIc q4vifjZ2Z64sNyJZuadZVbmDLUPcCNUB53xJtspnqqNTW4Ha6+h2P9OR/ tbuaVLgoGdAyKQNXEgk201xVHShL+9XTsrFTbVJKHYGBIeRtxJ3/qBdGZ 8OVYm14d7HoalyGPF4PhjxPI4etyp0mdB2VOlcQLfl6H85RV+nh6pD1E4 qrMMefBMNjeAAI3W7WbI3Giyx2tq49165yY+Dn4iLMQWMHwa2tiznIFgy BQtBkv4Y88JyXLJz/AekBLldRVgQOFkQiaLSAtaU/uRe0vZfnHEhOGiem Q==; X-CSE-ConnectionGUID: iWPxecE1SSGsHJTwRfxMTQ== X-CSE-MsgGUID: 5fd07XWQSYm5Sx0H3/bC/A== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="16734799" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:31:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:30:42 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:30:39 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v4 35/39] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Date: Fri, 23 Feb 2024 23:00:35 +0530 Message-ID: <20240223173035.673386-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add config flag for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v4: - Updated Reviewed-by tag --- arch/arm/mach-at91/Kconfig | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a8c022b4c053..49d38a3a47de 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -141,11 +141,28 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC =20 +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select ATMEL_SDRAMC + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" =20 config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -155,7 +172,7 @@ config ATMEL_CLOCKSOURCE_PIT =20 config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SO= C_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a @@ -166,7 +183,7 @@ config ATMEL_CLOCKSOURCE_TCB =20 config MICROCHIP_CLOCKSOURCE_PIT64B bool "64-bit Periodic Interval Timer (PIT64B) support" - default SOC_SAM9X60 || SOC_SAMA7 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 select MICROCHIP_PIT64B help Select this to get a high resolution clockevent (SAM9X60) or --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3BD71E503 for ; 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charset="utf-8" Enable config flags for SAM9X7 SoC for the sam9x7 SoC family. Signed-off-by: Varshini Rajendran --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index 1d53aec4c836..880f0c0f4cc3 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_AT91=3Dy CONFIG_SOC_AT91RM9200=3Dy CONFIG_SOC_AT91SAM9=3Dy CONFIG_SOC_SAM9X60=3Dy +CONFIG_SOC_SAM9X7=3Dy # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=3Dy CONFIG_UACCESS_WITH_MEMCPY=3Dy --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68DE212CD95; Fri, 23 Feb 2024 17:31:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709475; cv=none; b=UqoIcEPsHnQ7q5AWHTMCq1MXVbRNVU43IdxBE3ewBXLE68EXyhpxTdjGrm5Ho2xYBTu0B73Jthn5Xr2inFT+Pv2riyDNxOHF07qJ0sbVUB+fNKYVe6kUeRqvuOWabpKzV8QqLdUVBw/kVgKndIHhS5PMcYnI6LItfmcS5s6HFIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709475; c=relaxed/simple; bh=BCaSQY2WoNEMZ6Zsf2lTcrqJLQXnpQAbcQzag5jdoI0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YIAsUf54UF54X8tF+6yyUdNheGojZnmNLwg56ziYmwaPCtv0I1S5JuuZ2relMq3eGx6xCYqsas+cqpopwHLku743FG2BlFmwmzN/2nRdHaHkIbda0QitF2QvCMAvsK82d1/pqeJoMjQZbHPqwdImHUByl9jpiPJ88Dj1Hk0bpOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=BQdfFnjL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="BQdfFnjL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709472; x=1740245472; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=BCaSQY2WoNEMZ6Zsf2lTcrqJLQXnpQAbcQzag5jdoI0=; b=BQdfFnjLwNZOXJDudkuuc2/9lS5hMCC1y2x4cE5y4TNkoMPG8Jpv35Kk yF6bXnejWFPu/zyB1Z9+KBt67wCfQUoY3/uA2p+qwhWCVrO09RONVzYdQ HgCjgDVStG1PD+etGU18HQGfUbyCzksZntWqIEL6BSc/1Zc6RGgFV3unx QhiGHN+3ReLgs2Pg8+XtODgOYBPYxNM3CLyyLAIqbkDc9oBDLI5vng0iN C4SaJRpciff/0cLp7fD4i1t0jFbQ7zEzjNH2Kr8Crv++naYzW8C7gGwGR c8UY4OD+Jk14TRMlJDijQX7+yWfNyEFrkVbYga3ZUJQ4kAgO4VC0SsBZX A==; X-CSE-ConnectionGUID: HW6DC9r8Rxq9ZVuQvdhHkA== X-CSE-MsgGUID: n1IRNDTGTBiN7KlvrZuN5Q== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="18276499" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:31:10 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:30:59 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:30:57 -0700 From: Varshini Rajendran To: , , , , , , Subject: [PATCH v4 37/39] ARM: dts: at91: sam9x7: add device tree for SoC Date: Fri, 23 Feb 2024 23:00:51 +0530 Message-ID: <20240223173051.673490-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for SAM9X7 SoC family. Co-developed-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Signed-off-by: Varshini Rajendran --- Changes in v4: - Added pwm node support - Added microchip,nr-irqs to the interrupt-controller node for the driver to fetch the NIRQs - Dropped USB nodes owing to the discussion here https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=3DB= 7t+KS_kOinxaRx38=3DWxA@mail.gmail.com/ (Explained elaborartely in the cover letter) --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 1214 +++++++++++++++++++++++ 1 file changed, 1214 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/mi= crochip/sam9x7.dtsi new file mode 100644 index 000000000000..ddbeb456bb59 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -0,0 +1,1214 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + model =3D "Microchip SAM9X7 SoC"; + compatible =3D "microchip,sam9x7"; + interrupt-parent =3D <&aic>; + + aliases { + serial0 =3D &dbgu; + gpio0 =3D &pioA; + gpio1 =3D &pioB; + gpio2 =3D &pioC; + gpio3 =3D &pioD; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,arm926ej-s"; + device_type =3D "cpu"; + reg =3D <0>; + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + main_xtal: clock-mainxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + sram: sram@300000 { + compatible =3D "mmio-sram"; + reg =3D <0x300000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x300000 0x10000>; + }; + + ahb { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + sdmmc0: mmc@80000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x80000000 0x300>; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + + sdmmc1: mmc@90000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x90000000 0x300>; + interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + }; + + apb { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + flx4: flexcom@f0000000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0000000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0000000 0x800>; + status =3D "disabled"; + + uart4: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi4: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c4: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0004000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0004000 0x800>; + status =3D "disabled"; + + uart5: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi5: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c5: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible =3D "microchip,sam9x7-dma", "atmel,sama5d4-dma"; + reg =3D <0xf0008000 0x1000>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names =3D "dma_clk"; + status =3D "disabled"; + }; + + ssc: ssc@f0010000 { + compatible =3D "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; + reg =3D <0xf0010000 0x4000>; + interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names =3D "pclk"; + status =3D "disabled"; + }; + + i2s: i2s@f001c000 { + compatible =3D "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; + reg =3D <0xf001c000 0x100>; + interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names =3D "pclk", "gclk"; + status =3D "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0020000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0020000 0x800>; + status =3D "disabled"; + + uart11: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c11: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0024000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0024000 0x800>; + status =3D "disabled"; + + uart12: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c12: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0028000 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names =3D "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible =3D "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; + reg =3D <0xf002c000 0x100>; + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH 0>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names =3D "tx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names =3D "sha_clk"; + }; + + trng: rng@f0030000 { + compatible =3D "microchip,sam9x7-trng", "microchip,sam9x60-trng"; + reg =3D <0xf0030000 0x100>; + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 38>; + status =3D "disabled"; + }; + + aes: crypto@f0034000 { + compatible =3D "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; + reg =3D <0xf0034000 0x100>; + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH 0>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names =3D "aes_clk"; + }; + + tdes: crypto@f0038000 { + compatible =3D "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; + reg =3D <0xf0038000 0x100>; + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH 0>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names =3D "tdes_clk"; + }; + + classd: classd@f003c000 { + compatible =3D "microchip,sam9x7-classd", "atmel,sama5d2-classd"; + reg =3D <0xf003c000 0x100>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names =3D "tx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names =3D "pclk", "gclk"; + status =3D "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0040000 0x100>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names =3D "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH 0 + 68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 2= 9>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x3400 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + can1: can@f8004000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <30 IRQ_TYPE_LEVEL_HIGH 0 + 69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 3= 0>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x7800 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + tcb: timer@f8008000 { + compatible =3D "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd"= , "syscon"; + reg =3D <0xf8008000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk= 32k 0>; + clock-names =3D "t0_clk", "gclk", "slow_clk"; + status =3D "disabled"; + }; + + flx6: flexcom@f8010000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8010000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8010000 0x800>; + status =3D "disabled"; + + uart6: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c6: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8014000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8014000 0x800>; + status =3D "disabled"; + + uart7: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8018000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8018000 0x800>; + status =3D "disabled"; + + uart8: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c8: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf801c000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf801c000 0x800>; + status =3D "disabled"; + + uart0: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c0: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8020000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8020000 0x800>; + status =3D "disabled"; + + uart1: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8024000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8024000 0x800>; + status =3D "disabled"; + + uart2: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8028000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8028000 0x800>; + status =3D "disabled"; + + uart3: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible =3D "microchip,sam9x7-gem", "microchip,sama7g5-gem" ; + reg =3D <0xf802c000 0x1000>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ + 60 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ + 61 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 2 */ + 62 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 3 */ + 63 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 4 */ + 64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>= , <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; + clock-names =3D "hclk", "pclk", "tx_clk", "tsu_clk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 67>; + status =3D "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible =3D "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; + reg =3D <0xf8034000 0x300>; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 18>; + #pwm-cells =3D <3>; + status=3D "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8040000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8040000 0x800>; + status =3D "disabled"; + + uart9: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c9: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8044000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8044000 0x800>; + status =3D "disabled"; + + uart10: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c10: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + sfr: sfr@f8050000 { + compatible =3D "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon= "; + reg =3D <0xf8050000 0x100>; + }; + + matrix: matrix@ffffde00 { + compatible =3D "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "s= yscon"; + reg =3D <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible =3D "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; + reg =3D <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible =3D "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; + reg =3D <0xffffe800 0x200>; + clocks =3D <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names =3D "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible =3D "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon= "; + reg =3D <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible =3D "microchip,sam9x7-aic", "microchip,sam9x60-aic"; + reg =3D <0xfffff100 0x100>; + #interrupt-cells =3D <3>; + interrupt-controller; + atmel,external-irqs =3D <31>; + microchip,nr-irqs =3D <70>; + }; + + dbgu: serial@fffff200 { + compatible =3D "microchip,sam9x7-dbgu", "microchip,sam9x7-usart", "atme= l,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0xfffff200 0x200>; + atmel,usart-mode =3D ; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names =3D "usart"; + status =3D "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl",= "simple-mfd"; + ranges =3D <0xfffff400 0xfffff400 0x800>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask =3D < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f80 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff400 0x200>; + interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff600 0x200>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <26>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff800 0x200>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffffa00 0x200>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <22>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible =3D "microchip,sam9x7-pmc", "syscon"; + reg =3D <0xfffffc00 0x200>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells =3D <2>; + clocks =3D <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names =3D "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible =3D "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; + reg =3D <0xfffffe00 0x10>; + clocks =3D <&clk32k 0>; + }; + + power_management: power-management@fffffe10 { + compatible =3D "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; + reg =3D <0xfffffe10 0x10>; + clocks =3D <&clk32k 0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status =3D "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible =3D "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; + reg =3D <0xfffffe20 0x20>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + clk32k: sckc@fffffe50 { + compatible =3D "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; + reg =3D <0xfffffe50 0x4>; + clocks =3D <&slow_xtal>; + #clock-cells =3D <1>; + }; + + gpbr: syscon@fffffe60 { + compatible =3D "microchip,sam9x7-gbpr", "atmel,at91sam9260-gpbr", "sysc= on"; + reg =3D <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible =3D "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; + reg =3D <0xfffffea8 0x100>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible =3D "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; + reg =3D <0xffffff80 0x24>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 224811339B6; Fri, 23 Feb 2024 17:31:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; 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charset="utf-8" Add documentation for SAM9X75 Curiosity board. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Docume= ntation/devicetree/bindings/arm/atmel-at91.yaml index 89d75fbb1de4..d74d3a4701ac 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -106,6 +106,12 @@ properties: - const: microchip,sam9x60 - const: atmel,at91sam9 =20 + - description: Microchip SAM9X7 Evaluation Boards + items: + - const: microchip,sam9x75-curiosity + - const: microchip,sam9x7 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 --=20 2.25.1 From nobody Fri Dec 19 17:36:15 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D8EB12D763; Fri, 23 Feb 2024 17:31:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709491; cv=none; b=PlNLKs/2TKoHbTGjPtpUMvG9fMMn0bvBoqGwpTWsOrdLx3Tl/yXTVdm8xm7MP4E5TdQG/w35BHBrUFM/V7JX+psa6LOf6ckMe8VWMDjvCIaaJ99RNhl8uyckM6EaGlC4R7M0XgdHCQORyi6ni7EpFbWfS51gE0INKxDklGXZwuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708709491; c=relaxed/simple; bh=Z1LIIhp3DdCr6uVt0lYpOJ62r9L9VOMxLwm9s8WfSCM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YAA2RT4GXIFoKykmtYb0iFHaSvEbMntbrp5g78ZpjgB71AnpdtiG0l8s/98ozN5TjfBdAKBroSrOtE7kA/2FQ6M0PbK62mw8Jv9pHfJ2s8y8I+szcO3SJp+CUyRVdme5zsBB0XVbbV/i2VhP1Zmhs/DZV20pkq6eu5cXwZ6kWNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Yyz/3AH9; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Yyz/3AH9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708709490; x=1740245490; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Z1LIIhp3DdCr6uVt0lYpOJ62r9L9VOMxLwm9s8WfSCM=; b=Yyz/3AH9DtaABAob1NiEBG8fx8mtzftTFaXd2QAlM5PT45xmRSsG+m1H bvwmKKRojyFqZZoff/AH1OkuMGUEjmiPsK4bknKzQOXqh5X/cigiWxJKo i95M9QeAsXlPOLx2V9VwiQgy+C0LxfJrEnGPCmCUda6frMPVDs7RuDnSF Yk107QcKWyijer3hUBJIWUfOo/IHMhTaJBHk8XO2pHNONC5oQpzc5sbZC vRUMKSY5l8FyNQfBthSnU6K6Y8eVg3df60NTLuzTk7k9EBNPUw/6E+jqY e0BQAm+gMarwHEVbg4uaoEtWSm1KfDNv1BiD0K9MgUPQSIzA/lNc1uHej w==; X-CSE-ConnectionGUID: PANU8h+pSKGuucnF8SuIjA== X-CSE-MsgGUID: mMuWETYZTSazwK3yGcOyIw== X-IronPort-AV: E=Sophos;i="6.06,180,1705388400"; d="scan'208";a="184009809" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2024 10:31:29 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 23 Feb 2024 10:31:21 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 23 Feb 2024 10:31:16 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , Subject: [PATCH v4 39/39] ARM: dts: at91: sam9x75_curiosity: add sam9x75 curiosity board Date: Fri, 23 Feb 2024 23:01:13 +0530 Message-ID: <20240223173113.673595-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240223171342.669133-1-varshini.rajendran@microchip.com> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for sam9x75 curiosity board. Signed-off-by: Varshini Rajendran --- Changes in v4: - Removed full node paths - Renamed Leds with color names - Corrected regulator node names - Added support for classd and i2s nodes and their corresponding pinctrl nodes - Dropped USB nodes owing to the discussion here https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=3DB7= t+KS_kOinxaRx38=3DWxA@mail.gmail.com/ (Explained elaborately in the cover letter) - Updated the linux,code property with the necessary value --- arch/arm/boot/dts/microchip/Makefile | 3 + .../dts/microchip/at91-sam9x75_curiosity.dts | 309 ++++++++++++++++++ 2 files changed, 312 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/micro= chip/Makefile index efde9546c8f4..5b3d518da319 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -12,6 +12,7 @@ DTC_FLAGS_at91-sama5d3_eds :=3D -@ DTC_FLAGS_at91-sama5d3_xplained :=3D -@ DTC_FLAGS_at91-sama5d4_xplained :=3D -@ DTC_FLAGS_at91-sama7g5ek :=3D -@ +DTC_FLAGS_at91-sam9x75_curiosity :=3D -@ dtb-$(CONFIG_SOC_AT91RM9200) +=3D \ at91rm9200ek.dtb \ mpa1600.dtb @@ -59,6 +60,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) +=3D \ dtb-$(CONFIG_SOC_SAM9X60) +=3D \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +dtb-$(CONFIG_SOC_SAM9X7) +=3D \ + at91-sam9x75_curiosity.dtb dtb-$(CONFIG_SOC_SAM_V7) +=3D \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/= arm/boot/dts/microchip/at91-sam9x75_curiosity.dts new file mode 100644 index 000000000000..be37022d3d05 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Cur= iosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ +/dts-v1/; +#include "sam9x7.dtsi" +#include + +/ { + model =3D "Microchip SAM9X75 Curiosity"; + compatible =3D "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,= at91sam9"; + + aliases { + i2c0 =3D &i2c6; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_key_gpio_default>; + + button-user { + label =3D "USER"; + gpios =3D <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_led_gpio_default>; + + led-red { + label =3D "red"; + gpios =3D <&pioC 19 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label =3D "green"; + gpios =3D <&pioC 21 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label =3D "blue"; + gpios =3D <&pioC 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + memory@20000000 { + device_type =3D "memory"; + reg =3D <0x20000000 0x10000000>; + }; +}; + +&classd { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_classd>; + atmel,pwm-type =3D "diff"; + atmel,non-overlap-time =3D <10>; + status =3D "okay"; +}; + +&dbgu { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dbgu>; + status =3D "okay"; +}; + +&dma0 { + status =3D "okay"; +}; + +&flx6 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&i2c6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + status =3D "okay"; + + pmic@5b { + compatible =3D "microchip,mcp16502"; + reg =3D <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name =3D "VDD_IO"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name =3D "VDD_DDR"; + regulator-min-microvolt =3D <1283000>; + regulator-max-microvolt =3D <1450000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name =3D "VDD_CORE"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1210000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name =3D "VDD_OTHER"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-ramp-delay =3D <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3700000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2s_default>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; +}; + +&main_xtal { + clock-frequency =3D <24000000>; +}; + +&pinctrl { + + classd { + pinctrl_classd: classd { + atmel,pins =3D + ; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins =3D ; + }; + }; + + flexcom { + pinctrl_flx6_default: flx6-twi { + atmel,pins =3D + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: key-gpio-default { + atmel,pins =3D ; + }; + }; + + i2s { + pinctrl_i2s_default: i2s { + atmel,pins =3D + ; /* I2SMCK */ + }; + }; + + leds { + pinctrl_led_gpio_default: led-gpio-default { + atmel,pins =3D ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0 { + atmel,pins =3D + ; /* PA5 DAT3 periph A with pullup= */ + }; + }; + +}; /* pinctrl */ + +&rtt { + atmel,rtt-rtc-time-reg =3D <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sdmmc0_default>; + cd-gpios =3D <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; + status =3D "okay"; +}; + +&slow_xtal { + clock-frequency =3D <32768>; +}; + +&power_management { + debounce-delay-us =3D <976>; + status =3D "okay"; + + input@0 { + reg =3D <0>; + }; +}; + +&trng { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.25.1