From nobody Mon Feb 9 14:15:13 2026 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EC005DF25 for ; Fri, 23 Feb 2024 10:38:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708684703; cv=none; b=fREwX9CJngV7uWNoATIYGIkKxM6cSkwP9LPKCvPbfxk/1lpCq44+p0asyCI2638LKlpksFUW4wfuXBpmfEJmFN5cJhWORGw6LQKGqADfKLw8oopE/oaflaGSvYNIRAjukU2WTL/k2fz2z37rlTzxT9uI2ekfxdRN30Svng5OUOw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708684703; c=relaxed/simple; bh=2aGsE8mFtWNm5k18rp6bVdMp20XjRknEP+SUteZ5vfo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ry3Ni0NF4ofcH09oThhpOVnMWi6uZHHVACc7vnrcR2vlpcdNc5cRD2AAGabv4YaE6UYjlIluGM+ymBVWMKgcxPHsaDO7jh9fGRnfNorTQOtzzEcdOJZ0ijOlAw16zREPQRlvBqaYG5hvfPYIIW6ZwAqcjQlNKcsfgCxGDbfXMZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Th5yc31stz2BdPS; Fri, 23 Feb 2024 18:36:08 +0800 (CST) Received: from canpemm500009.china.huawei.com (unknown [7.192.105.203]) by mail.maildlp.com (Postfix) with ESMTPS id 1385C1A016B; Fri, 23 Feb 2024 18:38:19 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 23 Feb 2024 18:38:18 +0800 From: Yicong Yang To: , , , , , CC: , , , Subject: [PATCH v2 2/8] drivers/perf: hisi_pcie: Introduce hisi_pcie_pmu_get_event_ctrl_val() Date: Fri, 23 Feb 2024 18:33:53 +0800 Message-ID: <20240223103359.18669-3-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20240223103359.18669-1-yangyicong@huawei.com> References: <20240223103359.18669-1-yangyicong@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To canpemm500009.china.huawei.com (7.192.105.203) Content-Type: text/plain; charset="utf-8" From: Yicong Yang Factor out retrieving of the register value for the corresponding event from hisi_pcie_config_event_ctrl() into a new function hisi_pcie_pmu_get_event_ctrl_val() allowing future reuse. Signed-off-by: Yicong Yang Reviewed-by: Jonathan Cameron --- drivers/perf/hisilicon/hisi_pcie_pmu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilico= n/hisi_pcie_pmu.c index 9760ddde46fd..2468cf3b007c 100644 --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -216,10 +216,8 @@ static void hisi_pcie_pmu_writeq(struct hisi_pcie_pmu = *pcie_pmu, u32 reg_offset, writeq_relaxed(val, pcie_pmu->base + offset); } =20 -static void hisi_pcie_pmu_config_event_ctrl(struct perf_event *event) +static u64 hisi_pcie_pmu_get_event_ctrl_val(struct perf_event *event) { - struct hisi_pcie_pmu *pcie_pmu =3D to_pcie_pmu(event->pmu); - struct hw_perf_event *hwc =3D &event->hw; u64 port, trig_len, thr_len, len_mode; u64 reg =3D HISI_PCIE_INIT_SET; =20 @@ -256,6 +254,15 @@ static void hisi_pcie_pmu_config_event_ctrl(struct per= f_event *event) else reg |=3D FIELD_PREP(HISI_PCIE_LEN_M, HISI_PCIE_LEN_M_DEFAULT); =20 + return reg; +} + +static void hisi_pcie_pmu_config_event_ctrl(struct perf_event *event) +{ + struct hisi_pcie_pmu *pcie_pmu =3D to_pcie_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + u64 reg =3D hisi_pcie_pmu_get_event_ctrl_val(event); + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg); } =20 --=20 2.24.0