From nobody Sun Feb 8 05:23:15 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 99D0A5DF01 for ; Fri, 23 Feb 2024 09:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708681587; cv=none; b=VIZMnSZlpUP/eLERx7KRdYgxmOtxlVdyf8uByY3UQjP6AXbRItSlsoJSxCMKVHpsFsibQixYt7SPMq+37XhF4Pv+9z7VPl/955Ak4LT0XzTKKltoGFbaGvUnneI5ZoZxAnq1jrTwuLaoS2JSSoB+mRmF7/+oZonGRcvnWsHHGM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708681587; c=relaxed/simple; bh=uowSVM2SjzNXmtHjgIgF2ExRHxtW4sAgUT7RZkJdK9o=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=SXoLPmvMCdSfcnW1iz3br3NjhSM0wEVTfGxFhkDiuLKYfJc0CWxKqvyUts47eLoHpxABqweV9kCK7rwZ/5V9NeM9NZ1PaPIOCNbjUkp6iuB42eadmPnR5AhUfr66IQy6f8WCitRH6et4D0gKDr5D/X2ALbmnBBKbKtNHixNxaC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 240221596; Fri, 23 Feb 2024 01:47:02 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.46.223]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E9F2F3F766; Fri, 23 Feb 2024 01:46:20 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: broonie@kernel.org, Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Rutland , linux-kernel@vger.kernel.org Subject: [PATCH] arm64/hw_breakpoint: Define an ISS code for watchpoint exception Date: Fri, 23 Feb 2024 15:16:15 +0530 Message-Id: <20240223094615.3977323-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This defines a new ISS code macro i.e ESR_ELx_WnR for watchpoint exception. This represents an instruction's either writing to or reading from a memory location during an watchpoint exception, and also moves this macro into the ESR header as required. This drops non-standard AARCH64_ESR_ACCESS_MASK. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mark Brown --- This applies on v6.8-rc5 arch/arm64/include/asm/esr.h | 4 ++++ arch/arm64/include/asm/hw_breakpoint.h | 1 - arch/arm64/kernel/hw_breakpoint.c | 3 ++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 353fe08546cf..6c0a0b77fd2c 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -143,6 +143,10 @@ #define ESR_ELx_CM_SHIFT (8) #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) =20 +/* ISS field definitions for Watchpoint exception */ +#define ESR_ELx_WnR_SHIFT (6) +#define ESR_ELx_WnR (UL(1) << ESR_ELx_WnR_SHIFT) + /* ISS2 field definitions for Data Aborts */ #define ESR_ELx_TnD_SHIFT (10) #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/as= m/hw_breakpoint.h index d67c02e53a4a..6e4862e3d238 100644 --- a/arch/arm64/include/asm/hw_breakpoint.h +++ b/arch/arm64/include/asm/hw_breakpoint.h @@ -67,7 +67,6 @@ static inline void decode_ctrl_reg(u32 reg, /* Watchpoints */ #define ARM_BREAKPOINT_LOAD 1 #define ARM_BREAKPOINT_STORE 2 -#define AARCH64_ESR_ACCESS_MASK (1 << 6) =20 /* Lengths */ #define ARM_BREAKPOINT_LEN_1 0x1 diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index 86bdb2d68732..a73364a18c69 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -21,6 +21,7 @@ =20 #include #include +#include #include #include #include @@ -792,7 +793,7 @@ static int watchpoint_handler(unsigned long addr, unsig= ned long esr, * Check that the access type matches. * 0 =3D> load, otherwise =3D> store */ - access =3D (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W : + access =3D (esr & ESR_ELx_WnR) ? HW_BREAKPOINT_W : HW_BREAKPOINT_R; if (!(access & hw_breakpoint_type(wp))) continue; --=20 2.25.1